X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farmv7a.h;h=0ef04c162abf36fbb684a6b508f75bb9641b4c56;hp=6a62f72c6cc0240d0cf85540e3988c479d123592;hb=HEAD;hpb=d1bdcdcc8d429a2ce06fb35f82a67b2487b72ec3

diff --git a/src/target/armv7a.h b/src/target/armv7a.h
index 6a62f72c6c..8943f1c697 100644
--- a/src/target/armv7a.h
+++ b/src/target/armv7a.h
@@ -1,18 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
 /***************************************************************************
  *    Copyright (C) 2009 by David Brownell                                 *
- *                                                                         *
- *   This program is free software; you can redistribute it and/or modify  *
- *   it under the terms of the GNU General Public License as published by  *
- *   the Free Software Foundation; either version 2 of the License, or     *
- *   (at your option) any later version.                                   *
- *                                                                         *
- *   This program is distributed in the hope that it will be useful,       *
- *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
- *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
- *   GNU General Public License for more details.                          *
- *                                                                         *
- *   You should have received a copy of the GNU General Public License     *
- *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  ***************************************************************************/
 
 #ifndef OPENOCD_TARGET_ARMV7A_H
@@ -30,7 +19,7 @@ enum {
 	ARM_CPSR = 16
 };
 
-#define ARMV7_COMMON_MAGIC 0x0A450999
+#define ARMV7_COMMON_MAGIC 0x0A450999U
 
 /* VA to PA translation operations opc2 values*/
 #define V2PCWPR  0
@@ -48,8 +37,7 @@ struct armv7a_l2x_cache {
 };
 
 struct armv7a_cachesize {
-	uint32_t level_num;
-	/*  cache dimensionning */
+	/*  cache dimensioning */
 	uint32_t linelen;
 	uint32_t associativity;
 	uint32_t nsets;
@@ -77,8 +65,6 @@ struct armv7a_cache_common {
 	struct armv7a_arch_cache arch[6];	/* cache info, L1 - L7 */
 	int i_cache_enabled;
 	int d_u_cache_enabled;
-	int auto_cache_enabled;			/* openocd automatic
-						 * cache handling */
 	/* outer unified cache if some */
 	void *outer_cache;
 	int (*flush_all_data_cache)(struct target *target);
@@ -88,28 +74,30 @@ struct armv7a_mmu_common {
 	/* following field mmu working way */
 	int32_t cached;     /* 0: not initialized, 1: initialized */
 	uint32_t ttbcr;     /* cache for ttbcr register */
+	uint32_t ttbr[2];
 	uint32_t ttbr_mask[2];
 	uint32_t ttbr_range[2];
 
-	int (*read_physical_memory)(struct target *target, uint32_t address, uint32_t size,
+	int (*read_physical_memory)(struct target *target, target_addr_t address, uint32_t size,
 			uint32_t count, uint8_t *buffer);
 	struct armv7a_cache_common armv7a_cache;
 	uint32_t mmu_enabled;
 };
 
 struct armv7a_common {
+	unsigned int common_magic;
+
 	struct arm arm;
-	int common_magic;
 	struct reg_cache *core_cache;
 
 	/* Core Debug Unit */
 	struct arm_dpm dpm;
-	uint32_t debug_base;
+	target_addr_t debug_base;
 	struct adiv5_ap *debug_ap;
-	struct adiv5_ap *memory_ap;
-	bool memory_ap_available;
 	/* mdir */
 	uint8_t multi_processor_system;
+	uint8_t multi_threading_processor;
+	uint8_t level2_id;
 	uint8_t cluster_id;
 	uint8_t cpu_id;
 	bool is_armv7r;
@@ -178,6 +166,9 @@ static inline bool is_armv7a(struct armv7a_common *armv7a)
 /* See ARMv7a arch spec section C10.8 */
 #define CPUDBG_AUTHSTATUS	0xFB8
 
+/* See ARMv7a arch spec DDI 0406C C11.10 */
+#define CPUDBG_ID_PFR1		0xD24
+
 /* Masks for Vector Catch register */
 #define DBG_VCR_FIQ_MASK	((1 << 31) | (1 << 7))
 #define DBG_VCR_IRQ_MASK	((1 << 30) | (1 << 6))
@@ -185,15 +176,16 @@ static inline bool is_armv7a(struct armv7a_common *armv7a)
 #define DBG_VCR_PREF_ABORT_MASK	((1 << 27) | (1 << 3))
 #define DBG_VCR_SVC_MASK	((1 << 26) | (1 << 2))
 
+/* Masks for Multiprocessor Affinity Register */
+#define MPIDR_MP_EXT		(1UL << 31)
+
 int armv7a_arch_state(struct target *target);
 int armv7a_identify_cache(struct target *target);
 int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a);
-int armv7a_mmu_translate_va_pa(struct target *target, uint32_t va,
-		uint32_t *val, int meminfo);
-int armv7a_mmu_translate_va(struct target *target,  uint32_t va, uint32_t *val);
 
-int armv7a_handle_cache_info_command(struct command_context *cmd_ctx,
+int armv7a_handle_cache_info_command(struct command_invocation *cmd,
 		struct armv7a_cache_common *armv7a_cache);
+int armv7a_read_ttbcr(struct target *target);
 
 extern const struct command_registration armv7a_command_handlers[];