X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farmv7a.c;h=eecfa70976af0ed0ff3ca50788965701c6af0796;hp=37eb1b5f1b2ab31cc326138fe42293456c6cd2b0;hb=42097baf19d4459a57f5224506e59a8347740f19;hpb=d0e763ac7ef6aa17b17bd00ccdfbccfb4eacda69

diff --git a/src/target/armv7a.c b/src/target/armv7a.c
index 37eb1b5f1b..eecfa70976 100644
--- a/src/target/armv7a.c
+++ b/src/target/armv7a.c
@@ -124,14 +124,18 @@ done:
 	return retval;
 }
 
-static int armv7a_read_ttbcr(struct target *target)
+int armv7a_read_ttbcr(struct target *target)
 {
 	struct armv7a_common *armv7a = target_to_armv7a(target);
 	struct arm_dpm *dpm = armv7a->arm.dpm;
 	uint32_t ttbcr, ttbcr_n;
-	int retval = dpm->prepare(dpm);
+	int ttbidx;
+	int retval;
+
+	retval = dpm->prepare(dpm);
 	if (retval != ERROR_OK)
 		goto done;
+
 	/*  MRC p15,0,<Rt>,c2,c0,2 ; Read CP15 Translation Table Base Control Register*/
 	retval = dpm->instr_read_data_r0(dpm,
 			ARMV4_5_MRC(15, 0, 0, 2, 0, 2),
@@ -145,6 +149,15 @@ static int armv7a_read_ttbcr(struct target *target)
 	armv7a->armv7a_mmu.ttbcr = ttbcr;
 	armv7a->armv7a_mmu.cached = 1;
 
+	for (ttbidx = 0; ttbidx < 2; ttbidx++) {
+		/*  MRC p15,0,<Rt>,c2,c0,ttbidx */
+		retval = dpm->instr_read_data_r0(dpm,
+				ARMV4_5_MRC(15, 0, 0, 2, 0, ttbidx),
+				&armv7a->armv7a_mmu.ttbr[ttbidx]);
+		if (retval != ERROR_OK)
+			goto done;
+	}
+
 	/*
 	 * ARM Architecture Reference Manual (ARMv7-A and ARMv7-Redition),
 	 * document # ARM DDI 0406C
@@ -182,42 +195,21 @@ int armv7a_mmu_translate_va(struct target *target,  uint32_t va, uint32_t *val)
 	uint32_t second_lvl_descriptor = 0x0;
 	int retval;
 	struct armv7a_common *armv7a = target_to_armv7a(target);
-	struct arm_dpm *dpm = armv7a->arm.dpm;
 	uint32_t ttbidx = 0;	/*  default to ttbr0 */
 	uint32_t ttb_mask;
 	uint32_t va_mask;
-	uint32_t ttbcr;
 	uint32_t ttb;
 
-	retval = dpm->prepare(dpm);
-	if (retval != ERROR_OK)
-		goto done;
-
-	/*  MRC p15,0,<Rt>,c2,c0,2 ; Read CP15 Translation Table Base Control Register*/
-	retval = dpm->instr_read_data_r0(dpm,
-			ARMV4_5_MRC(15, 0, 0, 2, 0, 2),
-			&ttbcr);
-	if (retval != ERROR_OK)
-		goto done;
-
-	/* if ttbcr has changed or was not read before, re-read the information */
-	if ((armv7a->armv7a_mmu.cached == 0) ||
-		(armv7a->armv7a_mmu.ttbcr != ttbcr)) {
-		armv7a_read_ttbcr(target);
-	}
+	if (target->state != TARGET_HALTED)
+		LOG_INFO("target not halted, using cached values for translation table!");
 
 	/* if va is above the range handled by ttbr0, select ttbr1 */
 	if (va > armv7a->armv7a_mmu.ttbr_range[0]) {
 		/*  select ttb 1 */
 		ttbidx = 1;
 	}
-	/*  MRC p15,0,<Rt>,c2,c0,ttbidx */
-	retval = dpm->instr_read_data_r0(dpm,
-			ARMV4_5_MRC(15, 0, 0, 2, 0, ttbidx),
-			&ttb);
-	if (retval != ERROR_OK)
-		return retval;
 
+	ttb = armv7a->armv7a_mmu.ttbr[ttbidx];
 	ttb_mask = armv7a->armv7a_mmu.ttbr_mask[ttbidx];
 	va_mask = 0xfff00000 & armv7a->armv7a_mmu.ttbr_range[ttbidx];
 
@@ -279,9 +271,6 @@ int armv7a_mmu_translate_va(struct target *target,  uint32_t va, uint32_t *val)
 	}
 
 	return ERROR_OK;
-
-done:
-	return retval;
 }
 
 /*  V7 method VA TO PA  */
@@ -355,7 +344,7 @@ int armv7a_mmu_translate_va_pa(struct target *target, uint32_t va,
 				break;
 			case 7:
 				LOG_INFO("inner: Write-Back, no Write-Allocate");
-
+				break;
 			default:
 				LOG_INFO("inner: %" PRIx32 " ???", INNER);
 		}
@@ -565,9 +554,6 @@ int armv7a_identify_cache(struct target *target)
 	struct armv7a_cache_common *cache =
 		&(armv7a->armv7a_mmu.armv7a_cache);
 
-	if (!armv7a->is_armv7r)
-		armv7a_read_ttbcr(target);
-
 	retval = dpm->prepare(dpm);
 	if (retval != ERROR_OK)
 		goto done;
@@ -679,11 +665,40 @@ done:
 
 }
 
+static int armv7a_setup_semihosting(struct target *target, int enable)
+{
+	struct armv7a_common *armv7a = target_to_armv7a(target);
+	uint32_t vcr;
+	int ret;
+
+	ret = mem_ap_read_atomic_u32(armv7a->debug_ap,
+					 armv7a->debug_base + CPUDBG_VCR,
+					 &vcr);
+	if (ret < 0) {
+		LOG_ERROR("Failed to read VCR register\n");
+		return ret;
+	}
+
+	if (enable)
+		vcr |= DBG_VCR_SVC_MASK;
+	else
+		vcr &= ~DBG_VCR_SVC_MASK;
+
+	ret = mem_ap_write_atomic_u32(armv7a->debug_ap,
+					  armv7a->debug_base + CPUDBG_VCR,
+					  vcr);
+	if (ret < 0)
+		LOG_ERROR("Failed to write VCR register\n");
+
+	return ret;
+}
+
 int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a)
 {
 	struct arm *arm = &armv7a->arm;
 	arm->arch_info = armv7a;
 	target->arch_info = &armv7a->arm;
+	arm->setup_semihosting = armv7a_setup_semihosting;
 	/*  target is useful in all function arm v4 5 compatible */
 	armv7a->arm.target = target;
 	armv7a->arm.common_magic = ARM_COMMON_MAGIC;
@@ -756,9 +771,6 @@ const struct command_registration l2x_cache_command_handlers[] = {
 };
 
 const struct command_registration armv7a_command_handlers[] = {
-	{
-		.chain = dap_command_handlers,
-	},
 	{
 		.chain = l2x_cache_command_handlers,
 	},