X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farmv7a.c;h=eecfa70976af0ed0ff3ca50788965701c6af0796;hp=06bc748984c4c8eac129720dcca2fe810af94be7;hb=42097baf19d4459a57f5224506e59a8347740f19;hpb=55eeea7fceb67f29c9a43eeb7993c70214157343
diff --git a/src/target/armv7a.c b/src/target/armv7a.c
index 06bc748984..eecfa70976 100644
--- a/src/target/armv7a.c
+++ b/src/target/armv7a.c
@@ -1,6 +1,8 @@
/***************************************************************************
* Copyright (C) 2009 by David Brownell *
* *
+ * Copyright (C) ST-Ericsson SA 2011 michel.jaouen@stericsson.com *
+ * *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
@@ -12,33 +14,35 @@
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ * along with this program. If not, see . *
***************************************************************************/
+
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
-#include "replacements.h"
+#include
#include "armv7a.h"
#include "arm_disassembler.h"
#include "register.h"
-#include "binarybuffer.h"
-#include "command.h"
+#include
+#include
#include
#include
#include
+#include "arm_opcodes.h"
+#include "target.h"
+#include "target_type.h"
static void armv7a_show_fault_registers(struct target *target)
{
uint32_t dfsr, ifsr, dfar, ifar;
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct arm_dpm *dpm = armv7a->armv4_5_common.dpm;
+ struct arm_dpm *dpm = armv7a->arm.dpm;
int retval;
retval = dpm->prepare(dpm);
@@ -74,154 +78,704 @@ static void armv7a_show_fault_registers(struct target *target)
goto done;
LOG_USER("Data fault registers DFSR: %8.8" PRIx32
- ", DFAR: %8.8" PRIx32, dfsr, dfar);
+ ", DFAR: %8.8" PRIx32, dfsr, dfar);
LOG_USER("Instruction fault registers IFSR: %8.8" PRIx32
- ", IFAR: %8.8" PRIx32, ifsr, ifar);
+ ", IFAR: %8.8" PRIx32, ifsr, ifar);
done:
/* (void) */ dpm->finish(dpm);
}
-int armv7a_arch_state(struct target *target)
+
+/* retrieve main id register */
+static int armv7a_read_midr(struct target *target)
{
- static const char *state[] =
- {
- "disabled", "enabled"
- };
+ int retval = ERROR_FAIL;
+ struct armv7a_common *armv7a = target_to_armv7a(target);
+ struct arm_dpm *dpm = armv7a->arm.dpm;
+ uint32_t midr;
+ retval = dpm->prepare(dpm);
+ if (retval != ERROR_OK)
+ goto done;
+ /* MRC p15,0,,c0,c0,0; read main id register*/
+
+ retval = dpm->instr_read_data_r0(dpm,
+ ARMV4_5_MRC(15, 0, 0, 0, 0, 0),
+ &midr);
+ if (retval != ERROR_OK)
+ goto done;
+ armv7a->rev = (midr & 0xf);
+ armv7a->partnum = (midr >> 4) & 0xfff;
+ armv7a->arch = (midr >> 16) & 0xf;
+ armv7a->variant = (midr >> 20) & 0xf;
+ armv7a->implementor = (midr >> 24) & 0xff;
+ LOG_INFO("%s rev %" PRIx32 ", partnum %" PRIx32 ", arch %" PRIx32
+ ", variant %" PRIx32 ", implementor %" PRIx32,
+ target->cmd_name,
+ armv7a->rev,
+ armv7a->partnum,
+ armv7a->arch,
+ armv7a->variant,
+ armv7a->implementor);
+
+done:
+ dpm->finish(dpm);
+ return retval;
+}
+
+int armv7a_read_ttbcr(struct target *target)
+{
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct arm *armv4_5 = &armv7a->armv4_5_common;
+ struct arm_dpm *dpm = armv7a->arm.dpm;
+ uint32_t ttbcr, ttbcr_n;
+ int ttbidx;
+ int retval;
- if (armv7a->common_magic != ARMV7_COMMON_MAGIC)
- {
- LOG_ERROR("BUG: called for a non-ARMv7A target");
- return ERROR_INVALID_ARGUMENTS;
- }
-
- LOG_USER("target halted in %s state due to %s, current mode: %s\n"
- "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
- "MMU: %s, D-Cache: %s, I-Cache: %s",
- armv4_5_state_strings[armv4_5->core_state],
- Jim_Nvp_value2name_simple(nvp_target_debug_reason,
- target->debug_reason)->name,
- arm_mode_name(armv4_5->core_mode),
- buf_get_u32(armv4_5->cpsr->value, 0, 32),
- buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
- state[armv7a->armv4_5_mmu.mmu_enabled],
- state[armv7a->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
- state[armv7a->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);
-
- if (armv4_5->core_mode == ARMV4_5_MODE_ABT)
- armv7a_show_fault_registers(target);
- else if (target->debug_reason == DBG_REASON_WATCHPOINT)
- LOG_USER("Watchpoint triggered at PC %#08x",
- (unsigned) armv7a->dpm.wp_pc);
+ retval = dpm->prepare(dpm);
+ if (retval != ERROR_OK)
+ goto done;
- return ERROR_OK;
+ /* MRC p15,0,