X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farmv7a.c;h=97ce473e5aad2bb15ef5e19eb84c4ff74edd27f6;hp=bf474d3a62f5ad30e1dba95e02ab749bf2829cec;hb=c734202dc89bb3ee05a204140b3c890451e79686;hpb=248b85a6e739c8eb107c3a278b8eac6fc1f0cf62

diff --git a/src/target/armv7a.c b/src/target/armv7a.c
index bf474d3a62..97ce473e5a 100644
--- a/src/target/armv7a.c
+++ b/src/target/armv7a.c
@@ -14,9 +14,7 @@
  *   GNU General Public License for more details.                          *
  *                                                                         *
  *   You should have received a copy of the GNU General Public License     *
- *   along with this program; if not, write to the                         *
- *   Free Software Foundation, Inc.,                                       *
- *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
+ *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  ***************************************************************************/
 
 #ifdef HAVE_CONFIG_H
@@ -26,6 +24,7 @@
 #include <helper/replacements.h>
 
 #include "armv7a.h"
+#include "armv7a_mmu.h"
 #include "arm_disassembler.h"
 
 #include "register.h"
@@ -88,372 +87,109 @@ done:
 	/* (void) */ dpm->finish(dpm);
 }
 
-static int armv7a_read_ttbcr(struct target *target)
-{
-	struct armv7a_common *armv7a = target_to_armv7a(target);
-	struct arm_dpm *dpm = armv7a->arm.dpm;
-	uint32_t ttbcr;
-	int retval = dpm->prepare(dpm);
-	if (retval != ERROR_OK)
-		goto done;
-	/*  MRC p15,0,<Rt>,c2,c0,2 ; Read CP15 Translation Table Base Control Register*/
-	retval = dpm->instr_read_data_r0(dpm,
-			ARMV4_5_MRC(15, 0, 0, 2, 0, 2),
-			&ttbcr);
-	if (retval != ERROR_OK)
-		goto done;
-	armv7a->armv7a_mmu.ttbr1_used = ((ttbcr & 0x7) != 0) ? 1 : 0;
-	armv7a->armv7a_mmu.ttbr0_mask  = 7 << (32 - ((ttbcr & 0x7)));
-#if 0
-	LOG_INFO("ttb1 %s ,ttb0_mask %x",
-		armv7a->armv7a_mmu.ttbr1_used ? "used" : "not used",
-		armv7a->armv7a_mmu.ttbr0_mask);
-#endif
-	if (armv7a->armv7a_mmu.ttbr1_used == 1) {
-		LOG_INFO("SVC access above %" PRIx32,
-			 (uint32_t)(0xffffffff & armv7a->armv7a_mmu.ttbr0_mask));
-		armv7a->armv7a_mmu.os_border = 0xffffffff & armv7a->armv7a_mmu.ttbr0_mask;
-	} else {
-		/*  fix me , default is hard coded LINUX border  */
-		armv7a->armv7a_mmu.os_border = 0xc0000000;
-	}
-done:
-	dpm->finish(dpm);
-	return retval;
-}
 
-
-/*  method adapted to cortex A : reused arm v4 v5 method*/
-int armv7a_mmu_translate_va(struct target *target,  uint32_t va, uint32_t *val)
+/*  retrieve main id register  */
+static int armv7a_read_midr(struct target *target)
 {
-	uint32_t first_lvl_descriptor = 0x0;
-	uint32_t second_lvl_descriptor = 0x0;
-	int retval;
+	int retval = ERROR_FAIL;
 	struct armv7a_common *armv7a = target_to_armv7a(target);
 	struct arm_dpm *dpm = armv7a->arm.dpm;
-	uint32_t ttb = 0;	/*  default ttb0 */
-	if (armv7a->armv7a_mmu.ttbr1_used == -1)
-		armv7a_read_ttbcr(target);
-	if ((armv7a->armv7a_mmu.ttbr1_used) &&
-		(va > (0xffffffff & armv7a->armv7a_mmu.ttbr0_mask))) {
-		/*  select ttb 1 */
-		ttb = 1;
-	}
+	uint32_t midr;
 	retval = dpm->prepare(dpm);
 	if (retval != ERROR_OK)
 		goto done;
+	/* MRC p15,0,<Rd>,c0,c0,0; read main id register*/
 
-	/*  MRC p15,0,<Rt>,c2,c0,ttb */
 	retval = dpm->instr_read_data_r0(dpm,
-			ARMV4_5_MRC(15, 0, 0, 2, 0, ttb),
-			&ttb);
-	if (retval != ERROR_OK)
-		return retval;
-	retval = armv7a->armv7a_mmu.read_physical_memory(target,
-			(ttb & 0xffffc000) | ((va & 0xfff00000) >> 18),
-			4, 1, (uint8_t *)&first_lvl_descriptor);
+			ARMV4_5_MRC(15, 0, 0, 0, 0, 0),
+			&midr);
 	if (retval != ERROR_OK)
-		return retval;
-	first_lvl_descriptor = target_buffer_get_u32(target, (uint8_t *)
-			&first_lvl_descriptor);
-	/*  reuse armv4_5 piece of code, specific armv7a changes may come later */
-	LOG_DEBUG("1st lvl desc: %8.8" PRIx32 "", first_lvl_descriptor);
-
-	if ((first_lvl_descriptor & 0x3) == 0) {
-		LOG_ERROR("Address translation failure");
-		return ERROR_TARGET_TRANSLATION_FAULT;
-	}
-
-
-	if ((first_lvl_descriptor & 0x3) == 2) {
-		/* section descriptor */
-		*val = (first_lvl_descriptor & 0xfff00000) | (va & 0x000fffff);
-		return ERROR_OK;
-	}
-
-	if ((first_lvl_descriptor & 0x3) == 1) {
-		/* coarse page table */
-		retval = armv7a->armv7a_mmu.read_physical_memory(target,
-				(first_lvl_descriptor & 0xfffffc00) | ((va & 0x000ff000) >> 10),
-				4, 1, (uint8_t *)&second_lvl_descriptor);
-		if (retval != ERROR_OK)
-			return retval;
-	} else if ((first_lvl_descriptor & 0x3) == 3)   {
-		/* fine page table */
-		retval = armv7a->armv7a_mmu.read_physical_memory(target,
-				(first_lvl_descriptor & 0xfffff000) | ((va & 0x000ffc00) >> 8),
-				4, 1, (uint8_t *)&second_lvl_descriptor);
-		if (retval != ERROR_OK)
-			return retval;
-	}
-
-	second_lvl_descriptor = target_buffer_get_u32(target, (uint8_t *)
-			&second_lvl_descriptor);
-
-	LOG_DEBUG("2nd lvl desc: %8.8" PRIx32 "", second_lvl_descriptor);
-
-	if ((second_lvl_descriptor & 0x3) == 0) {
-		LOG_ERROR("Address translation failure");
-		return ERROR_TARGET_TRANSLATION_FAULT;
-	}
-
-	if ((second_lvl_descriptor & 0x3) == 1) {
-		/* large page descriptor */
-		*val = (second_lvl_descriptor & 0xffff0000) | (va & 0x0000ffff);
-		return ERROR_OK;
-	}
-
-	if ((second_lvl_descriptor & 0x3) == 2) {
-		/* small page descriptor */
-		*val = (second_lvl_descriptor & 0xfffff000) | (va & 0x00000fff);
-		return ERROR_OK;
-	}
-
-	if ((second_lvl_descriptor & 0x3) == 3) {
-		*val = (second_lvl_descriptor & 0xfffffc00) | (va & 0x000003ff);
-		return ERROR_OK;
-	}
+		goto done;
 
-	/* should not happen */
-	LOG_ERROR("Address translation failure");
-	return ERROR_TARGET_TRANSLATION_FAULT;
+	armv7a->rev = (midr & 0xf);
+	armv7a->partnum = (midr >> 4) & 0xfff;
+	armv7a->arch = (midr >> 16) & 0xf;
+	armv7a->variant = (midr >> 20) & 0xf;
+	armv7a->implementor = (midr >> 24) & 0xff;
+	LOG_INFO("%s rev %" PRIx32 ", partnum %" PRIx32 ", arch %" PRIx32
+			 ", variant %" PRIx32 ", implementor %" PRIx32,
+		 target->cmd_name,
+		 armv7a->rev,
+		 armv7a->partnum,
+		 armv7a->arch,
+		 armv7a->variant,
+		 armv7a->implementor);
 
 done:
+	dpm->finish(dpm);
 	return retval;
 }
 
-/*  V7 method VA TO PA  */
-int armv7a_mmu_translate_va_pa(struct target *target, uint32_t va,
-	uint32_t *val, int meminfo)
+int armv7a_read_ttbcr(struct target *target)
 {
-	int retval = ERROR_FAIL;
 	struct armv7a_common *armv7a = target_to_armv7a(target);
 	struct arm_dpm *dpm = armv7a->arm.dpm;
-	uint32_t virt = va & ~0xfff;
-	uint32_t NOS, NS, INNER, OUTER;
-	*val = 0xdeadbeef;
+	uint32_t ttbcr, ttbcr_n;
+	int ttbidx;
+	int retval;
+
 	retval = dpm->prepare(dpm);
 	if (retval != ERROR_OK)
 		goto done;
-	/*  mmu must be enable in order to get a correct translation
-	 *  use VA to PA CP15 register for conversion */
-	retval = dpm->instr_write_data_r0(dpm,
-			ARMV4_5_MCR(15, 0, 0, 7, 8, 0),
-			virt);
-	if (retval != ERROR_OK)
-		goto done;
-	retval = dpm->instr_read_data_r0(dpm,
-			ARMV4_5_MRC(15, 0, 0, 7, 4, 0),
-			val);
-	/* decode memory attribute */
-	NOS = (*val >> 10) & 1;	/*  Not Outer shareable */
-	NS = (*val >> 9) & 1;	/* Non secure */
-	INNER = (*val >> 4) &  0x7;
-	OUTER = (*val >> 2) & 0x3;
 
+	/*  MRC p15,0,<Rt>,c2,c0,2 ; Read CP15 Translation Table Base Control Register*/
+	retval = dpm->instr_read_data_r0(dpm,
+			ARMV4_5_MRC(15, 0, 0, 2, 0, 2),
+			&ttbcr);
 	if (retval != ERROR_OK)
 		goto done;
-	*val = (*val & ~0xfff)  +  (va & 0xfff);
-	if (*val == va)
-		LOG_WARNING("virt = phys  : MMU disable !!");
-	if (meminfo) {
-		LOG_INFO("%" PRIx32 " : %" PRIx32 " %s outer shareable %s secured",
-			va, *val,
-			NOS == 1 ? "not" : " ",
-			NS == 1 ? "not" : "");
-		switch (OUTER) {
-			case 0:
-				LOG_INFO("outer: Non-Cacheable");
-				break;
-			case 1:
-				LOG_INFO("outer: Write-Back, Write-Allocate");
-				break;
-			case 2:
-				LOG_INFO("outer: Write-Through, No Write-Allocate");
-				break;
-			case 3:
-				LOG_INFO("outer: Write-Back, no Write-Allocate");
-				break;
-		}
-		switch (INNER) {
-			case 0:
-				LOG_INFO("inner: Non-Cacheable");
-				break;
-			case 1:
-				LOG_INFO("inner: Strongly-ordered");
-				break;
-			case 3:
-				LOG_INFO("inner: Device");
-				break;
-			case 5:
-				LOG_INFO("inner: Write-Back, Write-Allocate");
-				break;
-			case 6:
-				LOG_INFO("inner:  Write-Through");
-				break;
-			case 7:
-				LOG_INFO("inner: Write-Back, no Write-Allocate");
-
-			default:
-				LOG_INFO("inner: %" PRIx32 " ???", INNER);
-		}
-	}
 
-done:
-	dpm->finish(dpm);
+	LOG_DEBUG("ttbcr %" PRIx32, ttbcr);
 
-	return retval;
-}
+	ttbcr_n = ttbcr & 0x7;
+	armv7a->armv7a_mmu.ttbcr = ttbcr;
+	armv7a->armv7a_mmu.cached = 1;
 
-static int armv7a_handle_inner_cache_info_command(struct command_context *cmd_ctx,
-	struct armv7a_cache_common *armv7a_cache)
-{
-	if (armv7a_cache->ctype == -1) {
-		command_print(cmd_ctx, "cache not yet identified");
-		return ERROR_OK;
+	for (ttbidx = 0; ttbidx < 2; ttbidx++) {
+		/*  MRC p15,0,<Rt>,c2,c0,ttbidx */
+		retval = dpm->instr_read_data_r0(dpm,
+				ARMV4_5_MRC(15, 0, 0, 2, 0, ttbidx),
+				&armv7a->armv7a_mmu.ttbr[ttbidx]);
+		if (retval != ERROR_OK)
+			goto done;
 	}
 
-	command_print(cmd_ctx,
-		"D-Cache: linelen %" PRIi32 ", associativity %" PRIi32 ", nsets %" PRIi32 ", cachesize %" PRId32 " KBytes",
-		armv7a_cache->d_u_size.linelen,
-		armv7a_cache->d_u_size.associativity,
-		armv7a_cache->d_u_size.nsets,
-		armv7a_cache->d_u_size.cachesize);
-
-	command_print(cmd_ctx,
-		"I-Cache: linelen %" PRIi32 ", associativity %" PRIi32 ", nsets %" PRIi32 ", cachesize %" PRId32 " KBytes",
-		armv7a_cache->i_size.linelen,
-		armv7a_cache->i_size.associativity,
-		armv7a_cache->i_size.nsets,
-		armv7a_cache->i_size.cachesize);
-
-	return ERROR_OK;
-}
-
-static int _armv7a_flush_all_data(struct target *target)
-{
-	struct armv7a_common *armv7a = target_to_armv7a(target);
-	struct arm_dpm *dpm = armv7a->arm.dpm;
-	struct armv7a_cachesize *d_u_size =
-		&(armv7a->armv7a_mmu.armv7a_cache.d_u_size);
-	int32_t c_way, c_index = d_u_size->index;
-	int retval;
-	/*  check that cache data is on at target halt */
-	if (!armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled) {
-		LOG_INFO("flushed not performed :cache not on at target halt");
-		return ERROR_OK;
-	}
-	retval = dpm->prepare(dpm);
+	/*
+	 * ARM Architecture Reference Manual (ARMv7-A and ARMv7-Redition),
+	 * document # ARM DDI 0406C
+	 */
+	armv7a->armv7a_mmu.ttbr_range[0]  = 0xffffffff >> ttbcr_n;
+	armv7a->armv7a_mmu.ttbr_range[1] = 0xffffffff;
+	armv7a->armv7a_mmu.ttbr_mask[0] = 0xffffffff << (14 - ttbcr_n);
+	armv7a->armv7a_mmu.ttbr_mask[1] = 0xffffffff << 14;
+	armv7a->armv7a_mmu.cached = 1;
+
+	retval = armv7a_read_midr(target);
 	if (retval != ERROR_OK)
 		goto done;
-	do {
-		c_way = d_u_size->way;
-		do {
-			uint32_t value = (c_index << d_u_size->index_shift)
-				| (c_way << d_u_size->way_shift);
-			/*  DCCISW */
-			/* LOG_INFO ("%d %d %x",c_way,c_index,value); */
-			retval = dpm->instr_write_data_r0(dpm,
-					ARMV4_5_MCR(15, 0, 0, 7, 14, 2),
-					value);
-			if (retval != ERROR_OK)
-				goto done;
-			c_way -= 1;
-		} while (c_way >= 0);
-		c_index -= 1;
-	} while (c_index >= 0);
-	return retval;
-done:
-	LOG_ERROR("flushed failed");
-	dpm->finish(dpm);
-	return retval;
-}
 
-static int  armv7a_flush_all_data(struct target *target)
-{
-	int retval = ERROR_FAIL;
-	/*  check that armv7a_cache is correctly identify */
-	struct armv7a_common *armv7a = target_to_armv7a(target);
-	if (armv7a->armv7a_mmu.armv7a_cache.ctype == -1) {
-		LOG_ERROR("trying to flush un-identified cache");
-		return retval;
+	/* FIXME: why this special case based on part number? */
+	if ((armv7a->partnum & 0xf) == 0) {
+		/*  ARM DDI 0344H , ARM DDI 0407F */
+		armv7a->armv7a_mmu.ttbr_mask[0]  = 7 << (32 - ttbcr_n);
 	}
 
-	if (target->smp) {
-		/*  look if all the other target have been flushed in order to flush level
-		 *  2 */
-		struct target_list *head;
-		struct target *curr;
-		head = target->head;
-		while (head != (struct target_list *)NULL) {
-			curr = head->target;
-			if (curr->state == TARGET_HALTED) {
-				LOG_INFO("Wait flushing data l1 on core %" PRId32, curr->coreid);
-				retval = _armv7a_flush_all_data(curr);
-			}
-			head = head->next;
-		}
-	} else
-		retval = _armv7a_flush_all_data(target);
-	return retval;
-}
-
-/* L2 is not specific to armv7a  a specific file is needed */
-static int armv7a_l2x_flush_all_data(struct target *target)
-{
+	LOG_DEBUG("ttbr1 %s, ttbr0_mask %" PRIx32 " ttbr1_mask %" PRIx32,
+		  (ttbcr_n != 0) ? "used" : "not used",
+		  armv7a->armv7a_mmu.ttbr_mask[0],
+		  armv7a->armv7a_mmu.ttbr_mask[1]);
 
-#define L2X0_CLEAN_INV_WAY              0x7FC
-	int retval = ERROR_FAIL;
-	struct armv7a_common *armv7a = target_to_armv7a(target);
-	struct armv7a_l2x_cache *l2x_cache = (struct armv7a_l2x_cache *)
-		(armv7a->armv7a_mmu.armv7a_cache.l2_cache);
-	uint32_t base = l2x_cache->base;
-	uint32_t l2_way = l2x_cache->way;
-	uint32_t l2_way_val = (1 << l2_way) - 1;
-	retval = armv7a_flush_all_data(target);
-	if (retval != ERROR_OK)
-		return retval;
-	retval = target->type->write_phys_memory(target,
-			(uint32_t)(base+(uint32_t)L2X0_CLEAN_INV_WAY),
-			(uint32_t)4,
-			(uint32_t)1,
-			(uint8_t *)&l2_way_val);
+done:
+	dpm->finish(dpm);
 	return retval;
 }
 
-static int armv7a_handle_l2x_cache_info_command(struct command_context *cmd_ctx,
-	struct armv7a_cache_common *armv7a_cache)
-{
-
-	struct armv7a_l2x_cache *l2x_cache = (struct armv7a_l2x_cache *)
-		(armv7a_cache->l2_cache);
-
-	if (armv7a_cache->ctype == -1) {
-		command_print(cmd_ctx, "cache not yet identified");
-		return ERROR_OK;
-	}
-
-	command_print(cmd_ctx,
-		"L1 D-Cache: linelen %" PRIi32 ", associativity %" PRIi32 ", nsets %" PRIi32 ", cachesize %" PRId32 " KBytes",
-		armv7a_cache->d_u_size.linelen,
-		armv7a_cache->d_u_size.associativity,
-		armv7a_cache->d_u_size.nsets,
-		armv7a_cache->d_u_size.cachesize);
-
-	command_print(cmd_ctx,
-		"L1 I-Cache: linelen %" PRIi32 ", associativity %" PRIi32 ", nsets %" PRIi32 ", cachesize %" PRId32 " KBytes",
-		armv7a_cache->i_size.linelen,
-		armv7a_cache->i_size.associativity,
-		armv7a_cache->i_size.nsets,
-		armv7a_cache->i_size.cachesize);
-	command_print(cmd_ctx, "L2 unified cache Base Address 0x%" PRIx32 ", %" PRId32 " ways",
-		l2x_cache->base, l2x_cache->way);
-
-
-	return ERROR_OK;
-}
-
-
+/* FIXME: remove it */
 static int armv7a_l2x_cache_init(struct target *target, uint32_t base, uint32_t way)
 {
 	struct armv7a_l2x_cache *l2x_cache;
@@ -466,65 +202,90 @@ static int armv7a_l2x_cache_init(struct target *target, uint32_t base, uint32_t
 	l2x_cache->way = way;
 	/*LOG_INFO("cache l2 initialized base %x  way %d",
 	l2x_cache->base,l2x_cache->way);*/
-	if (armv7a->armv7a_mmu.armv7a_cache.l2_cache)
-		LOG_INFO("cache l2 already initialized\n");
-	armv7a->armv7a_mmu.armv7a_cache.l2_cache = l2x_cache;
-	/*  initialize l1 / l2x cache function  */
-	armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache
-		= armv7a_l2x_flush_all_data;
-	armv7a->armv7a_mmu.armv7a_cache.display_cache_info =
-		armv7a_handle_l2x_cache_info_command;
+	if (armv7a->armv7a_mmu.armv7a_cache.outer_cache)
+		LOG_INFO("outer cache already initialized\n");
+	armv7a->armv7a_mmu.armv7a_cache.outer_cache = l2x_cache;
 	/*  initialize all target in this cluster (smp target)
 	 *  l2 cache must be configured after smp declaration */
 	while (head != (struct target_list *)NULL) {
 		curr = head->target;
 		if (curr != target) {
 			armv7a = target_to_armv7a(curr);
-			if (armv7a->armv7a_mmu.armv7a_cache.l2_cache)
-				LOG_ERROR("smp target : cache l2 already initialized\n");
-			armv7a->armv7a_mmu.armv7a_cache.l2_cache = l2x_cache;
-			armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache =
-				armv7a_l2x_flush_all_data;
-			armv7a->armv7a_mmu.armv7a_cache.display_cache_info =
-				armv7a_handle_l2x_cache_info_command;
+			if (armv7a->armv7a_mmu.armv7a_cache.outer_cache)
+				LOG_ERROR("smp target : outer cache already initialized\n");
+			armv7a->armv7a_mmu.armv7a_cache.outer_cache = l2x_cache;
 		}
 		head = head->next;
 	}
 	return JIM_OK;
 }
 
+/* FIXME: remove it */
 COMMAND_HANDLER(handle_cache_l2x)
 {
 	struct target *target = get_current_target(CMD_CTX);
 	uint32_t base, way;
-	switch (CMD_ARGC) {
-		case 0:
-			return ERROR_COMMAND_SYNTAX_ERROR;
-			break;
-		case 2:
-			/* command_print(CMD_CTX, "%s %s", CMD_ARGV[0], CMD_ARGV[1]); */
-			COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], base);
-			COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], way);
-
-			/* AP address is in bits 31:24 of DP_SELECT */
-			armv7a_l2x_cache_init(target, base, way);
-			break;
-		default:
-			return ERROR_COMMAND_SYNTAX_ERROR;
-	}
+
+	if (CMD_ARGC != 2)
+		return ERROR_COMMAND_SYNTAX_ERROR;
+
+	/* command_print(CMD_CTX, "%s %s", CMD_ARGV[0], CMD_ARGV[1]); */
+	COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], base);
+	COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], way);
+
+	/* AP address is in bits 31:24 of DP_SELECT */
+	armv7a_l2x_cache_init(target, base, way);
+
 	return ERROR_OK;
 }
 
 int armv7a_handle_cache_info_command(struct command_context *cmd_ctx,
 	struct armv7a_cache_common *armv7a_cache)
 {
-	if (armv7a_cache->ctype == -1) {
+	struct armv7a_l2x_cache *l2x_cache = (struct armv7a_l2x_cache *)
+		(armv7a_cache->outer_cache);
+
+	int cl;
+
+	if (armv7a_cache->info == -1) {
 		command_print(cmd_ctx, "cache not yet identified");
 		return ERROR_OK;
 	}
 
-	if (armv7a_cache->display_cache_info)
-		armv7a_cache->display_cache_info(cmd_ctx, armv7a_cache);
+	for (cl = 0; cl < armv7a_cache->loc; cl++) {
+		struct armv7a_arch_cache *arch = &(armv7a_cache->arch[cl]);
+
+		if (arch->ctype & 1) {
+			command_print(cmd_ctx,
+				"L%d I-Cache: linelen %" PRIi32
+				", associativity %" PRIi32
+				", nsets %" PRIi32
+				", cachesize %" PRId32 " KBytes",
+				cl+1,
+				arch->i_size.linelen,
+				arch->i_size.associativity,
+				arch->i_size.nsets,
+				arch->i_size.cachesize);
+		}
+
+		if (arch->ctype >= 2) {
+			command_print(cmd_ctx,
+				"L%d D-Cache: linelen %" PRIi32
+				", associativity %" PRIi32
+				", nsets %" PRIi32
+				", cachesize %" PRId32 " KBytes",
+				cl+1,
+				arch->d_u_size.linelen,
+				arch->d_u_size.associativity,
+				arch->d_u_size.nsets,
+				arch->d_u_size.cachesize);
+		}
+	}
+
+	if (l2x_cache != NULL)
+		command_print(cmd_ctx, "Outer unified cache Base Address 0x%" PRIx32 ", %" PRId32 " ways",
+			l2x_cache->base, l2x_cache->way);
+
 	return ERROR_OK;
 }
 
@@ -546,23 +307,21 @@ static int armv7a_read_mpidr(struct target *target)
 	if (retval != ERROR_OK)
 		goto done;
 
-	/* ARMv7R uses a different format for MPIDR.
-	 * When configured uniprocessor (most R cores) it reads as 0.
-	 * This will need to be implemented for multiprocessor ARMv7R cores. */
-	if (armv7a->is_armv7r) {
-		if (mpidr)
-			LOG_ERROR("MPIDR nonzero in ARMv7-R target");
-		goto done;
-	}
-
-	if (mpidr & 1<<31) {
+	/* Is register in Multiprocessing Extensions register format? */
+	if (mpidr & MPIDR_MP_EXT) {
+		LOG_DEBUG("%s: MPIDR 0x%" PRIx32, target_name(target), mpidr);
 		armv7a->multi_processor_system = (mpidr >> 30) & 1;
+		armv7a->multi_threading_processor = (mpidr >> 24) & 1;
+		armv7a->level2_id = (mpidr >> 16) & 0xf;
 		armv7a->cluster_id = (mpidr >> 8) & 0xf;
-		armv7a->cpu_id = mpidr & 0x3;
-		LOG_INFO("%s cluster %x core %x %s", target_name(target),
+		armv7a->cpu_id = mpidr & 0xf;
+		LOG_INFO("%s: MPIDR level2 %x, cluster %x, core %x, %s, %s",
+			target_name(target),
+			armv7a->level2_id,
 			armv7a->cluster_id,
 			armv7a->cpu_id,
-			armv7a->multi_processor_system == 0 ? "multi core" : "mono core");
+			armv7a->multi_processor_system == 0 ? "multi core" : "mono core",
+			armv7a->multi_threading_processor == 1 ? "SMT" : "no SMT");
 
 	} else
 		LOG_ERROR("MPIDR not in multiprocessor format");
@@ -574,21 +333,75 @@ done:
 
 }
 
+static int get_cache_info(struct arm_dpm *dpm, int cl, int ct, uint32_t *cache_reg)
+{
+	int retval = ERROR_OK;
+
+	/*  select cache level */
+	retval = dpm->instr_write_data_r0(dpm,
+			ARMV4_5_MCR(15, 2, 0, 0, 0, 0),
+			(cl << 1) | (ct == 1 ? 1 : 0));
+	if (retval != ERROR_OK)
+		goto done;
+
+	retval = dpm->instr_read_data_r0(dpm,
+			ARMV4_5_MRC(15, 1, 0, 0, 0, 0),
+			cache_reg);
+ done:
+	return retval;
+}
+
+static struct armv7a_cachesize decode_cache_reg(uint32_t cache_reg)
+{
+	struct armv7a_cachesize size;
+	int i = 0;
+
+	size.linelen = 16 << (cache_reg & 0x7);
+	size.associativity = ((cache_reg >> 3) & 0x3ff) + 1;
+	size.nsets = ((cache_reg >> 13) & 0x7fff) + 1;
+	size.cachesize = size.linelen * size.associativity * size.nsets / 1024;
+
+	/*  compute info for set way operation on cache */
+	size.index_shift = (cache_reg & 0x7) + 4;
+	size.index = (cache_reg >> 13) & 0x7fff;
+	size.way = ((cache_reg >> 3) & 0x3ff);
+
+	while (((size.way << i) & 0x80000000) == 0)
+		i++;
+	size.way_shift = i;
+
+	return size;
+}
+
 int armv7a_identify_cache(struct target *target)
 {
 	/*  read cache descriptor */
 	int retval = ERROR_FAIL;
 	struct armv7a_common *armv7a = target_to_armv7a(target);
 	struct arm_dpm *dpm = armv7a->arm.dpm;
-	uint32_t cache_selected, clidr;
-	uint32_t cache_i_reg, cache_d_reg;
-	struct armv7a_cache_common *cache = &(armv7a->armv7a_mmu.armv7a_cache);
-	if (!armv7a->is_armv7r)
-		armv7a_read_ttbcr(target);
+	uint32_t csselr, clidr, ctr;
+	uint32_t cache_reg;
+	int cl, ctype;
+	struct armv7a_cache_common *cache =
+		&(armv7a->armv7a_mmu.armv7a_cache);
+
 	retval = dpm->prepare(dpm);
+	if (retval != ERROR_OK)
+		goto done;
 
+	/* retrieve CTR
+	 * mrc p15, 0, r0, c0, c0, 1		@ read ctr */
+	retval = dpm->instr_read_data_r0(dpm,
+			ARMV4_5_MRC(15, 0, 0, 0, 0, 1),
+			&ctr);
 	if (retval != ERROR_OK)
 		goto done;
+
+	cache->iminline = 4UL << (ctr & 0xf);
+	cache->dminline = 4UL << ((ctr & 0xf0000) >> 16);
+	LOG_DEBUG("ctr %" PRIx32 " ctr.iminline %" PRId32 " ctr.dminline %" PRId32,
+		 ctr, cache->iminline, cache->dminline);
+
 	/*  retrieve CLIDR
 	 *  mrc	p15, 1, r0, c0, c0, 1		@ read clidr */
 	retval = dpm->instr_read_data_r0(dpm,
@@ -596,129 +409,86 @@ int armv7a_identify_cache(struct target *target)
 			&clidr);
 	if (retval != ERROR_OK)
 		goto done;
-	clidr = (clidr & 0x7000000) >> 23;
-	LOG_INFO("number of cache level %" PRIx32, (uint32_t)(clidr / 2));
-	if ((clidr / 2) > 1) {
-		/* FIXME not supported present in cortex A8 and later */
-		/*  in cortex A7, A15 */
-		LOG_ERROR("cache l2 present :not supported");
-	}
-	/*  retrieve selected cache
+
+	cache->loc = (clidr & 0x7000000) >> 24;
+	LOG_DEBUG("Number of cache levels to PoC %" PRId32, cache->loc);
+
+	/*  retrieve selected cache for later restore
 	 *  MRC p15, 2,<Rd>, c0, c0, 0; Read CSSELR */
 	retval = dpm->instr_read_data_r0(dpm,
 			ARMV4_5_MRC(15, 2, 0, 0, 0, 0),
-			&cache_selected);
+			&csselr);
 	if (retval != ERROR_OK)
 		goto done;
 
-	retval = armv7a->arm.mrc(target, 15,
-			2, 0,	/* op1, op2 */
-			0, 0,	/* CRn, CRm */
-			&cache_selected);
-	if (retval != ERROR_OK)
-		goto done;
-	/* select instruction cache
-	 *  MCR p15, 2,<Rd>, c0, c0, 0; Write CSSELR
-	 *  [0]  : 1 instruction cache selection , 0 data cache selection */
-	retval = dpm->instr_write_data_r0(dpm,
-			ARMV4_5_MRC(15, 2, 0, 0, 0, 0),
-			1);
-	if (retval != ERROR_OK)
-		goto done;
+	/* retrieve all available inner caches */
+	for (cl = 0; cl < cache->loc; clidr >>= 3, cl++) {
 
-	/* read CCSIDR
-	 * MRC P15,1,<RT>,C0, C0,0 ;on cortex A9 read CCSIDR
-	 * [2:0] line size  001 eight word per line
-	 * [27:13] NumSet 0x7f 16KB, 0xff 32Kbytes, 0x1ff 64Kbytes */
-	retval = dpm->instr_read_data_r0(dpm,
-			ARMV4_5_MRC(15, 1, 0, 0, 0, 0),
-			&cache_i_reg);
-	if (retval != ERROR_OK)
-		goto done;
+		/* isolate cache type at current level */
+		ctype = clidr & 7;
 
-	/*  select data cache*/
-	retval = dpm->instr_write_data_r0(dpm,
-			ARMV4_5_MRC(15, 2, 0, 0, 0, 0),
-			0);
-	if (retval != ERROR_OK)
-		goto done;
+		/* skip reserved values */
+		if (ctype > CACHE_LEVEL_HAS_UNIFIED_CACHE)
+			continue;
 
-	retval = dpm->instr_read_data_r0(dpm,
-			ARMV4_5_MRC(15, 1, 0, 0, 0, 0),
-			&cache_d_reg);
-	if (retval != ERROR_OK)
-		goto done;
+		/* separate d or unified d/i cache at this level ? */
+		if (ctype & (CACHE_LEVEL_HAS_UNIFIED_CACHE | CACHE_LEVEL_HAS_D_CACHE)) {
+			/* retrieve d-cache info */
+			retval = get_cache_info(dpm, cl, 0, &cache_reg);
+			if (retval != ERROR_OK)
+				goto done;
+			cache->arch[cl].d_u_size = decode_cache_reg(cache_reg);
+
+			LOG_DEBUG("data/unified cache index %d << %d, way %d << %d",
+					cache->arch[cl].d_u_size.index,
+					cache->arch[cl].d_u_size.index_shift,
+					cache->arch[cl].d_u_size.way,
+					cache->arch[cl].d_u_size.way_shift);
+
+			LOG_DEBUG("cacheline %d bytes %d KBytes asso %d ways",
+					cache->arch[cl].d_u_size.linelen,
+					cache->arch[cl].d_u_size.cachesize,
+					cache->arch[cl].d_u_size.associativity);
+		}
+
+		/* separate i-cache at this level ? */
+		if (ctype & CACHE_LEVEL_HAS_I_CACHE) {
+			/* retrieve i-cache info */
+			retval = get_cache_info(dpm, cl, 1, &cache_reg);
+			if (retval != ERROR_OK)
+				goto done;
+			cache->arch[cl].i_size = decode_cache_reg(cache_reg);
+
+			LOG_DEBUG("instruction cache index %d << %d, way %d << %d",
+					cache->arch[cl].i_size.index,
+					cache->arch[cl].i_size.index_shift,
+					cache->arch[cl].i_size.way,
+					cache->arch[cl].i_size.way_shift);
+
+			LOG_DEBUG("cacheline %d bytes %d KBytes asso %d ways",
+					cache->arch[cl].i_size.linelen,
+					cache->arch[cl].i_size.cachesize,
+					cache->arch[cl].i_size.associativity);
+		}
+
+		cache->arch[cl].ctype = ctype;
+	}
 
 	/*  restore selected cache  */
 	dpm->instr_write_data_r0(dpm,
 		ARMV4_5_MRC(15, 2, 0, 0, 0, 0),
-		cache_selected);
+		csselr);
 
 	if (retval != ERROR_OK)
 		goto done;
-	dpm->finish(dpm);
 
-	/* put fake type */
-	cache->d_u_size.linelen = 16 << (cache_d_reg & 0x7);
-	cache->d_u_size.cachesize = (((cache_d_reg >> 13) & 0x7fff)+1)/8;
-	cache->d_u_size.nsets = (cache_d_reg >> 13) & 0x7fff;
-	cache->d_u_size.associativity = ((cache_d_reg >> 3) & 0x3ff) + 1;
-	/*  compute info for set way operation on cache */
-	cache->d_u_size.index_shift = (cache_d_reg & 0x7) + 4;
-	cache->d_u_size.index = (cache_d_reg >> 13) & 0x7fff;
-	cache->d_u_size.way = ((cache_d_reg >> 3) & 0x3ff);
-	cache->d_u_size.way_shift = cache->d_u_size.way + 1;
-	{
-		int i = 0;
-		while (((cache->d_u_size.way_shift >> i) & 1) != 1)
-			i++;
-		cache->d_u_size.way_shift = 32-i;
-	}
-#if 0
-	LOG_INFO("data cache index %d << %d, way %d << %d",
-			cache->d_u_size.index, cache->d_u_size.index_shift,
-			cache->d_u_size.way,
-			cache->d_u_size.way_shift);
-
-	LOG_INFO("data cache %d bytes %d KBytes asso %d ways",
-			cache->d_u_size.linelen,
-			cache->d_u_size.cachesize,
-			cache->d_u_size.associativity);
-#endif
-	cache->i_size.linelen = 16 << (cache_i_reg & 0x7);
-	cache->i_size.associativity = ((cache_i_reg >> 3) & 0x3ff) + 1;
-	cache->i_size.nsets = (cache_i_reg >> 13) & 0x7fff;
-	cache->i_size.cachesize = (((cache_i_reg >> 13) & 0x7fff)+1)/8;
-	/*  compute info for set way operation on cache */
-	cache->i_size.index_shift = (cache_i_reg & 0x7) + 4;
-	cache->i_size.index = (cache_i_reg >> 13) & 0x7fff;
-	cache->i_size.way = ((cache_i_reg >> 3) & 0x3ff);
-	cache->i_size.way_shift = cache->i_size.way + 1;
-	{
-		int i = 0;
-		while (((cache->i_size.way_shift >> i) & 1) != 1)
-			i++;
-		cache->i_size.way_shift = 32-i;
-	}
-#if 0
-	LOG_INFO("instruction cache index %d << %d, way %d << %d",
-			cache->i_size.index, cache->i_size.index_shift,
-			cache->i_size.way, cache->i_size.way_shift);
-
-	LOG_INFO("instruction cache %d bytes %d KBytes asso %d ways",
-			cache->i_size.linelen,
-			cache->i_size.cachesize,
-			cache->i_size.associativity);
-#endif
 	/*  if no l2 cache initialize l1 data cache flush function function */
 	if (armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache == NULL) {
-		armv7a->armv7a_mmu.armv7a_cache.display_cache_info =
-			armv7a_handle_inner_cache_info_command;
 		armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache =
-			armv7a_flush_all_data;
+			armv7a_cache_auto_flush_all_data;
 	}
-	armv7a->armv7a_mmu.armv7a_cache.ctype = 0;
 
+	armv7a->armv7a_mmu.armv7a_cache.info = 1;
 done:
 	dpm->finish(dpm);
 	armv7a_read_mpidr(target);
@@ -726,19 +496,48 @@ done:
 
 }
 
+static int armv7a_setup_semihosting(struct target *target, int enable)
+{
+	struct armv7a_common *armv7a = target_to_armv7a(target);
+	uint32_t vcr;
+	int ret;
+
+	ret = mem_ap_read_atomic_u32(armv7a->debug_ap,
+					 armv7a->debug_base + CPUDBG_VCR,
+					 &vcr);
+	if (ret < 0) {
+		LOG_ERROR("Failed to read VCR register\n");
+		return ret;
+	}
+
+	if (enable)
+		vcr |= DBG_VCR_SVC_MASK;
+	else
+		vcr &= ~DBG_VCR_SVC_MASK;
+
+	ret = mem_ap_write_atomic_u32(armv7a->debug_ap,
+					  armv7a->debug_base + CPUDBG_VCR,
+					  vcr);
+	if (ret < 0)
+		LOG_ERROR("Failed to write VCR register\n");
+
+	return ret;
+}
+
 int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a)
 {
 	struct arm *arm = &armv7a->arm;
 	arm->arch_info = armv7a;
 	target->arch_info = &armv7a->arm;
+	arm->setup_semihosting = armv7a_setup_semihosting;
 	/*  target is useful in all function arm v4 5 compatible */
 	armv7a->arm.target = target;
 	armv7a->arm.common_magic = ARM_COMMON_MAGIC;
 	armv7a->common_magic = ARMV7_COMMON_MAGIC;
-	armv7a->armv7a_mmu.armv7a_cache.l2_cache = NULL;
-	armv7a->armv7a_mmu.armv7a_cache.ctype = -1;
+	armv7a->armv7a_mmu.armv7a_cache.info = -1;
+	armv7a->armv7a_mmu.armv7a_cache.outer_cache = NULL;
 	armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache = NULL;
-	armv7a->armv7a_mmu.armv7a_cache.display_cache_info = NULL;
+	armv7a->armv7a_mmu.armv7a_cache.auto_cache_enabled = 1;
 	return ERROR_OK;
 }
 
@@ -783,8 +582,7 @@ static const struct command_registration l2_cache_commands[] = {
 		.name = "l2x",
 		.handler = handle_cache_l2x,
 		.mode = COMMAND_EXEC,
-		.help = "configure l2x cache "
-			"",
+		.help = "configure l2x cache",
 		.usage = "[base_addr] [number_of_way]",
 	},
 	COMMAND_REGISTRATION_DONE
@@ -802,13 +600,12 @@ const struct command_registration l2x_cache_command_handlers[] = {
 	COMMAND_REGISTRATION_DONE
 };
 
-
 const struct command_registration armv7a_command_handlers[] = {
 	{
-		.chain = dap_command_handlers,
+		.chain = l2x_cache_command_handlers,
 	},
 	{
-		.chain = l2x_cache_command_handlers,
+		.chain = arm7a_cache_command_handlers,
 	},
 	COMMAND_REGISTRATION_DONE
 };