X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farmv4_5_mmu.h;h=7beaf4ee96323669e12abddaa53a7183d62d4af0;hp=0c9b550110796f1a7fce43b644f7e733940cd3ff;hb=HEAD;hpb=1e5daf5886999a8ff01a4957e17c1466d76e022d diff --git a/src/target/armv4_5_mmu.h b/src/target/armv4_5_mmu.h index 0c9b550110..774f1056eb 100644 --- a/src/target/armv4_5_mmu.h +++ b/src/target/armv4_5_mmu.h @@ -1,57 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /*************************************************************************** * Copyright (C) 2005 by Dominic Rath * * Dominic.Rath@gmx.de * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ -#ifndef ARMV4_5_MMU_H -#define ARMV4_5_MMU_H + +#ifndef OPENOCD_TARGET_ARMV4_5_MMU_H +#define OPENOCD_TARGET_ARMV4_5_MMU_H #include "armv4_5_cache.h" -#include "target.h" - -typedef struct armv4_5_mmu_common_s -{ - uint32_t (*get_ttb)(target_t *target); - int (*read_memory)(target_t *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer); - int (*write_memory)(target_t *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer); - void (*disable_mmu_caches)(target_t *target, int mmu, int d_u_cache, int i_cache); - void (*enable_mmu_caches)(target_t *target, int mmu, int d_u_cache, int i_cache); - armv4_5_cache_common_t armv4_5_cache; + +struct target; + +struct armv4_5_mmu_common { + int (*get_ttb)(struct target *target, uint32_t *result); + int (*read_memory)(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer); + int (*write_memory)(struct target *target, target_addr_t address, + uint32_t size, uint32_t count, const uint8_t *buffer); + int (*disable_mmu_caches)(struct target *target, int mmu, int d_u_cache, int i_cache); + int (*enable_mmu_caches)(struct target *target, int mmu, int d_u_cache, int i_cache); + struct armv4_5_cache_common armv4_5_cache; int has_tiny_pages; int mmu_enabled; -} armv4_5_mmu_common_t; - -enum -{ - ARMV4_5_SECTION, ARMV4_5_LARGE_PAGE, ARMV4_5_SMALL_PAGE, ARMV4_5_TINY_PAGE }; -extern char* armv4_5_page_type_names[]; +int armv4_5_mmu_translate_va(struct target *target, + struct armv4_5_mmu_common *armv4_5_mmu, uint32_t va, + uint32_t *cb, uint32_t *val); + +int armv4_5_mmu_read_physical(struct target *target, + struct armv4_5_mmu_common *armv4_5_mmu, + uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer); -extern uint32_t armv4_5_mmu_translate_va(target_t *target, armv4_5_mmu_common_t *armv4_5_mmu, uint32_t va, int *type, uint32_t *cb, int *domain, uint32_t *ap); -extern int armv4_5_mmu_read_physical(target_t *target, armv4_5_mmu_common_t *armv4_5_mmu, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer); -extern int armv4_5_mmu_write_physical(target_t *target, armv4_5_mmu_common_t *armv4_5_mmu, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer); +int armv4_5_mmu_write_physical(struct target *target, + struct armv4_5_mmu_common *armv4_5_mmu, + uint32_t address, uint32_t size, uint32_t count, const uint8_t *buffer); -enum -{ +enum { ARMV4_5_MMU_ENABLED = 0x1, ARMV4_5_ALIGNMENT_CHECK = 0x2, ARMV4_5_MMU_S_BIT = 0x100, ARMV4_5_MMU_R_BIT = 0x200 }; -#endif /* ARMV4_5_MMU_H */ +#endif /* OPENOCD_TARGET_ARMV4_5_MMU_H */