X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farmv4_5.h;h=c8fc558082fe502e7cdaefc7683786284d66878a;hp=d126f964efa4da96bfe35422c0150e86829064e5;hb=69c751956293e822faa6cf844f2864d81c36a578;hpb=d6c8945662e6027f6ba12d73bac2473088672db5

diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index d126f964ef..c8fc558082 100644
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -35,31 +35,32 @@ typedef enum armv4_5_mode
 	ARMV4_5_MODE_IRQ = 18,
 	ARMV4_5_MODE_SVC = 19,
 	ARMV4_5_MODE_ABT = 23,
+	ARM_MODE_MON = 26,
 	ARMV4_5_MODE_UND = 27,
 	ARMV4_5_MODE_SYS = 31,
 	ARMV4_5_MODE_ANY = -1
 } armv4_5_mode_t;
 
+const char *arm_mode_name(unsigned psr_mode);
+bool is_arm_mode(unsigned psr_mode);
+
 int armv4_5_mode_to_number(enum armv4_5_mode mode);
 enum armv4_5_mode armv4_5_number_to_mode(int number);
 
-extern const char **armv4_5_mode_strings;
-
 typedef enum armv4_5_state
 {
 	ARMV4_5_STATE_ARM,
 	ARMV4_5_STATE_THUMB,
 	ARMV4_5_STATE_JAZELLE,
+	ARM_STATE_THUMB_EE,
 } armv4_5_state_t;
 
 extern char* armv4_5_state_strings[];
 
-extern int armv4_5_core_reg_map[7][17];
+extern const int armv4_5_core_reg_map[8][17];
 
 #define ARMV4_5_CORE_REG_MODE(cache, mode, num) \
 		cache->reg_list[armv4_5_core_reg_map[armv4_5_mode_to_number(mode)][num]]
-#define ARMV4_5_CORE_REG_MODENUM(cache, mode, num) \
-		cache->reg_list[armv4_5_core_reg_map[mode][num]]
 
 /* offsets into armv4_5 core register cache */
 enum
@@ -69,7 +70,8 @@ enum
 	ARMV4_5_SPSR_IRQ = 33,
 	ARMV4_5_SPSR_SVC = 34,
 	ARMV4_5_SPSR_ABT = 35,
-	ARMV4_5_SPSR_UND = 36
+	ARMV4_5_SPSR_UND = 36,
+	ARM_SPSR_MON = 39,
 };
 
 #define ARMV4_5_COMMON_MAGIC 0x0A450A45
@@ -89,7 +91,15 @@ struct arm
 	int common_magic;
 	struct reg_cache *core_cache;
 
-	int /* armv4_5_mode */ core_mode;
+	/**
+	 * Indicates what registers are in the ARM state core register set.
+	 * ARMV4_5_MODE_ANY indicates the standard set of 37 registers,
+	 * seen on for example ARM7TDMI cores.  ARM_MODE_MON indicates three
+	 * more registers are shadowed, for "Secure Monitor" mode.
+	 */
+	enum armv4_5_mode core_type;
+
+	enum armv4_5_mode core_mode;
 	enum armv4_5_state core_state;
 
 	/** Flag reporting unavailability of the BKPT instruction. */
@@ -99,9 +109,9 @@ struct arm
 	struct etm_context *etm;
 
 	int (*full_context)(struct target *target);
-	int (*read_core_reg)(struct target *target,
+	int (*read_core_reg)(struct target *target, struct reg *reg,
 			int num, enum armv4_5_mode mode);
-	int (*write_core_reg)(struct target *target,
+	int (*write_core_reg)(struct target *target, struct reg *reg,
 			int num, enum armv4_5_mode mode, uint32_t value);
 	void *arch_info;
 };
@@ -127,12 +137,13 @@ struct armv4_5_algorithm
 	enum armv4_5_state core_state;
 };
 
-struct armv4_5_core_reg
+struct arm_reg
 {
 	int num;
 	enum armv4_5_mode mode;
 	struct target *target;
 	struct arm *armv4_5_common;
+	uint32_t value;
 };
 
 struct reg_cache* armv4_5_build_reg_cache(struct target *target,
@@ -151,8 +162,6 @@ int armv4_5_run_algorithm(struct target *target,
 		uint32_t entry_point, uint32_t exit_point,
 		int timeout_ms, void *arch_info);
 
-int armv4_5_invalidate_core_regs(struct target *target);
-
 int arm_checksum_memory(struct target *target,
 		uint32_t address, uint32_t count, uint32_t *checksum);
 int arm_blank_check_memory(struct target *target,