X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farmv4_5.h;h=9823f4e66b936b070d14d3d7c1bd06eabcc20a50;hp=d37f70977f1831457bd1ed457a9defccfd2d4417;hb=af949b2531d2a8863d077025db40cbb170d13a63;hpb=db7e77237c5a8104b527aeb23a2546b4bab92d8a

diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index d37f70977f..9823f4e66b 100644
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -5,6 +5,9 @@
  *   Copyright (C) 2008 by Spencer Oliver                                  *
  *   spen@spen-soft.co.uk                                                  *
  *                                                                         *
+ *   Copyright (C) 2009 by Øyvind Harboe                                   *
+ *   oyvind.harboe@zylin.com                                               *
+ *                                                                         *
  *   This program is free software; you can redistribute it and/or modify  *
  *   it under the terms of the GNU General Public License as published by  *
  *   the Free Software Foundation; either version 2 of the License, or     *
@@ -26,6 +29,7 @@
 #include "register.h"
 #include "target.h"
 #include "log.h"
+#include "etm.h"
 
 typedef enum armv4_5_mode
 {
@@ -70,35 +74,69 @@ enum
 
 #define ARMV4_5_COMMON_MAGIC 0x0A450A45
 
-typedef struct armv4_5_common_s
+/* NOTE:  this is being morphed into a generic toplevel holder for ARMs. */
+#define armv4_5_common_s arm
+
+/**
+ * Represents a generic ARM core, with standard application registers.
+ *
+ * There are sixteen application registers (including PC, SP, LR) and a PSR.
+ * Cortex-M series cores do not support as many core states or shadowed
+ * registers as traditional ARM cores, and only support Thumb2 instructions.
+ */
+struct arm
 {
 	int common_magic;
-	reg_cache_t *core_cache;
-	enum armv4_5_mode core_mode;
+	struct reg_cache *core_cache;
+
+	int /* armv4_5_mode */ core_mode;
 	enum armv4_5_state core_state;
+
+	/** Flag reporting unavailability of the BKPT instruction. */
+	bool is_armv4;
+
+	/** Handle for the Embedded Trace Module, if one is present. */
+	struct etm_context *etm;
+
 	int (*full_context)(struct target_s *target);
-	int (*read_core_reg)(struct target_s *target, int num, enum armv4_5_mode mode);
-	int (*write_core_reg)(struct target_s *target, int num, enum armv4_5_mode mode, uint32_t value);
+	int (*read_core_reg)(struct target_s *target,
+			int num, enum armv4_5_mode mode);
+	int (*write_core_reg)(struct target_s *target,
+			int num, enum armv4_5_mode mode, uint32_t value);
 	void *arch_info;
-} armv4_5_common_t;
+};
+
+#define target_to_armv4_5 target_to_arm
+
+/** Convert target handle to generic ARM target state handle. */
+static inline struct arm *target_to_arm(struct target_s *target)
+{
+	return target->arch_info;
+}
 
-typedef struct armv4_5_algorithm_s
+static inline bool is_arm(struct arm *arm)
+{
+	return arm && arm->common_magic == ARMV4_5_COMMON_MAGIC;
+}
+
+struct armv4_5_algorithm
 {
 	int common_magic;
 
 	enum armv4_5_mode core_mode;
 	enum armv4_5_state core_state;
-} armv4_5_algorithm_t;
+};
 
-typedef struct armv4_5_core_reg_s
+struct armv4_5_core_reg
 {
 	int num;
 	enum armv4_5_mode mode;
 	target_t *target;
-	armv4_5_common_t *armv4_5_common;
-} armv4_5_core_reg_t;
+	struct arm *armv4_5_common;
+};
 
-extern reg_cache_t* armv4_5_build_reg_cache(target_t *target, armv4_5_common_t *armv4_5_common);
+struct reg_cache* armv4_5_build_reg_cache(target_t *target,
+		struct arm *armv4_5_common);
 
 /* map psr mode bits to linear number */
 static __inline int armv4_5_mode_to_number(enum armv4_5_mode mode)
@@ -114,7 +152,7 @@ static __inline int armv4_5_mode_to_number(enum armv4_5_mode mode)
 		case ARMV4_5_MODE_SYS: return 6; break;
 		case ARMV4_5_MODE_ANY: return 0; break;	/* map MODE_ANY to user mode */
 		default:
-			LOG_ERROR("invalid mode value encountered");
+			LOG_ERROR("invalid mode value encountered %d", mode);
 			return -1;
 	}
 }
@@ -132,20 +170,25 @@ static __inline enum armv4_5_mode armv4_5_number_to_mode(int number)
 		case 5: return ARMV4_5_MODE_UND; break;
 		case 6: return ARMV4_5_MODE_SYS; break;
 		default:
-			LOG_ERROR("mode index out of bounds");
+			LOG_ERROR("mode index out of bounds %d", number);
 			return ARMV4_5_MODE_ANY;
 	}
 };
 
-extern int armv4_5_arch_state(struct target_s *target);
-extern int armv4_5_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size);
+int armv4_5_arch_state(struct target_s *target);
+int armv4_5_get_gdb_reg_list(target_t *target,
+		reg_t **reg_list[], int *reg_list_size);
 
-extern int armv4_5_register_commands(struct command_context_s *cmd_ctx);
-extern int armv4_5_init_arch_info(target_t *target, armv4_5_common_t *armv4_5);
+int armv4_5_register_commands(struct command_context_s *cmd_ctx);
+int armv4_5_init_arch_info(target_t *target, struct arm *armv4_5);
 
-extern int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info);
+int armv4_5_run_algorithm(struct target_s *target,
+		int num_mem_params, struct mem_param *mem_params,
+		int num_reg_params, struct reg_param *reg_params,
+		uint32_t entry_point, uint32_t exit_point,
+		int timeout_ms, void *arch_info);
 
-extern int armv4_5_invalidate_core_regs(target_t *target);
+int armv4_5_invalidate_core_regs(target_t *target);
 
 /* ARM mode instructions
  */
@@ -154,7 +197,7 @@ extern int armv4_5_invalidate_core_regs(target_t *target);
  * Rn: base register
  * List: for each bit in list: store register
  * S: in priviledged mode: store user-mode registers
- * W=1: update the base register. W=0: leave the base register untouched
+ * W = 1: update the base register. W = 0: leave the base register untouched
  */
 #define ARMV4_5_STMIA(Rn, List, S, W)	(0xe8800000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
 
@@ -162,7 +205,7 @@ extern int armv4_5_invalidate_core_regs(target_t *target);
  * Rn: base register
  * List: for each bit in list: store register
  * S: in priviledged mode: store user-mode registers
- * W=1: update the base register. W=0: leave the base register untouched
+ * W = 1: update the base register. W = 0: leave the base register untouched
  */
 #define ARMV4_5_LDMIA(Rn, List, S, W)	(0xe8900000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
 
@@ -170,7 +213,7 @@ extern int armv4_5_invalidate_core_regs(target_t *target);
 #define ARMV4_5_NOP					(0xe1a08008)
 
 /* Move PSR to general purpose register
- * R=1: SPSR R=0: CPSR
+ * R = 1: SPSR R = 0: CPSR
  * Rn: target register
  */
 #define ARMV4_5_MRS(Rn, R)			(0xe10f0000 | ((R) << 22) | ((Rn) << 12))
@@ -188,7 +231,7 @@ extern int armv4_5_invalidate_core_regs(target_t *target);
 #define ARMV4_5_LDR(Rd, Rn)			(0xe5900000 | ((Rd) << 12) | ((Rn) << 16))
 
 /* Move general purpose register to PSR
- * R=1: SPSR R=0: CPSR
+ * R = 1: SPSR R = 0: CPSR
  * Field: Field mask
  * 1: control field 2: extension field 4: status field 8: flags field
  * Rm: source register
@@ -314,4 +357,19 @@ extern int armv4_5_invalidate_core_regs(target_t *target);
  */
 #define ARMV5_T_BKPT(Im) ((0xbe00 | Im) | ((0xbe00 | Im) << 16))
 
+/* build basic mrc/mcr opcode */
+
+static inline uint32_t mrc_opcode(int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm)
+{
+	uint32_t t = 0;
+	t|=op1<<21;
+	t|=op2<<5;
+	t|=CRn<<16;
+	t|=CRm<<0;
+	return t;
+}
+
+
+
+
 #endif /* ARMV4_5_H */