X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farmv4_5.h;h=9823f4e66b936b070d14d3d7c1bd06eabcc20a50;hp=22069d1b0066a924580ba1ac9aec7d53de0ab2cb;hb=af949b2531d2a8863d077025db40cbb170d13a63;hpb=15e8e4530866454c18c5d91ad9e867f339c2e82b

diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index 22069d1b00..9823f4e66b 100644
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -84,10 +84,10 @@ enum
  * Cortex-M series cores do not support as many core states or shadowed
  * registers as traditional ARM cores, and only support Thumb2 instructions.
  */
-typedef struct arm
+struct arm
 {
 	int common_magic;
-	reg_cache_t *core_cache;
+	struct reg_cache *core_cache;
 
 	int /* armv4_5_mode */ core_mode;
 	enum armv4_5_state core_state;
@@ -96,7 +96,7 @@ typedef struct arm
 	bool is_armv4;
 
 	/** Handle for the Embedded Trace Module, if one is present. */
-	struct etm *etm;
+	struct etm_context *etm;
 
 	int (*full_context)(struct target_s *target);
 	int (*read_core_reg)(struct target_s *target,
@@ -104,7 +104,7 @@ typedef struct arm
 	int (*write_core_reg)(struct target_s *target,
 			int num, enum armv4_5_mode mode, uint32_t value);
 	void *arch_info;
-} armv4_5_common_t;
+};
 
 #define target_to_armv4_5 target_to_arm
 
@@ -127,16 +127,16 @@ struct armv4_5_algorithm
 	enum armv4_5_state core_state;
 };
 
-typedef struct armv4_5_core_reg_s
+struct armv4_5_core_reg
 {
 	int num;
 	enum armv4_5_mode mode;
 	target_t *target;
-	armv4_5_common_t *armv4_5_common;
-} armv4_5_core_reg_t;
+	struct arm *armv4_5_common;
+};
 
-reg_cache_t* armv4_5_build_reg_cache(target_t *target,
-		armv4_5_common_t *armv4_5_common);
+struct reg_cache* armv4_5_build_reg_cache(target_t *target,
+		struct arm *armv4_5_common);
 
 /* map psr mode bits to linear number */
 static __inline int armv4_5_mode_to_number(enum armv4_5_mode mode)
@@ -180,7 +180,7 @@ int armv4_5_get_gdb_reg_list(target_t *target,
 		reg_t **reg_list[], int *reg_list_size);
 
 int armv4_5_register_commands(struct command_context_s *cmd_ctx);
-int armv4_5_init_arch_info(target_t *target, armv4_5_common_t *armv4_5);
+int armv4_5_init_arch_info(target_t *target, struct arm *armv4_5);
 
 int armv4_5_run_algorithm(struct target_s *target,
 		int num_mem_params, struct mem_param *mem_params,