X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farmv4_5.h;h=822d14393b2eb94c00ca7573fe907fab8bd9e88d;hp=e3d053c98295dcc1b5ca2feaaace593b2add9a92;hb=66ee303456910f684244a20a0ac2e958d40b78cb;hpb=8a6d4ced4c0d17626c3875d5f8819efa3ac0f155

diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index e3d053c982..822d14393b 100644
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -27,6 +27,8 @@
 #define ARMV4_5_H
 
 #include "target.h"
+#include "command.h"
+
 
 typedef enum armv4_5_mode
 {
@@ -52,6 +54,7 @@ typedef enum armv4_5_state
 	ARMV4_5_STATE_ARM,
 	ARMV4_5_STATE_THUMB,
 	ARMV4_5_STATE_JAZELLE,
+	ARM_STATE_THUMB_EE,
 } armv4_5_state_t;
 
 extern char* armv4_5_state_strings[];
@@ -61,23 +64,11 @@ extern const int armv4_5_core_reg_map[8][17];
 #define ARMV4_5_CORE_REG_MODE(cache, mode, num) \
 		cache->reg_list[armv4_5_core_reg_map[armv4_5_mode_to_number(mode)][num]]
 
-/* offsets into armv4_5 core register cache */
-enum
-{
-	ARMV4_5_CPSR = 31,
-	ARMV4_5_SPSR_FIQ = 32,
-	ARMV4_5_SPSR_IRQ = 33,
-	ARMV4_5_SPSR_SVC = 34,
-	ARMV4_5_SPSR_ABT = 35,
-	ARMV4_5_SPSR_UND = 36,
-	ARM_SPSR_MON = 39,
-};
+/* offset into armv4_5 core register cache -- OBSOLETE, DO NOT USE! */
+enum { ARMV4_5_CPSR = 31, };
 
 #define ARMV4_5_COMMON_MAGIC 0x0A450A45
 
-/* NOTE:  this is being morphed into a generic toplevel holder for ARMs. */
-#define armv4_5_common_s arm
-
 /**
  * Represents a generic ARM core, with standard application registers.
  *
@@ -90,6 +81,14 @@ struct arm
 	int common_magic;
 	struct reg_cache *core_cache;
 
+	/** Handle to the CPSR; valid in all core modes. */
+	struct reg *cpsr;
+
+	/** Handle to the SPSR; valid only in core modes with an SPSR. */
+	struct reg *spsr;
+
+	const int *map;
+
 	/**
 	 * Indicates what registers are in the ARM state core register set.
 	 * ARMV4_5_MODE_ANY indicates the standard set of 37 registers,
@@ -104,13 +103,19 @@ struct arm
 	/** Flag reporting unavailability of the BKPT instruction. */
 	bool is_armv4;
 
+	/** Backpointer to the target. */
+	struct target *target;
+
+	/** Handle for the debug module, if one is present. */
+	struct arm_dpm *dpm;
+
 	/** Handle for the Embedded Trace Module, if one is present. */
 	struct etm_context *etm;
 
 	int (*full_context)(struct target *target);
-	int (*read_core_reg)(struct target *target,
+	int (*read_core_reg)(struct target *target, struct reg *reg,
 			int num, enum armv4_5_mode mode);
-	int (*write_core_reg)(struct target *target,
+	int (*write_core_reg)(struct target *target, struct reg *reg,
 			int num, enum armv4_5_mode mode, uint32_t value);
 	void *arch_info;
 };
@@ -136,12 +141,13 @@ struct armv4_5_algorithm
 	enum armv4_5_state core_state;
 };
 
-struct armv4_5_core_reg
+struct arm_reg
 {
 	int num;
 	enum armv4_5_mode mode;
 	struct target *target;
 	struct arm *armv4_5_common;
+	uint32_t value;
 };
 
 struct reg_cache* armv4_5_build_reg_cache(struct target *target,
@@ -151,7 +157,8 @@ int armv4_5_arch_state(struct target *target);
 int armv4_5_get_gdb_reg_list(struct target *target,
 		struct reg **reg_list[], int *reg_list_size);
 
-int armv4_5_register_commands(struct command_context *cmd_ctx);
+extern const struct command_registration arm_command_handlers[];
+
 int armv4_5_init_arch_info(struct target *target, struct arm *armv4_5);
 
 int armv4_5_run_algorithm(struct target *target,
@@ -160,13 +167,14 @@ int armv4_5_run_algorithm(struct target *target,
 		uint32_t entry_point, uint32_t exit_point,
 		int timeout_ms, void *arch_info);
 
-int armv4_5_invalidate_core_regs(struct target *target);
-
 int arm_checksum_memory(struct target *target,
 		uint32_t address, uint32_t count, uint32_t *checksum);
 int arm_blank_check_memory(struct target *target,
 		uint32_t address, uint32_t count, uint32_t *blank);
 
+void arm_set_cpsr(struct arm *arm, uint32_t cpsr);
+struct reg *arm_reg_current(struct arm *arm, unsigned regnum);
+
 extern struct reg arm_gdb_dummy_fp_reg;
 extern struct reg arm_gdb_dummy_fps_reg;