X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farmv4_5.c;h=eeb6694c93c28fd1590425ba409de19be51b4a63;hp=8d3a8917d11581cfaa2399ae42c5086237176c02;hb=0f3bbcf09683904c1f21b6961cbb0f36b07043c0;hpb=ce1feaa7322affd3b979c9fe93dd8f7462ea9eca

diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 8d3a8917d1..eeb6694c93 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -217,7 +217,7 @@ enum arm_mode armv4_5_number_to_mode(int number)
 	}
 }
 
-const char *arm_state_strings[] =
+static const char *arm_state_strings[] =
 {
 	"ARM", "Thumb", "Jazelle", "ThumbEE",
 };
@@ -577,6 +577,7 @@ struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm)
 		cache->num_regs++;
 	}
 
+	arm->pc = reg_list + 15;
 	arm->cpsr = reg_list + ARMV4_5_CPSR;
 	arm->core_cache = cache;
 	return cache;
@@ -598,8 +599,7 @@ int arm_arch_state(struct target *target)
 			debug_reason_name(target),
 			arm_mode_name(armv4_5->core_mode),
 			buf_get_u32(armv4_5->cpsr->value, 0, 32),
-			buf_get_u32(armv4_5->core_cache->reg_list[15].value,
-					0, 32),
+			buf_get_u32(armv4_5->pc->value, 0, 32),
 			armv4_5->is_semihosting ? ", semihosting" : "");
 
 	return ERROR_OK;
@@ -627,6 +627,12 @@ COMMAND_HANDLER(handle_armv4_5_reg_command)
 		return ERROR_FAIL;
 	}
 
+	if (armv4_5->core_type != ARM_MODE_ANY)
+	{
+		command_print(CMD_CTX, "Microcontroller Profile not supported - use standard reg cmd");
+		return ERROR_OK;
+	}
+
 	if (!is_arm_mode(armv4_5->core_mode))
 		return ERROR_FAIL;
 
@@ -706,6 +712,13 @@ COMMAND_HANDLER(handle_armv4_5_core_state_command)
 		return ERROR_FAIL;
 	}
 
+	if (armv4_5->core_type == ARM_MODE_THREAD)
+	{
+		/* armv7m not supported */
+		command_print(CMD_CTX, "Unsupported Command");
+		return ERROR_OK;
+	}
+
 	if (CMD_ARGC > 0)
 	{
 		if (strcmp(CMD_ARGV[0], "arm") == 0)
@@ -723,7 +736,7 @@ COMMAND_HANDLER(handle_armv4_5_core_state_command)
 	return ERROR_OK;
 }
 
-COMMAND_HANDLER(handle_armv4_5_disassemble_command)
+COMMAND_HANDLER(handle_arm_disassemble_command)
 {
 	int retval = ERROR_OK;
 	struct target *target = get_current_target(CMD_CTX);
@@ -737,6 +750,12 @@ COMMAND_HANDLER(handle_armv4_5_disassemble_command)
 		return ERROR_FAIL;
 	}
 
+	if (arm->core_type == ARM_MODE_THREAD)
+	{
+		/* armv7m is always thumb mode */
+		thumb = 1;
+	}
+
 	switch (CMD_ARGC) {
 	case 3:
 		if (strcmp(CMD_ARGV[2], "thumb") != 0)
@@ -925,6 +944,49 @@ static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
 	return JIM_OK;
 }
 
+COMMAND_HANDLER(handle_arm_semihosting_command)
+{
+	struct target *target = get_current_target(CMD_CTX);
+	struct arm *arm = target ? target_to_arm(target) : NULL;
+
+	if (!is_arm(arm)) {
+		command_print(CMD_CTX, "current target isn't an ARM");
+		return ERROR_FAIL;
+	}
+
+	if (!arm->setup_semihosting)
+	{
+		command_print(CMD_CTX, "semihosting not supported for current target");
+	}
+
+	if (CMD_ARGC > 0)
+	{
+		int semihosting;
+
+		COMMAND_PARSE_ENABLE(CMD_ARGV[0], semihosting);
+
+		if (!target_was_examined(target))
+		{
+			LOG_ERROR("Target not examined yet");
+			return ERROR_FAIL;
+		}
+
+		if (arm->setup_semihosting(target, semihosting) != ERROR_OK) {
+			LOG_ERROR("Failed to Configure semihosting");
+			return ERROR_FAIL;
+		}
+
+		/* FIXME never let that "catch" be dropped! */
+		arm->is_semihosting = semihosting;
+	}
+
+	command_print(CMD_CTX, "semihosting is %s",
+			arm->is_semihosting
+			? "enabled" : "disabled");
+
+	return ERROR_OK;
+}
+
 static const struct command_registration arm_exec_command_handlers[] = {
 	{
 		.name = "reg",
@@ -941,7 +1003,7 @@ static const struct command_registration arm_exec_command_handlers[] = {
 	},
 	{
 		.name = "disassemble",
-		.handler = handle_armv4_5_disassemble_command,
+		.handler = handle_arm_disassemble_command,
 		.mode = COMMAND_EXEC,
 		.usage = "address [count ['thumb']]",
 		.help = "disassemble instructions ",
@@ -959,6 +1021,13 @@ static const struct command_registration arm_exec_command_handlers[] = {
 		.help = "read coprocessor register",
 		.usage = "cpnum op1 CRn op2 CRm",
 	},
+	{
+		"semihosting",
+		.handler = handle_arm_semihosting_command,
+		.mode = COMMAND_EXEC,
+		.usage = "['enable'|'disable']",
+		.help = "activate support for semihosting operations",
+	},
 
 	COMMAND_REGISTRATION_DONE
 };
@@ -1018,11 +1087,10 @@ static int armv4_5_run_algorithm_completion(struct target *target, uint32_t exit
 	}
 
 	/* fast exit: ARMv5+ code can use BKPT */
-	if (exit_point && buf_get_u32(armv4_5->core_cache->reg_list[15].value,
-				0, 32) != exit_point)
+	if (exit_point && buf_get_u32(armv4_5->pc->value, 0, 32) != exit_point)
 	{
 		LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "",
-			buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
+			buf_get_u32(armv4_5->pc->value, 0, 32));
 		return ERROR_TARGET_TIMEOUT;
 	}