X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farmv4_5.c;h=e092063ae1c52005ec0c373d63e428541190d858;hp=51fd4b42732dc8813a8dd4d6de7c28a46b197740;hb=68c598e88d5e09728ea845a81ab279c615bbaf0f;hpb=8b4e882a1630d63bbc9840fa3f968e36b6ac3702 diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c index 51fd4b4273..e092063ae1 100644 --- a/src/target/armv4_5.c +++ b/src/target/armv4_5.c @@ -2,6 +2,9 @@ * Copyright (C) 2005 by Dominic Rath * * Dominic.Rath@gmx.de * * * + * Copyright (C) 2008 by Spencer Oliver * + * spen@spen-soft.co.uk * + * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * * the Free Software Foundation; either version 2 of the License, or * @@ -17,7 +20,13 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ +#ifdef HAVE_CONFIG_H #include "config.h" +#endif + +#include "replacements.h" + +#include "arm_disassembler.h" #include "armv4_5.h" @@ -64,11 +73,14 @@ char* armv4_5_core_reg_list[] = "cpsr", "spsr_fiq", "spsr_irq", "spsr_svc", "spsr_abt", "spsr_und" }; -char* armv4_5_mode_strings[] = +char * armv4_5_mode_strings_list[] = { - "User", "FIQ", "IRQ", "Supervisor", "Abort", "Undefined", "System" + "Illegal mode value", "User", "FIQ", "IRQ", "Supervisor", "Abort", "Undefined", "System" }; +/* Hack! Yuk! allow -1 index, which simplifies codepaths elsewhere in the code */ +char** armv4_5_mode_strings = armv4_5_mode_strings_list+1; + char* armv4_5_state_strings[] = { "ARM", "Thumb", "Jazelle" @@ -163,42 +175,6 @@ reg_t armv4_5_gdb_dummy_fps_reg = "GDB dummy floating-point status register", armv4_5_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0 }; -/* map psr mode bits to linear number */ -int armv4_5_mode_to_number(enum armv4_5_mode mode) -{ - switch (mode) - { - case 16: return 0; break; - case 17: return 1; break; - case 18: return 2; break; - case 19: return 3; break; - case 23: return 4; break; - case 27: return 5; break; - case 31: return 6; break; - case -1: return 0; break; /* map MODE_ANY to user mode */ - default: - ERROR("invalid mode value encountered"); - return -1; - } -} - -/* map linear number to mode bits */ -enum armv4_5_mode armv4_5_number_to_mode(int number) -{ - switch(number) - { - case 0: return ARMV4_5_MODE_USR; break; - case 1: return ARMV4_5_MODE_FIQ; break; - case 2: return ARMV4_5_MODE_IRQ; break; - case 3: return ARMV4_5_MODE_SVC; break; - case 4: return ARMV4_5_MODE_ABT; break; - case 5: return ARMV4_5_MODE_UND; break; - case 6: return ARMV4_5_MODE_SYS; break; - default: - ERROR("mode index out of bounds"); - return -1; - } -}; int armv4_5_get_core_reg(reg_t *reg) { @@ -208,25 +184,59 @@ int armv4_5_get_core_reg(reg_t *reg) if (target->state != TARGET_HALTED) { + LOG_ERROR("Target not halted"); return ERROR_TARGET_NOT_HALTED; } - //retval = armv4_5->armv4_5_common->full_context(target); + /* retval = armv4_5->armv4_5_common->full_context(target); */ retval = armv4_5->armv4_5_common->read_core_reg(target, armv4_5->num, armv4_5->mode); return retval; } -int armv4_5_set_core_reg(reg_t *reg, u32 value) +int armv4_5_set_core_reg(reg_t *reg, u8 *buf) { armv4_5_core_reg_t *armv4_5 = reg->arch_info; target_t *target = armv4_5->target; + armv4_5_common_t *armv4_5_target = target->arch_info; + u32 value = buf_get_u32(buf, 0, 32); if (target->state != TARGET_HALTED) { return ERROR_TARGET_NOT_HALTED; } + if (reg == &armv4_5_target->core_cache->reg_list[ARMV4_5_CPSR]) + { + if (value & 0x20) + { + /* T bit should be set */ + if (armv4_5_target->core_state == ARMV4_5_STATE_ARM) + { + /* change state to Thumb */ + LOG_DEBUG("changing to Thumb state"); + armv4_5_target->core_state = ARMV4_5_STATE_THUMB; + } + } + else + { + /* T bit should be cleared */ + if (armv4_5_target->core_state == ARMV4_5_STATE_THUMB) + { + /* change state to ARM */ + LOG_DEBUG("changing to ARM state"); + armv4_5_target->core_state = ARMV4_5_STATE_ARM; + } + } + + if (armv4_5_target->core_mode != (value & 0x1f)) + { + LOG_DEBUG("changing ARM core mode to '%s'", armv4_5_mode_strings[armv4_5_mode_to_number(value & 0x1f)]); + armv4_5_target->core_mode = value & 0x1f; + armv4_5_target->write_core_reg(target, 16, ARMV4_5_MODE_ANY, value); + } + } + buf_set_u32(reg->value, 0, 32, value); reg->dirty = 1; reg->valid = 1; @@ -253,7 +263,7 @@ reg_cache_t* armv4_5_build_reg_cache(target_t *target, armv4_5_common_t *armv4_5 int num_regs = 37; reg_cache_t *cache = malloc(sizeof(reg_cache_t)); reg_t *reg_list = malloc(sizeof(reg_t) * num_regs); - armv4_5_core_reg_t *arch_info = malloc(sizeof(reg_t) * num_regs); + armv4_5_core_reg_t *arch_info = malloc(sizeof(armv4_5_core_reg_t) * num_regs); int i; cache->name = "arm v4/5 registers"; @@ -283,20 +293,19 @@ reg_cache_t* armv4_5_build_reg_cache(target_t *target, armv4_5_common_t *armv4_5 return cache; } -int armv4_5_arch_state(struct target_s *target, char *buf, int buf_size) +int armv4_5_arch_state(struct target_s *target) { armv4_5_common_t *armv4_5 = target->arch_info; if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) { - ERROR("BUG: called for a non-ARMv4/5 target"); + LOG_ERROR("BUG: called for a non-ARMv4/5 target"); exit(-1); } - snprintf(buf, buf_size, - "target halted in %s state due to %s, current mode: %s\ncpsr: 0x%8.8x pc: 0x%8.8x", + LOG_USER("target halted in %s state due to %s, current mode: %s\ncpsr: 0x%8.8x pc: 0x%8.8x", armv4_5_state_strings[armv4_5->core_state], - target_debug_reason_strings[target->debug_reason], + Jim_Nvp_value2name_simple( nvp_target_debug_reason, target->debug_reason )->name, armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)], buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32), buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); @@ -324,6 +333,9 @@ int handle_armv4_5_reg_command(struct command_context_s *cmd_ctx, char *cmd, cha return ERROR_OK; } + if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) + return ERROR_FAIL; + for (num = 0; num <= 15; num++) { output_len = 0; @@ -377,15 +389,57 @@ int handle_armv4_5_core_state_command(struct command_context_s *cmd_ctx, char *c return ERROR_OK; } +int handle_armv4_5_disassemble_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +{ + target_t *target = get_current_target(cmd_ctx); + armv4_5_common_t *armv4_5 = target->arch_info; + u32 address; + int count; + int i; + arm_instruction_t cur_instruction; + u32 opcode; + int thumb = 0; + + if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) + { + command_print(cmd_ctx, "current target isn't an ARMV4/5 target"); + return ERROR_OK; + } + + if (argc < 2) + { + command_print(cmd_ctx, "usage: armv4_5 disassemble
['thumb']"); + return ERROR_OK; + } + + address = strtoul(args[0], NULL, 0); + count = strtoul(args[1], NULL, 0); + + if (argc >= 3) + if (strcmp(args[2], "thumb") == 0) + thumb = 1; + + for (i = 0; i < count; i++) + { + target_read_u32(target, address, &opcode); + arm_evaluate_opcode(opcode, address, &cur_instruction); + command_print(cmd_ctx, "%s", cur_instruction.text); + address += (thumb) ? 2 : 4; + } + + return ERROR_OK; +} + int armv4_5_register_commands(struct command_context_s *cmd_ctx) { command_t *armv4_5_cmd; - armv4_5_cmd = register_command(cmd_ctx, NULL, "armv4_5", NULL, COMMAND_ANY, NULL); + armv4_5_cmd = register_command(cmd_ctx, NULL, "armv4_5", NULL, COMMAND_ANY, "armv4/5 specific commands"); register_command(cmd_ctx, armv4_5_cmd, "reg", handle_armv4_5_reg_command, COMMAND_EXEC, "display ARM core registers"); register_command(cmd_ctx, armv4_5_cmd, "core_state", handle_armv4_5_core_state_command, COMMAND_EXEC, "display/change ARM core state "); + register_command(cmd_ctx, armv4_5_cmd, "disassemble", handle_armv4_5_disassemble_command, COMMAND_EXEC, "disassemble instructions
['thumb']"); return ERROR_OK; } @@ -394,10 +448,8 @@ int armv4_5_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list armv4_5_common_t *armv4_5 = target->arch_info; int i; - if (target->state != TARGET_HALTED) - { - return ERROR_TARGET_NOT_HALTED; - } + if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) + return ERROR_FAIL; *reg_list_size = 26; *reg_list = malloc(sizeof(reg_t*) * (*reg_list_size)); @@ -429,19 +481,23 @@ int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, mem_param int exit_breakpoint_size = 0; int i; int retval = ERROR_OK; + LOG_DEBUG("Running algorithm"); if (armv4_5_algorithm_info->common_magic != ARMV4_5_COMMON_MAGIC) { - ERROR("current target isn't an ARMV4/5 target"); + LOG_ERROR("current target isn't an ARMV4/5 target"); return ERROR_TARGET_INVALID; } if (target->state != TARGET_HALTED) { - WARNING("target not halted"); + LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } + if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) + return ERROR_FAIL; + for (i = 0; i <= 16; i++) { if (!ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).valid) @@ -460,17 +516,17 @@ int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, mem_param reg_t *reg = register_get_by_name(armv4_5->core_cache, reg_params[i].reg_name, 0); if (!reg) { - ERROR("BUG: register '%s' not found", reg_params[i].reg_name); + LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name); exit(-1); } if (reg->size != reg_params[i].size) { - ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name); + LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name); exit(-1); } - armv4_5_set_core_reg(reg, buf_get_u32(reg_params[i].value, 0, 32)); + armv4_5_set_core_reg(reg, reg_params[i].value); } armv4_5->core_state = armv4_5_algorithm_info->core_state; @@ -480,13 +536,13 @@ int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, mem_param exit_breakpoint_size = 2; else { - ERROR("BUG: can't execute algorithms when not in ARM or Thumb state"); + LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state"); exit(-1); } if (armv4_5_algorithm_info->core_mode != ARMV4_5_MODE_ANY) { - DEBUG("setting core_mode: 0x%2.2x", armv4_5_algorithm_info->core_mode); + LOG_DEBUG("setting core_mode: 0x%2.2x", armv4_5_algorithm_info->core_mode); buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 5, armv4_5_algorithm_info->core_mode); armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1; armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1; @@ -494,34 +550,29 @@ int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, mem_param if ((retval = breakpoint_add(target, exit_point, exit_breakpoint_size, BKPT_HARD)) != ERROR_OK) { - ERROR("can't add breakpoint to finish algorithm execution"); + LOG_ERROR("can't add breakpoint to finish algorithm execution"); return ERROR_TARGET_FAILURE; } - target->type->resume(target, 0, entry_point, 1, 1); - target->type->poll(target); + target_resume(target, 0, entry_point, 1, 1); - while (target->state != TARGET_HALTED) + target_wait_state(target, TARGET_HALTED, timeout_ms); + if (target->state != TARGET_HALTED) { - usleep(10000); - target->type->poll(target); - if ((timeout_ms -= 10) <= 0) + if ((retval=target_halt(target))!=ERROR_OK) + return retval; + if ((retval=target_wait_state(target, TARGET_HALTED, 500))!=ERROR_OK) { - ERROR("timeout waiting for algorithm to complete, trying to halt target"); - target->type->halt(target); - timeout_ms = 1000; - while (target->state != TARGET_HALTED) - { - usleep(10000); - target->type->poll(target); - if ((timeout_ms -= 10) <= 0) - { - ERROR("target didn't reenter debug state, exiting"); - exit(-1); - } - } - retval = ERROR_TARGET_TIMEOUT; + return retval; } + return ERROR_TARGET_TIMEOUT; + } + + if (buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32) != exit_point) + { + LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4x", + buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); + return ERROR_TARGET_TIMEOUT; } breakpoint_remove(target, exit_point); @@ -540,13 +591,13 @@ int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, mem_param reg_t *reg = register_get_by_name(armv4_5->core_cache, reg_params[i].reg_name, 0); if (!reg) { - ERROR("BUG: register '%s' not found", reg_params[i].reg_name); + LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name); exit(-1); } if (reg->size != reg_params[i].size) { - ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name); + LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name); exit(-1); } @@ -556,7 +607,7 @@ int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, mem_param for (i = 0; i <= 16; i++) { - DEBUG("restoring register %s with value 0x%8.8x", ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).name, buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32)); + LOG_DEBUG("restoring register %s with value 0x%8.8x", ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).name, context[i]); buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32, context[i]); ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).valid = 1; ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).dirty = 1;