X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farmv4_5.c;h=b5e33ff5466fdf2ec010349c24e2db57830c97e0;hp=eebf866a7ab67ff4cc57d3adf3cf7bbf424af23e;hb=c4992c6d863d0ead91d84d19bbfe1643d720b205;hpb=570631454df083f2af26e453939424a14a9684f1 diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c index eebf866a7a..b5e33ff546 100644 --- a/src/target/armv4_5.c +++ b/src/target/armv4_5.c @@ -28,112 +28,295 @@ #endif #include "armv4_5.h" +#include "arm_jtag.h" +#include "breakpoints.h" #include "arm_disassembler.h" #include "binarybuffer.h" +#include "algorithm.h" +#include "register.h" + + +/* offsets into armv4_5 core register cache */ +enum { +// ARMV4_5_CPSR = 31, + ARMV4_5_SPSR_FIQ = 32, + ARMV4_5_SPSR_IRQ = 33, + ARMV4_5_SPSR_SVC = 34, + ARMV4_5_SPSR_ABT = 35, + ARMV4_5_SPSR_UND = 36, + ARM_SPSR_MON = 39, +}; - -bitfield_desc_t armv4_5_psr_bitfield_desc[] = -{ - {"M[4:0]", 5}, - {"T", 1}, - {"F", 1}, - {"I", 1}, - {"reserved", 16}, - {"J", 1}, - {"reserved", 2}, - {"Q", 1}, - {"V", 1}, - {"C", 1}, - {"Z", 1}, - {"N", 1}, +static const uint8_t arm_usr_indices[17] = { + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, ARMV4_5_CPSR, }; -char* armv4_5_core_reg_list[] = -{ - "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13_usr", "lr_usr", "pc", +static const uint8_t arm_fiq_indices[8] = { + 16, 17, 18, 19, 20, 21, 22, ARMV4_5_SPSR_FIQ, +}; - "r8_fiq", "r9_fiq", "r10_fiq", "r11_fiq", "r12_fiq", "r13_fiq", "lr_fiq", +static const uint8_t arm_irq_indices[3] = { + 23, 24, ARMV4_5_SPSR_IRQ, +}; - "r13_irq", "lr_irq", +static const uint8_t arm_svc_indices[3] = { + 25, 26, ARMV4_5_SPSR_SVC, +}; - "r13_svc", "lr_svc", +static const uint8_t arm_abt_indices[3] = { + 27, 28, ARMV4_5_SPSR_ABT, +}; - "r13_abt", "lr_abt", +static const uint8_t arm_und_indices[3] = { + 29, 30, ARMV4_5_SPSR_UND, +}; - "r13_und", "lr_und", +static const uint8_t arm_mon_indices[3] = { + 37, 38, ARM_SPSR_MON, +}; - "cpsr", "spsr_fiq", "spsr_irq", "spsr_svc", "spsr_abt", "spsr_und" +static const struct { + const char *name; + unsigned short psr; + /* For user and system modes, these list indices for all registers. + * otherwise they're just indices for the shadow registers and SPSR. + */ + unsigned short n_indices; + const uint8_t *indices; +} arm_mode_data[] = { + /* Seven modes are standard from ARM7 on. "System" and "User" share + * the same registers; other modes shadow from 3 to 8 registers. + */ + { + .name = "User", + .psr = ARMV4_5_MODE_USR, + .n_indices = ARRAY_SIZE(arm_usr_indices), + .indices = arm_usr_indices, + }, + { + .name = "FIQ", + .psr = ARMV4_5_MODE_FIQ, + .n_indices = ARRAY_SIZE(arm_fiq_indices), + .indices = arm_fiq_indices, + }, + { + .name = "Supervisor", + .psr = ARMV4_5_MODE_SVC, + .n_indices = ARRAY_SIZE(arm_svc_indices), + .indices = arm_svc_indices, + }, + { + .name = "Abort", + .psr = ARMV4_5_MODE_ABT, + .n_indices = ARRAY_SIZE(arm_abt_indices), + .indices = arm_abt_indices, + }, + { + .name = "IRQ", + .psr = ARMV4_5_MODE_IRQ, + .n_indices = ARRAY_SIZE(arm_irq_indices), + .indices = arm_irq_indices, + }, + { + .name = "Undefined instruction", + .psr = ARMV4_5_MODE_UND, + .n_indices = ARRAY_SIZE(arm_und_indices), + .indices = arm_und_indices, + }, + { + .name = "System", + .psr = ARMV4_5_MODE_SYS, + .n_indices = ARRAY_SIZE(arm_usr_indices), + .indices = arm_usr_indices, + }, + /* TrustZone "Security Extensions" add a secure monitor mode. + * This is distinct from a "debug monitor" which can support + * non-halting debug, in conjunction with some debuggers. + */ + { + .name = "Secure Monitor", + .psr = ARM_MODE_MON, + .n_indices = ARRAY_SIZE(arm_mon_indices), + .indices = arm_mon_indices, + }, }; -char * armv4_5_mode_strings_list[] = +/** Map PSR mode bits to the name of an ARM processor operating mode. */ +const char *arm_mode_name(unsigned psr_mode) { - "Illegal mode value", "User", "FIQ", "IRQ", "Supervisor", "Abort", "Undefined", "System" -}; + for (unsigned i = 0; i < ARRAY_SIZE(arm_mode_data); i++) { + if (arm_mode_data[i].psr == psr_mode) + return arm_mode_data[i].name; + } + LOG_ERROR("unrecognized psr mode: %#02x", psr_mode); + return "UNRECOGNIZED"; +} -/* Hack! Yuk! allow -1 index, which simplifies codepaths elsewhere in the code */ -char** armv4_5_mode_strings = armv4_5_mode_strings_list+1; +/** Return true iff the parameter denotes a valid ARM processor mode. */ +bool is_arm_mode(unsigned psr_mode) +{ + for (unsigned i = 0; i < ARRAY_SIZE(arm_mode_data); i++) { + if (arm_mode_data[i].psr == psr_mode) + return true; + } + return false; +} -char* armv4_5_state_strings[] = +/** Map PSR mode bits to linear number indexing armv4_5_core_reg_map */ +int armv4_5_mode_to_number(enum armv4_5_mode mode) { - "ARM", "Thumb", "Jazelle" -}; + switch (mode) { + case ARMV4_5_MODE_ANY: + /* map MODE_ANY to user mode */ + case ARMV4_5_MODE_USR: + return 0; + case ARMV4_5_MODE_FIQ: + return 1; + case ARMV4_5_MODE_IRQ: + return 2; + case ARMV4_5_MODE_SVC: + return 3; + case ARMV4_5_MODE_ABT: + return 4; + case ARMV4_5_MODE_UND: + return 5; + case ARMV4_5_MODE_SYS: + return 6; + case ARM_MODE_MON: + return 7; + default: + LOG_ERROR("invalid mode value encountered %d", mode); + return -1; + } +} -int armv4_5_core_reg_arch_type = -1; +/** Map linear number indexing armv4_5_core_reg_map to PSR mode bits. */ +enum armv4_5_mode armv4_5_number_to_mode(int number) +{ + switch (number) { + case 0: + return ARMV4_5_MODE_USR; + case 1: + return ARMV4_5_MODE_FIQ; + case 2: + return ARMV4_5_MODE_IRQ; + case 3: + return ARMV4_5_MODE_SVC; + case 4: + return ARMV4_5_MODE_ABT; + case 5: + return ARMV4_5_MODE_UND; + case 6: + return ARMV4_5_MODE_SYS; + case 7: + return ARM_MODE_MON; + default: + LOG_ERROR("mode index out of bounds %d", number); + return ARMV4_5_MODE_ANY; + } +} -armv4_5_core_reg_t armv4_5_core_reg_list_arch_info[] = +char* armv4_5_state_strings[] = { - {0, ARMV4_5_MODE_ANY, NULL, NULL}, - {1, ARMV4_5_MODE_ANY, NULL, NULL}, - {2, ARMV4_5_MODE_ANY, NULL, NULL}, - {3, ARMV4_5_MODE_ANY, NULL, NULL}, - {4, ARMV4_5_MODE_ANY, NULL, NULL}, - {5, ARMV4_5_MODE_ANY, NULL, NULL}, - {6, ARMV4_5_MODE_ANY, NULL, NULL}, - {7, ARMV4_5_MODE_ANY, NULL, NULL}, - {8, ARMV4_5_MODE_ANY, NULL, NULL}, - {9, ARMV4_5_MODE_ANY, NULL, NULL}, - {10, ARMV4_5_MODE_ANY, NULL, NULL}, - {11, ARMV4_5_MODE_ANY, NULL, NULL}, - {12, ARMV4_5_MODE_ANY, NULL, NULL}, - {13, ARMV4_5_MODE_USR, NULL, NULL}, - {14, ARMV4_5_MODE_USR, NULL, NULL}, - {15, ARMV4_5_MODE_ANY, NULL, NULL}, - - {8, ARMV4_5_MODE_FIQ, NULL, NULL}, - {9, ARMV4_5_MODE_FIQ, NULL, NULL}, - {10, ARMV4_5_MODE_FIQ, NULL, NULL}, - {11, ARMV4_5_MODE_FIQ, NULL, NULL}, - {12, ARMV4_5_MODE_FIQ, NULL, NULL}, - {13, ARMV4_5_MODE_FIQ, NULL, NULL}, - {14, ARMV4_5_MODE_FIQ, NULL, NULL}, - - {13, ARMV4_5_MODE_IRQ, NULL, NULL}, - {14, ARMV4_5_MODE_IRQ, NULL, NULL}, - - {13, ARMV4_5_MODE_SVC, NULL, NULL}, - {14, ARMV4_5_MODE_SVC, NULL, NULL}, - - {13, ARMV4_5_MODE_ABT, NULL, NULL}, - {14, ARMV4_5_MODE_ABT, NULL, NULL}, - - {13, ARMV4_5_MODE_UND, NULL, NULL}, - {14, ARMV4_5_MODE_UND, NULL, NULL}, - - {16, ARMV4_5_MODE_ANY, NULL, NULL}, - {16, ARMV4_5_MODE_FIQ, NULL, NULL}, - {16, ARMV4_5_MODE_IRQ, NULL, NULL}, - {16, ARMV4_5_MODE_SVC, NULL, NULL}, - {16, ARMV4_5_MODE_ABT, NULL, NULL}, - {16, ARMV4_5_MODE_UND, NULL, NULL} + "ARM", "Thumb", "Jazelle", "ThumbEE", }; -/* map core mode (USR, FIQ, ...) and register number to indizes into the register cache */ -int armv4_5_core_reg_map[7][17] = +/* Templates for ARM core registers. + * + * NOTE: offsets in this table are coupled to the arm_mode_data + * table above, the armv4_5_core_reg_map array below, and also to + * the ARMV4_5_CPSR symbol (which should vanish after ARM11 updates). + */ +static const struct { + /* The name is used for e.g. the "regs" command. */ + const char *name; + + /* The {cookie, mode} tuple uniquely identifies one register. + * In a given mode, cookies 0..15 map to registers R0..R15, + * with R13..R15 usually called SP, LR, PC. + * + * MODE_ANY is used as *input* to the mapping, and indicates + * various special cases (sigh) and errors. + * + * Cookie 16 is (currently) confusing, since it indicates + * CPSR -or- SPSR depending on whether 'mode' is MODE_ANY. + * (Exception modes have both CPSR and SPSR registers ...) + */ + unsigned cookie; + enum armv4_5_mode mode; +} arm_core_regs[] = { + /* IMPORTANT: we guarantee that the first eight cached registers + * correspond to r0..r7, and the fifteenth to PC, so that callers + * don't need to map them. + */ + { .name = "r0", .cookie = 0, .mode = ARMV4_5_MODE_ANY, }, + { .name = "r1", .cookie = 1, .mode = ARMV4_5_MODE_ANY, }, + { .name = "r2", .cookie = 2, .mode = ARMV4_5_MODE_ANY, }, + { .name = "r3", .cookie = 3, .mode = ARMV4_5_MODE_ANY, }, + { .name = "r4", .cookie = 4, .mode = ARMV4_5_MODE_ANY, }, + { .name = "r5", .cookie = 5, .mode = ARMV4_5_MODE_ANY, }, + { .name = "r6", .cookie = 6, .mode = ARMV4_5_MODE_ANY, }, + { .name = "r7", .cookie = 7, .mode = ARMV4_5_MODE_ANY, }, + + /* NOTE: regs 8..12 might be shadowed by FIQ ... flagging + * them as MODE_ANY creates special cases. (ANY means + * "not mapped" elsewhere; here it's "everything but FIQ".) + */ + { .name = "r8", .cookie = 8, .mode = ARMV4_5_MODE_ANY, }, + { .name = "r9", .cookie = 9, .mode = ARMV4_5_MODE_ANY, }, + { .name = "r10", .cookie = 10, .mode = ARMV4_5_MODE_ANY, }, + { .name = "r11", .cookie = 11, .mode = ARMV4_5_MODE_ANY, }, + { .name = "r12", .cookie = 12, .mode = ARMV4_5_MODE_ANY, }, + + /* NOTE all MODE_USR registers are equivalent to MODE_SYS ones */ + { .name = "sp_usr", .cookie = 13, .mode = ARMV4_5_MODE_USR, }, + { .name = "lr_usr", .cookie = 14, .mode = ARMV4_5_MODE_USR, }, + + /* guaranteed to be at index 15 */ + { .name = "pc", .cookie = 15, .mode = ARMV4_5_MODE_ANY, }, + + { .name = "r8_fiq", .cookie = 8, .mode = ARMV4_5_MODE_FIQ, }, + { .name = "r9_fiq", .cookie = 9, .mode = ARMV4_5_MODE_FIQ, }, + { .name = "r10_fiq", .cookie = 10, .mode = ARMV4_5_MODE_FIQ, }, + { .name = "r11_fiq", .cookie = 11, .mode = ARMV4_5_MODE_FIQ, }, + { .name = "r12_fiq", .cookie = 12, .mode = ARMV4_5_MODE_FIQ, }, + + { .name = "lr_fiq", .cookie = 13, .mode = ARMV4_5_MODE_FIQ, }, + { .name = "sp_fiq", .cookie = 14, .mode = ARMV4_5_MODE_FIQ, }, + + { .name = "lr_irq", .cookie = 13, .mode = ARMV4_5_MODE_IRQ, }, + { .name = "sp_irq", .cookie = 14, .mode = ARMV4_5_MODE_IRQ, }, + + { .name = "lr_svc", .cookie = 13, .mode = ARMV4_5_MODE_SVC, }, + { .name = "sp_svc", .cookie = 14, .mode = ARMV4_5_MODE_SVC, }, + + { .name = "lr_abt", .cookie = 13, .mode = ARMV4_5_MODE_ABT, }, + { .name = "sp_abt", .cookie = 14, .mode = ARMV4_5_MODE_ABT, }, + + { .name = "lr_und", .cookie = 13, .mode = ARMV4_5_MODE_UND, }, + { .name = "sp_und", .cookie = 14, .mode = ARMV4_5_MODE_UND, }, + + { .name = "cpsr", .cookie = 16, .mode = ARMV4_5_MODE_ANY, }, + { .name = "spsr_fiq", .cookie = 16, .mode = ARMV4_5_MODE_FIQ, }, + { .name = "spsr_irq", .cookie = 16, .mode = ARMV4_5_MODE_IRQ, }, + { .name = "spsr_svc", .cookie = 16, .mode = ARMV4_5_MODE_SVC, }, + { .name = "spsr_abt", .cookie = 16, .mode = ARMV4_5_MODE_ABT, }, + { .name = "spsr_und", .cookie = 16, .mode = ARMV4_5_MODE_UND, }, + + { .name = "lr_mon", .cookie = 13, .mode = ARM_MODE_MON, }, + { .name = "sp_mon", .cookie = 14, .mode = ARM_MODE_MON, }, + { .name = "spsr_mon", .cookie = 16, .mode = ARM_MODE_MON, }, +}; + +/* map core mode (USR, FIQ, ...) and register number to + * indices into the register cache + */ +const int armv4_5_core_reg_map[8][17] = { { /* USR */ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31 }, - { /* FIQ */ + { /* FIQ (8 shadows of USR, vs normal 3) */ 0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 15, 32 }, { /* IRQ */ @@ -148,30 +331,146 @@ int armv4_5_core_reg_map[7][17] = { /* UND */ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 29, 30, 15, 36 }, - { /* SYS */ + { /* SYS (same registers as USR) */ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31 + }, + { /* MON */ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 37, 38, 15, 39, } }; -u8 armv4_5_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +/** + * Configures host-side ARM records to reflect the specified CPSR. + * Later, code can use arm_reg_current() to map register numbers + * according to how they are exposed by this mode. + */ +void arm_set_cpsr(struct arm *arm, uint32_t cpsr) +{ + enum armv4_5_mode mode = cpsr & 0x1f; + int num; + + /* NOTE: this may be called very early, before the register + * cache is set up. We can't defend against many errors, in + * particular against CPSRs that aren't valid *here* ... + */ + if (arm->cpsr) { + buf_set_u32(arm->cpsr->value, 0, 32, cpsr); + arm->cpsr->valid = 1; + arm->cpsr->dirty = 0; + } + + arm->core_mode = mode; -reg_t armv4_5_gdb_dummy_fp_reg = + /* mode_to_number() warned; set up a somewhat-sane mapping */ + num = armv4_5_mode_to_number(mode); + if (num < 0) { + mode = ARMV4_5_MODE_USR; + num = 0; + } + + arm->map = &armv4_5_core_reg_map[num][0]; + arm->spsr = (mode == ARMV4_5_MODE_USR || mode == ARMV4_5_MODE_SYS) + ? NULL + : arm->core_cache->reg_list + arm->map[16]; + + /* Older ARMs won't have the J bit */ + enum armv4_5_state state; + + if (cpsr & (1 << 5)) { /* T */ + if (cpsr & (1 << 24)) { /* J */ + LOG_WARNING("ThumbEE -- incomplete support"); + state = ARM_STATE_THUMB_EE; + } else + state = ARMV4_5_STATE_THUMB; + } else { + if (cpsr & (1 << 24)) { /* J */ + LOG_ERROR("Jazelle state handling is BROKEN!"); + state = ARMV4_5_STATE_JAZELLE; + } else + state = ARMV4_5_STATE_ARM; + } + arm->core_state = state; + + LOG_DEBUG("set CPSR %#8.8x: %s mode, %s state", (unsigned) cpsr, + arm_mode_name(mode), + armv4_5_state_strings[arm->core_state]); +} + +/** + * Returns handle to the register currently mapped to a given number. + * Someone must have called arm_set_cpsr() before. + * + * \param arm This core's state and registers are used. + * \param regnum From 0..15 corresponding to R0..R14 and PC. + * Note that R0..R7 don't require mapping; you may access those + * as the first eight entries in the register cache. Likewise + * R15 (PC) doesn't need mapping; you may also access it directly. + * However, R8..R14, and SPSR (arm->spsr) *must* be mapped. + * CPSR (arm->cpsr) is also not mapped. + */ +struct reg *arm_reg_current(struct arm *arm, unsigned regnum) { - "GDB dummy floating-point register", armv4_5_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0 + struct reg *r; + + if (regnum > 16) + return NULL; + + r = arm->core_cache->reg_list + arm->map[regnum]; + + /* e.g. invalid CPSR said "secure monitor" mode on a core + * that doesn't support it... + */ + if (!r) { + LOG_ERROR("Invalid CPSR mode"); + r = arm->core_cache->reg_list + regnum; + } + + return r; +} + +static const uint8_t arm_gdb_dummy_fp_value[12]; + +/** + * Dummy FPA registers are required to support GDB on ARM. + * Register packets require eight obsolete FPA register values. + * Modern ARM cores use Vector Floating Point (VFP), if they + * have any floating point support. VFP is not FPA-compatible. + */ +struct reg arm_gdb_dummy_fp_reg = +{ + .name = "GDB dummy FPA register", + .value = (uint8_t *) arm_gdb_dummy_fp_value, + .valid = 1, + .size = 96, }; -u8 armv4_5_gdb_dummy_fps_value[] = {0, 0, 0, 0}; +static const uint8_t arm_gdb_dummy_fps_value[4]; -reg_t armv4_5_gdb_dummy_fps_reg = +/** + * Dummy FPA status registers are required to support GDB on ARM. + * Register packets require an obsolete FPA status register. + */ +struct reg arm_gdb_dummy_fps_reg = { - "GDB dummy floating-point status register", armv4_5_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0 + .name = "GDB dummy FPA status register", + .value = (uint8_t *) arm_gdb_dummy_fps_value, + .valid = 1, + .size = 32, }; -int armv4_5_get_core_reg(reg_t *reg) +static void arm_gdb_dummy_init(void) __attribute__ ((constructor)); + +static void arm_gdb_dummy_init(void) +{ + register_init_dummy(&arm_gdb_dummy_fp_reg); + register_init_dummy(&arm_gdb_dummy_fps_reg); +} + +static int armv4_5_get_core_reg(struct reg *reg) { int retval; - armv4_5_core_reg_t *armv4_5 = reg->arch_info; - target_t *target = armv4_5->target; + struct arm_reg *armv4_5 = reg->arch_info; + struct target *target = armv4_5->target; if (target->state != TARGET_HALTED) { @@ -179,317 +478,379 @@ int armv4_5_get_core_reg(reg_t *reg) return ERROR_TARGET_NOT_HALTED; } - /* retval = armv4_5->armv4_5_common->full_context(target); */ - retval = armv4_5->armv4_5_common->read_core_reg(target, armv4_5->num, armv4_5->mode); + retval = armv4_5->armv4_5_common->read_core_reg(target, reg, armv4_5->num, armv4_5->mode); + if (retval == ERROR_OK) { + reg->valid = 1; + reg->dirty = 0; + } return retval; } -int armv4_5_set_core_reg(reg_t *reg, u8 *buf) +static int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf) { - armv4_5_core_reg_t *armv4_5 = reg->arch_info; - target_t *target = armv4_5->target; - armv4_5_common_t *armv4_5_target = target->arch_info; - u32 value = buf_get_u32(buf, 0, 32); + struct arm_reg *armv4_5 = reg->arch_info; + struct target *target = armv4_5->target; + struct arm *armv4_5_target = target_to_armv4_5(target); + uint32_t value = buf_get_u32(buf, 0, 32); if (target->state != TARGET_HALTED) { + LOG_ERROR("Target not halted"); return ERROR_TARGET_NOT_HALTED; } - if (reg == &armv4_5_target->core_cache->reg_list[ARMV4_5_CPSR]) - { - if (value & 0x20) - { - /* T bit should be set */ - if (armv4_5_target->core_state == ARMV4_5_STATE_ARM) - { - /* change state to Thumb */ - LOG_DEBUG("changing to Thumb state"); - armv4_5_target->core_state = ARMV4_5_STATE_THUMB; - } - } - else - { - /* T bit should be cleared */ - if (armv4_5_target->core_state == ARMV4_5_STATE_THUMB) - { - /* change state to ARM */ - LOG_DEBUG("changing to ARM state"); - armv4_5_target->core_state = ARMV4_5_STATE_ARM; - } - } - - if (armv4_5_target->core_mode != (enum armv4_5_mode)(value & 0x1f)) - { - LOG_DEBUG("changing ARM core mode to '%s'", armv4_5_mode_strings[armv4_5_mode_to_number(value & 0x1f)]); - armv4_5_target->core_mode = value & 0x1f; - armv4_5_target->write_core_reg(target, 16, ARMV4_5_MODE_ANY, value); + /* Except for CPSR, the "reg" command exposes a writeback model + * for the register cache. + */ + if (reg == armv4_5_target->cpsr) { + arm_set_cpsr(armv4_5_target, value); + + /* Older cores need help to be in ARM mode during halt + * mode debug, so we clear the J and T bits if we flush. + * For newer cores (v6/v7a/v7r) we don't need that, but + * it won't hurt since CPSR is always flushed anyway. + */ + if (armv4_5_target->core_mode != + (enum armv4_5_mode)(value & 0x1f)) { + LOG_DEBUG("changing ARM core mode to '%s'", + arm_mode_name(value & 0x1f)); + value &= ~((1 << 24) | (1 << 5)); + armv4_5_target->write_core_reg(target, reg, + 16, ARMV4_5_MODE_ANY, value); } + } else { + buf_set_u32(reg->value, 0, 32, value); + reg->valid = 1; } - - buf_set_u32(reg->value, 0, 32, value); reg->dirty = 1; - reg->valid = 1; return ERROR_OK; } -int armv4_5_invalidate_core_regs(target_t *target) +static const struct reg_arch_type arm_reg_type = { + .get = armv4_5_get_core_reg, + .set = armv4_5_set_core_reg, +}; + +struct reg_cache* armv4_5_build_reg_cache(struct target *target, struct arm *armv4_5_common) { - armv4_5_common_t *armv4_5 = target->arch_info; + int num_regs = ARRAY_SIZE(arm_core_regs); + struct reg_cache *cache = malloc(sizeof(struct reg_cache)); + struct reg *reg_list = calloc(num_regs, sizeof(struct reg)); + struct arm_reg *arch_info = calloc(num_regs, sizeof(struct arm_reg)); int i; - for (i = 0; i < 37; i++) - { - armv4_5->core_cache->reg_list[i].valid = 0; - armv4_5->core_cache->reg_list[i].dirty = 0; + if (!cache || !reg_list || !arch_info) { + free(cache); + free(reg_list); + free(arch_info); + return NULL; } - return ERROR_OK; -} - -reg_cache_t* armv4_5_build_reg_cache(target_t *target, armv4_5_common_t *armv4_5_common) -{ - int num_regs = 37; - reg_cache_t *cache = malloc(sizeof(reg_cache_t)); - reg_t *reg_list = malloc(sizeof(reg_t) * num_regs); - armv4_5_core_reg_t *arch_info = malloc(sizeof(armv4_5_core_reg_t) * num_regs); - int i; - - cache->name = "arm v4/5 registers"; + cache->name = "ARM registers"; cache->next = NULL; cache->reg_list = reg_list; - cache->num_regs = num_regs; + cache->num_regs = 0; - if (armv4_5_core_reg_arch_type == -1) - armv4_5_core_reg_arch_type = register_reg_arch_type(armv4_5_get_core_reg, armv4_5_set_core_reg); + for (i = 0; i < num_regs; i++) + { + /* Skip registers this core doesn't expose */ + if (arm_core_regs[i].mode == ARM_MODE_MON + && armv4_5_common->core_type != ARM_MODE_MON) + continue; - register_init_dummy(&armv4_5_gdb_dummy_fp_reg); - register_init_dummy(&armv4_5_gdb_dummy_fps_reg); + /* REVISIT handle Cortex-M, which only shadows R13/SP */ - for (i = 0; i < 37; i++) - { - arch_info[i] = armv4_5_core_reg_list_arch_info[i]; + arch_info[i].num = arm_core_regs[i].cookie; + arch_info[i].mode = arm_core_regs[i].mode; arch_info[i].target = target; arch_info[i].armv4_5_common = armv4_5_common; - reg_list[i].name = armv4_5_core_reg_list[i]; + + reg_list[i].name = (char *) arm_core_regs[i].name; reg_list[i].size = 32; - reg_list[i].value = calloc(1, 4); - reg_list[i].dirty = 0; - reg_list[i].valid = 0; - reg_list[i].bitfield_desc = NULL; - reg_list[i].num_bitfields = 0; - reg_list[i].arch_type = armv4_5_core_reg_arch_type; + reg_list[i].value = &arch_info[i].value; + reg_list[i].type = &arm_reg_type; reg_list[i].arch_info = &arch_info[i]; + + cache->num_regs++; } + armv4_5_common->cpsr = reg_list + ARMV4_5_CPSR; + armv4_5_common->core_cache = cache; return cache; } -int armv4_5_arch_state(struct target_s *target) +int armv4_5_arch_state(struct target *target) { - armv4_5_common_t *armv4_5 = target->arch_info; + struct arm *armv4_5 = target_to_armv4_5(target); if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) { LOG_ERROR("BUG: called for a non-ARMv4/5 target"); - exit(-1); + return ERROR_FAIL; } - LOG_USER("target halted in %s state due to %s, current mode: %s\ncpsr: 0x%8.8x pc: 0x%8.8x", + LOG_USER("target halted in %s state due to %s, current mode: %s\ncpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "", armv4_5_state_strings[armv4_5->core_state], - Jim_Nvp_value2name_simple( nvp_target_debug_reason, target->debug_reason )->name, - armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)], - buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32), + Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name, + arm_mode_name(armv4_5->core_mode), + buf_get_u32(armv4_5->cpsr->value, 0, 32), buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); return ERROR_OK; } -int handle_armv4_5_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +#define ARMV4_5_CORE_REG_MODENUM(cache, mode, num) \ + cache->reg_list[armv4_5_core_reg_map[mode][num]] + +COMMAND_HANDLER(handle_armv4_5_reg_command) { - char output[128]; - int output_len; - int mode, num; - target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5 = target->arch_info; + struct target *target = get_current_target(CMD_CTX); + struct arm *armv4_5 = target_to_armv4_5(target); + unsigned num_regs; + struct reg *regs; - if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) + if (!is_arm(armv4_5)) { - command_print(cmd_ctx, "current target isn't an ARMV4/5 target"); - return ERROR_OK; + command_print(CMD_CTX, "current target isn't an ARM"); + return ERROR_FAIL; } if (target->state != TARGET_HALTED) { - command_print(cmd_ctx, "error: target must be halted for register accesses"); - return ERROR_OK; + command_print(CMD_CTX, "error: target must be halted for register accesses"); + return ERROR_FAIL; } - if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) + if (!is_arm_mode(armv4_5->core_mode)) return ERROR_FAIL; - for (num = 0; num <= 15; num++) - { - output_len = 0; - for (mode = 0; mode < 6; mode++) - { - if (!ARMV4_5_CORE_REG_MODENUM(armv4_5->core_cache, mode, num).valid) - { - armv4_5->full_context(target); + if (!armv4_5->full_context) { + command_print(CMD_CTX, "error: target doesn't support %s", + CMD_NAME); + return ERROR_FAIL; + } + + num_regs = armv4_5->core_cache->num_regs; + regs = armv4_5->core_cache->reg_list; + + for (unsigned mode = 0; mode < ARRAY_SIZE(arm_mode_data); mode++) { + const char *name; + char *sep = "\n"; + char *shadow = ""; + + /* label this bank of registers (or shadows) */ + switch (arm_mode_data[mode].psr) { + case ARMV4_5_MODE_SYS: + continue; + case ARMV4_5_MODE_USR: + name = "System and User"; + sep = ""; + break; + case ARM_MODE_MON: + if (armv4_5->core_type != ARM_MODE_MON) + continue; + /* FALLTHROUGH */ + default: + name = arm_mode_data[mode].name; + shadow = "shadow "; + break; + } + command_print(CMD_CTX, "%s%s mode %sregisters", + sep, name, shadow); + + /* display N rows of up to 4 registers each */ + for (unsigned i = 0; i < arm_mode_data[mode].n_indices;) { + char output[80]; + int output_len = 0; + + for (unsigned j = 0; j < 4; j++, i++) { + uint32_t value; + struct reg *reg = regs; + + if (i >= arm_mode_data[mode].n_indices) + break; + + reg += arm_mode_data[mode].indices[i]; + + /* REVISIT be smarter about faults... */ + if (!reg->valid) + armv4_5->full_context(target); + + value = buf_get_u32(reg->value, 0, 32); + output_len += snprintf(output + output_len, + sizeof(output) - output_len, + "%8s: %8.8" PRIx32 " ", + reg->name, value); } - output_len += snprintf(output + output_len, 128 - output_len, "%8s: %8.8x ", ARMV4_5_CORE_REG_MODENUM(armv4_5->core_cache, mode, num).name, - buf_get_u32(ARMV4_5_CORE_REG_MODENUM(armv4_5->core_cache, mode, num).value, 0, 32)); + command_print(CMD_CTX, "%s", output); } - command_print(cmd_ctx, "%s", output); } - command_print(cmd_ctx, " cpsr: %8.8x spsr_fiq: %8.8x spsr_irq: %8.8x spsr_svc: %8.8x spsr_abt: %8.8x spsr_und: %8.8x", - buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32), - buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_SPSR_FIQ].value, 0, 32), - buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_SPSR_IRQ].value, 0, 32), - buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_SPSR_SVC].value, 0, 32), - buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_SPSR_ABT].value, 0, 32), - buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_SPSR_UND].value, 0, 32)); return ERROR_OK; } -int handle_armv4_5_core_state_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +COMMAND_HANDLER(handle_armv4_5_core_state_command) { - target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5 = target->arch_info; + struct target *target = get_current_target(CMD_CTX); + struct arm *armv4_5 = target_to_armv4_5(target); - if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) + if (!is_arm(armv4_5)) { - command_print(cmd_ctx, "current target isn't an ARMV4/5 target"); - return ERROR_OK; + command_print(CMD_CTX, "current target isn't an ARM"); + return ERROR_FAIL; } - if (argc > 0) + if (CMD_ARGC > 0) { - if (strcmp(args[0], "arm") == 0) + if (strcmp(CMD_ARGV[0], "arm") == 0) { armv4_5->core_state = ARMV4_5_STATE_ARM; } - if (strcmp(args[0], "thumb") == 0) + if (strcmp(CMD_ARGV[0], "thumb") == 0) { armv4_5->core_state = ARMV4_5_STATE_THUMB; } } - command_print(cmd_ctx, "core state: %s", armv4_5_state_strings[armv4_5->core_state]); + command_print(CMD_CTX, "core state: %s", armv4_5_state_strings[armv4_5->core_state]); return ERROR_OK; } -int handle_armv4_5_disassemble_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +COMMAND_HANDLER(handle_armv4_5_disassemble_command) { int retval = ERROR_OK; - target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5 = target->arch_info; - u32 address; - int count; - int i; - arm_instruction_t cur_instruction; - u32 opcode; - u16 thumb_opcode; + struct target *target = get_current_target(CMD_CTX); + struct arm *arm = target ? target_to_arm(target) : NULL; + uint32_t address; + int count = 1; int thumb = 0; - if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) - { - command_print(cmd_ctx, "current target isn't an ARMV4/5 target"); - return ERROR_OK; - } - - if (argc < 2) - { - command_print(cmd_ctx, "usage: armv4_5 disassemble