X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farmv4_5.c;h=4a7fd7a4ba2e9db60bdc0b1a42427e4e69153004;hp=32daa792203529e8c090afecab51b2d9ac2aae56;hb=40580e2d71ac56131a5da7e5f67a0b63450e4f24;hpb=0cba0d4df3fe120f08945703506f8405760325c9

diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 32daa79220..4a7fd7a4ba 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -231,7 +231,7 @@ int armv4_5_set_core_reg(reg_t *reg, u8 *buf)
 			}
 		}
 
-		if (armv4_5_target->core_mode != (value & 0x1f))
+		if (armv4_5_target->core_mode != (enum armv4_5_mode)(value & 0x1f))
 		{
 			LOG_DEBUG("changing ARM core mode to '%s'", armv4_5_mode_strings[armv4_5_mode_to_number(value & 0x1f)]);
 			armv4_5_target->core_mode = value & 0x1f;
@@ -404,6 +404,7 @@ int handle_armv4_5_disassemble_command(struct command_context_s *cmd_ctx, char *
 	int i;
 	arm_instruction_t cur_instruction;
 	u32 opcode;
+	u16 thumb_opcode;
 	int thumb = 0;
 
 	if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
@@ -427,13 +428,26 @@ int handle_armv4_5_disassemble_command(struct command_context_s *cmd_ctx, char *
 
 	for (i = 0; i < count; i++)
 	{
-		if((retval = target_read_u32(target, address, &opcode)) != ERROR_OK)
+		if(thumb)
 		{
-			return retval;
+			if((retval = target_read_u16(target, address, &thumb_opcode)) != ERROR_OK)
+			{
+				return retval;
+			}
+			if((retval = thumb_evaluate_opcode(thumb_opcode, address, &cur_instruction)) != ERROR_OK)
+			{
+				return retval;
+			}
 		}
-		if((retval = arm_evaluate_opcode(opcode, address, &cur_instruction)) != ERROR_OK)
-		{
-			return retval;
+		else {
+			if((retval = target_read_u32(target, address, &opcode)) != ERROR_OK)
+			{
+				return retval;
+			}
+			if((retval = arm_evaluate_opcode(opcode, address, &cur_instruction)) != ERROR_OK)
+			{
+				return retval;
+			}
 		}
 		command_print(cmd_ctx, "%s", cur_instruction.text);
 		address += (thumb) ? 2 : 4;
@@ -647,10 +661,15 @@ int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem
 
 	for (i = 0; i <= 16; i++)
 	{
-		LOG_DEBUG("restoring register %s with value 0x%8.8x", ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).name, context[i]);
-		buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32, context[i]);
-		ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).valid = 1;
-		ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).dirty = 1;
+		u32 regvalue;
+		regvalue = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32);
+		if (regvalue != context[i])
+		{
+			LOG_DEBUG("restoring register %s with value 0x%8.8x", ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).name, context[i]);
+			buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32, context[i]);
+			ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).valid = 1;
+			ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).dirty = 1;
+		}
 	}
 	buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, cpsr);
 	armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;