X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farmv4_5.c;h=3eab03354bc6ceb3386f5a74d4aad0ef9fe1a27f;hp=4932e20ae5b570d098658300889b9734fa220034;hb=e9297b40b994f071474210e7d9e224d50e25fcaf;hpb=b9628accd6da0aef6a9fc03efb96e05afab99c99

diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 4932e20ae5..3eab03354b 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -17,7 +17,11 @@
  *   Free Software Foundation, Inc.,                                       *
  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  ***************************************************************************/
+#ifdef HAVE_CONFIG_H
 #include "config.h"
+#endif
+
+#include "replacements.h"
 
 #include "arm_disassembler.h"
 
@@ -219,16 +223,42 @@ int armv4_5_get_core_reg(reg_t *reg)
 	return retval;
 }
 
-int armv4_5_set_core_reg(reg_t *reg, u32 value)
+int armv4_5_set_core_reg(reg_t *reg, u8 *buf)
 {
 	armv4_5_core_reg_t *armv4_5 = reg->arch_info;
 	target_t *target = armv4_5->target;
+	armv4_5_common_t *armv4_5_target = target->arch_info;
+	u32 value = buf_get_u32(buf, 0, 32);
 		
 	if (target->state != TARGET_HALTED)
 	{
 		return ERROR_TARGET_NOT_HALTED;
 	}
 	
+	if (reg == &armv4_5_target->core_cache->reg_list[ARMV4_5_CPSR])
+	{
+		if (value & 0x20)
+		{
+			/* T bit should be set */
+			if (armv4_5_target->core_state == ARMV4_5_STATE_ARM)
+			{
+				/* change state to Thumb */
+				DEBUG("changing to Thumb state");
+				armv4_5_target->core_state = ARMV4_5_STATE_THUMB;	
+			}
+		}
+		else
+		{
+			/* T bit should be cleared */
+			if (armv4_5_target->core_state == ARMV4_5_STATE_THUMB)
+			{
+				/* change state to ARM */
+				DEBUG("changing to ARM state");
+				armv4_5_target->core_state = ARMV4_5_STATE_ARM;	
+			}
+		}
+	}
+	
 	buf_set_u32(reg->value, 0, 32, value);
 	reg->dirty = 1;
 	reg->valid = 1;
@@ -255,7 +285,7 @@ reg_cache_t* armv4_5_build_reg_cache(target_t *target, armv4_5_common_t *armv4_5
 	int num_regs = 37;
 	reg_cache_t *cache = malloc(sizeof(reg_cache_t));
 	reg_t *reg_list = malloc(sizeof(reg_t) * num_regs);
-	armv4_5_core_reg_t *arch_info = malloc(sizeof(reg_t) * num_regs);
+	armv4_5_core_reg_t *arch_info = malloc(sizeof(armv4_5_core_reg_t) * num_regs);
 	int i;
 	
 	cache->name = "arm v4/5 registers";
@@ -388,7 +418,7 @@ int handle_armv4_5_disassemble_command(struct command_context_s *cmd_ctx, char *
 	int i;
 	arm_instruction_t cur_instruction;
 	u32 opcode;
-	int thumb;
+	int thumb = 0;
 	
 	if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
 	{
@@ -411,7 +441,7 @@ int handle_armv4_5_disassemble_command(struct command_context_s *cmd_ctx, char *
 	
 	for (i = 0; i < count; i++)
 	{
-		target->type->read_memory(target, address, 4, 1, (u8*)&opcode);
+		target_read_u32(target, address, &opcode);
 		evaluate_opcode(opcode, address, &cur_instruction);
 		command_print(cmd_ctx, "%s", cur_instruction.text);
 		address += (thumb) ? 2 : 4;
@@ -424,7 +454,7 @@ int armv4_5_register_commands(struct command_context_s *cmd_ctx)
 {
 	command_t *armv4_5_cmd;
 
-	armv4_5_cmd = register_command(cmd_ctx, NULL, "armv4_5", NULL, COMMAND_ANY, NULL);
+	armv4_5_cmd = register_command(cmd_ctx, NULL, "armv4_5", NULL, COMMAND_ANY, "armv4/5 specific commands");
 	
 	register_command(cmd_ctx, armv4_5_cmd, "reg", handle_armv4_5_reg_command, COMMAND_EXEC, "display ARM core registers");
 	register_command(cmd_ctx, armv4_5_cmd, "core_state", handle_armv4_5_core_state_command, COMMAND_EXEC, "display/change ARM core state <arm|thumb>");
@@ -514,7 +544,7 @@ int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, mem_param
 			exit(-1);
 		}
 		
-		armv4_5_set_core_reg(reg, buf_get_u32(reg_params[i].value, 0, 32));
+		armv4_5_set_core_reg(reg, reg_params[i].value);
 	}
 	
 	armv4_5->core_state = armv4_5_algorithm_info->core_state;
@@ -600,7 +630,7 @@ int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, mem_param
 	
 	for (i = 0; i <= 16; i++)
 	{
-		DEBUG("restoring register %s with value 0x%8.8x", ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).name, buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32));
+		DEBUG("restoring register %s with value 0x%8.8x", ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).name, context[i]);
 		buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32, context[i]);
 		ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).valid = 1;
 		ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).dirty = 1;