X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farmv4_5.c;h=3156c666f67a85b321dec9edc1cbc6f31567f42a;hp=44e5b0ace125404a0609beaf9d3e0da17b83805c;hb=ff810723e051ed1f86cffcb565ade6b4d1fc50c8;hpb=8f446fcf676e9cd13cf53d9946f0cae5d29a10ec diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c index 44e5b0ace1..3156c666f6 100644 --- a/src/target/armv4_5.c +++ b/src/target/armv4_5.c @@ -36,6 +36,17 @@ #include "register.h" +/* offsets into armv4_5 core register cache */ +enum { +// ARMV4_5_CPSR = 31, + ARMV4_5_SPSR_FIQ = 32, + ARMV4_5_SPSR_IRQ = 33, + ARMV4_5_SPSR_SVC = 34, + ARMV4_5_SPSR_ABT = 35, + ARMV4_5_SPSR_UND = 36, + ARM_SPSR_MON = 39, +}; + static const uint8_t arm_usr_indices[17] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, ARMV4_5_CPSR, }; @@ -214,7 +225,7 @@ char* armv4_5_state_strings[] = * * NOTE: offsets in this table are coupled to the arm_mode_data * table above, the armv4_5_core_reg_map array below, and also to - * the ARMV4_5_*PSR* symols. + * the ARMV4_5_CPSR symbol (which should vanish after ARM11 updates). */ static const struct { /* The name is used for e.g. the "regs" command. */ @@ -234,6 +245,10 @@ static const struct { unsigned cookie; enum armv4_5_mode mode; } arm_core_regs[] = { + /* IMPORTANT: we guarantee that the first eight cached registers + * correspond to r0..r7, and the fifteenth to PC, so that callers + * don't need to map them. + */ { .name = "r0", .cookie = 0, .mode = ARMV4_5_MODE_ANY, }, { .name = "r1", .cookie = 1, .mode = ARMV4_5_MODE_ANY, }, { .name = "r2", .cookie = 2, .mode = ARMV4_5_MODE_ANY, }, @@ -244,7 +259,8 @@ static const struct { { .name = "r7", .cookie = 7, .mode = ARMV4_5_MODE_ANY, }, /* NOTE: regs 8..12 might be shadowed by FIQ ... flagging - * them as MODE_ANY creates special cases. + * them as MODE_ANY creates special cases. (ANY means + * "not mapped" elsewhere; here it's "everything but FIQ".) */ { .name = "r8", .cookie = 8, .mode = ARMV4_5_MODE_ANY, }, { .name = "r9", .cookie = 9, .mode = ARMV4_5_MODE_ANY, }, @@ -256,6 +272,7 @@ static const struct { { .name = "sp_usr", .cookie = 13, .mode = ARMV4_5_MODE_USR, }, { .name = "lr_usr", .cookie = 14, .mode = ARMV4_5_MODE_USR, }, + /* guaranteed to be at index 15 */ { .name = "pc", .cookie = 15, .mode = ARMV4_5_MODE_ANY, }, { .name = "r8_fiq", .cookie = 8, .mode = ARMV4_5_MODE_FIQ, }, @@ -322,6 +339,73 @@ const int armv4_5_core_reg_map[8][17] = } }; +/** + * Configures host-side ARM records to reflect the specified CPSR. + * Later, code can use arm_reg_current() to map register numbers + * according to how they are exposed by this mode. + */ +void arm_set_cpsr(struct arm *arm, uint32_t cpsr) +{ + enum armv4_5_mode mode = cpsr & 0x1f; + int num; + + /* NOTE: this may be called very early, before the register + * cache is set up. We can't defend against many errors, in + * particular against CPSRs that aren't valid *here* ... + */ + if (arm->cpsr) { + buf_set_u32(arm->cpsr->value, 0, 32, cpsr); + arm->cpsr->valid = 1; + arm->cpsr->dirty = 0; + } + + arm->core_mode = mode; + + /* mode_to_number() warned; set up a somewhat-sane mapping */ + num = armv4_5_mode_to_number(mode); + if (num < 0) { + mode = ARMV4_5_MODE_USR; + num = 0; + } + + arm->map = &armv4_5_core_reg_map[num][0]; + arm->spsr = (mode == ARMV4_5_MODE_USR || mode == ARMV4_5_MODE_SYS) + ? NULL + : arm->core_cache->reg_list + arm->map[16]; +} + +/** + * Returns handle to the register currently mapped to a given number. + * Someone must have called arm_set_cpsr() before. + * + * \param arm This core's state and registers are used. + * \param regnum From 0..15 corresponding to R0..R14 and PC. + * Note that R0..R7 don't require mapping; you may access those + * as the first eight entries in the register cache. Likewise + * R15 (PC) doesn't need mapping; you may also access it directly. + * However, R8..R14, and SPSR (arm->spsr) *must* be mapped. + * CPSR (arm->cpsr) is also not mapped. + */ +struct reg *arm_reg_current(struct arm *arm, unsigned regnum) +{ + struct reg *r; + + if (regnum > 16) + return NULL; + + r = arm->core_cache->reg_list + arm->map[regnum]; + + /* e.g. invalid CPSR said "secure monitor" mode on a core + * that doesn't support it... + */ + if (!r) { + LOG_ERROR("Invalid CPSR mode"); + r = arm->core_cache->reg_list + regnum; + } + + return r; +} + static const uint8_t arm_gdb_dummy_fp_value[12]; /** @@ -363,7 +447,7 @@ static void arm_gdb_dummy_init(void) static int armv4_5_get_core_reg(struct reg *reg) { int retval; - struct armv4_5_core_reg *armv4_5 = reg->arch_info; + struct arm_reg *armv4_5 = reg->arch_info; struct target *target = armv4_5->target; if (target->state != TARGET_HALTED) @@ -372,16 +456,18 @@ static int armv4_5_get_core_reg(struct reg *reg) return ERROR_TARGET_NOT_HALTED; } - retval = armv4_5->armv4_5_common->read_core_reg(target, armv4_5->num, armv4_5->mode); - if (retval == ERROR_OK) + retval = armv4_5->armv4_5_common->read_core_reg(target, reg, armv4_5->num, armv4_5->mode); + if (retval == ERROR_OK) { reg->valid = 1; + reg->dirty = 0; + } return retval; } static int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf) { - struct armv4_5_core_reg *armv4_5 = reg->arch_info; + struct arm_reg *armv4_5 = reg->arch_info; struct target *target = armv4_5->target; struct armv4_5_common_s *armv4_5_target = target_to_armv4_5(target); uint32_t value = buf_get_u32(buf, 0, 32); @@ -392,8 +478,16 @@ static int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf) return ERROR_TARGET_NOT_HALTED; } - if (reg == &armv4_5_target->core_cache->reg_list[ARMV4_5_CPSR]) + /* Except for CPSR, the "reg" command exposes a writeback model + * for the register cache. + */ + buf_set_u32(reg->value, 0, 32, value); + reg->dirty = 1; + reg->valid = 1; + + if (reg == armv4_5_target->cpsr) { + /* FIXME handle J bit too; mostly for ThumbEE, also Jazelle */ if (value & 0x20) { /* T bit should be set */ @@ -415,19 +509,22 @@ static int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf) } } + /* REVISIT Why only update core for mode change, not also + * for state changes? Possibly older cores need to stay + * in ARM mode during halt mode debug, not execute Thumb; + * v6/v7a/v7r seem to do that automatically... + */ + if (armv4_5_target->core_mode != (enum armv4_5_mode)(value & 0x1f)) { LOG_DEBUG("changing ARM core mode to '%s'", arm_mode_name(value & 0x1f)); - armv4_5_target->core_mode = value & 0x1f; - armv4_5_target->write_core_reg(target, 16, ARMV4_5_MODE_ANY, value); + armv4_5_target->write_core_reg(target, reg, + 16, ARMV4_5_MODE_ANY, value); + arm_set_cpsr(armv4_5_target, value); } } - buf_set_u32(reg->value, 0, 32, value); - reg->dirty = 1; - reg->valid = 1; - return ERROR_OK; } @@ -436,29 +533,12 @@ static const struct reg_arch_type arm_reg_type = { .set = armv4_5_set_core_reg, }; -/** Marks the contents of the register cache as invalid (and clean). */ -int armv4_5_invalidate_core_regs(struct target *target) -{ - struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); - unsigned num_regs = armv4_5->core_cache->num_regs; - struct reg *reg = armv4_5->core_cache->reg_list; - - for (unsigned i = 0; i < num_regs; i++, reg++) { - reg->valid = 0; - reg->dirty = 0; - } - - /* FIXME don't bother returning a value then */ - return ERROR_OK; -} - struct reg_cache* armv4_5_build_reg_cache(struct target *target, struct arm *armv4_5_common) { int num_regs = ARRAY_SIZE(arm_core_regs); struct reg_cache *cache = malloc(sizeof(struct reg_cache)); struct reg *reg_list = calloc(num_regs, sizeof(struct reg)); - struct armv4_5_core_reg *arch_info = calloc(num_regs, - sizeof(struct armv4_5_core_reg)); + struct arm_reg *arch_info = calloc(num_regs, sizeof(struct arm_reg)); int i; if (!cache || !reg_list || !arch_info) { @@ -496,6 +576,8 @@ struct reg_cache* armv4_5_build_reg_cache(struct target *target, struct arm *arm cache->num_regs++; } + armv4_5_common->cpsr = reg_list + ARMV4_5_CPSR; + armv4_5_common->core_cache = cache; return cache; } @@ -513,7 +595,7 @@ int armv4_5_arch_state(struct target *target) armv4_5_state_strings[armv4_5->core_state], Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name, arm_mode_name(armv4_5->core_mode), - buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32), + buf_get_u32(armv4_5->cpsr->value, 0, 32), buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); return ERROR_OK; @@ -742,17 +824,13 @@ int armv4_5_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list = malloc(sizeof(struct reg*) * (*reg_list_size)); for (i = 0; i < 16; i++) - { - (*reg_list)[i] = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i); - } + (*reg_list)[i] = arm_reg_current(armv4_5, i); for (i = 16; i < 24; i++) - { (*reg_list)[i] = &arm_gdb_dummy_fp_reg; - } (*reg_list)[24] = &arm_gdb_dummy_fps_reg; - (*reg_list)[25] = &armv4_5->core_cache->reg_list[ARMV4_5_CPSR]; + (*reg_list)[25] = armv4_5->cpsr; return ERROR_OK; } @@ -795,7 +873,6 @@ int armv4_5_run_algorithm_inner(struct target *target, int num_mem_params, struc struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); struct armv4_5_algorithm *armv4_5_algorithm_info = arch_info; enum armv4_5_state core_state = armv4_5->core_state; - enum armv4_5_mode core_mode = armv4_5->core_mode; uint32_t context[17]; uint32_t cpsr; int exit_breakpoint_size = 0; @@ -825,13 +902,21 @@ int armv4_5_run_algorithm_inner(struct target *target, int num_mem_params, struc return ERROR_FAIL; } + /* save r0..pc, cpsr-or-spsr, and then cpsr-for-sure; + * they'll be restored later. + */ for (i = 0; i <= 16; i++) { - if (!ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).valid) - armv4_5->read_core_reg(target, i, armv4_5_algorithm_info->core_mode); - context[i] = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32); + struct reg *r; + + r = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, + armv4_5_algorithm_info->core_mode, i); + if (!r->valid) + armv4_5->read_core_reg(target, r, i, + armv4_5_algorithm_info->core_mode); + context[i] = buf_get_u32(r->value, 0, 32); } - cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32); + cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32); for (i = 0; i < num_mem_params; i++) { @@ -875,10 +960,12 @@ int armv4_5_run_algorithm_inner(struct target *target, int num_mem_params, struc if (armv4_5_algorithm_info->core_mode != ARMV4_5_MODE_ANY) { - LOG_DEBUG("setting core_mode: 0x%2.2x", armv4_5_algorithm_info->core_mode); - buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 5, armv4_5_algorithm_info->core_mode); - armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1; - armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1; + LOG_DEBUG("setting core_mode: 0x%2.2x", + armv4_5_algorithm_info->core_mode); + buf_set_u32(armv4_5->cpsr->value, 0, 5, + armv4_5_algorithm_info->core_mode); + armv4_5->cpsr->dirty = 1; + armv4_5->cpsr->valid = 1; } /* terminate using a hardware or (ARMv5+) software breakpoint */ @@ -935,6 +1022,7 @@ int armv4_5_run_algorithm_inner(struct target *target, int num_mem_params, struc } } + /* restore everything we saved before (17 or 18 registers) */ for (i = 0; i <= 16; i++) { uint32_t regvalue; @@ -947,12 +1035,11 @@ int armv4_5_run_algorithm_inner(struct target *target, int num_mem_params, struc ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).dirty = 1; } } - buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, cpsr); - armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1; - armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1; + + arm_set_cpsr(armv4_5, cpsr); + armv4_5->cpsr->dirty = 1; armv4_5->core_state = core_state; - armv4_5->core_mode = core_mode; return retval; } @@ -1152,8 +1239,8 @@ int armv4_5_init_arch_info(struct target *target, struct arm *armv4_5) target->arch_info = armv4_5; armv4_5->common_magic = ARMV4_5_COMMON_MAGIC; + arm_set_cpsr(armv4_5, ARMV4_5_MODE_USR); armv4_5->core_state = ARMV4_5_STATE_ARM; - armv4_5->core_mode = ARMV4_5_MODE_USR; /* core_type may be overridden by subtype logic */ armv4_5->core_type = ARMV4_5_MODE_ANY;