X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farmv4_5.c;h=11b6be60c051936ea047f16315d6a13a6e927248;hp=949ced410518069d0eadc247b78abeb4a1c31894;hb=374127301ec1d72033b9d573b72c7abdfd61990d;hpb=de0130a0aad83c1ef692ee4d68ab996a8668424d

diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 949ced4105..11b6be60c0 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -23,6 +23,7 @@
  *   Free Software Foundation, Inc.,                                       *
  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  ***************************************************************************/
+
 #ifdef HAVE_CONFIG_H
 #include "config.h"
 #endif
@@ -36,10 +37,9 @@
 #include "algorithm.h"
 #include "register.h"
 
-
 /* offsets into armv4_5 core register cache */
 enum {
-//	ARMV4_5_CPSR = 31,
+/*	ARMV4_5_CPSR = 31, */
 	ARMV4_5_SPSR_FIQ = 32,
 	ARMV4_5_SPSR_IRQ = 33,
 	ARMV4_5_SPSR_SVC = 34,
@@ -167,27 +167,27 @@ bool is_arm_mode(unsigned psr_mode)
 int arm_mode_to_number(enum arm_mode mode)
 {
 	switch (mode) {
-	case ARM_MODE_ANY:
+		case ARM_MODE_ANY:
 		/* map MODE_ANY to user mode */
-	case ARM_MODE_USR:
-		return 0;
-	case ARM_MODE_FIQ:
-		return 1;
-	case ARM_MODE_IRQ:
-		return 2;
-	case ARM_MODE_SVC:
-		return 3;
-	case ARM_MODE_ABT:
-		return 4;
-	case ARM_MODE_UND:
-		return 5;
-	case ARM_MODE_SYS:
-		return 6;
-	case ARM_MODE_MON:
-		return 7;
-	default:
-		LOG_ERROR("invalid mode value encountered %d", mode);
-		return -1;
+		case ARM_MODE_USR:
+			return 0;
+		case ARM_MODE_FIQ:
+			return 1;
+		case ARM_MODE_IRQ:
+			return 2;
+		case ARM_MODE_SVC:
+			return 3;
+		case ARM_MODE_ABT:
+			return 4;
+		case ARM_MODE_UND:
+			return 5;
+		case ARM_MODE_SYS:
+			return 6;
+		case ARM_MODE_MON:
+			return 7;
+		default:
+			LOG_ERROR("invalid mode value encountered %d", mode);
+			return -1;
 	}
 }
 
@@ -195,30 +195,29 @@ int arm_mode_to_number(enum arm_mode mode)
 enum arm_mode armv4_5_number_to_mode(int number)
 {
 	switch (number) {
-	case 0:
-		return ARM_MODE_USR;
-	case 1:
-		return ARM_MODE_FIQ;
-	case 2:
-		return ARM_MODE_IRQ;
-	case 3:
-		return ARM_MODE_SVC;
-	case 4:
-		return ARM_MODE_ABT;
-	case 5:
-		return ARM_MODE_UND;
-	case 6:
-		return ARM_MODE_SYS;
-	case 7:
-		return ARM_MODE_MON;
-	default:
-		LOG_ERROR("mode index out of bounds %d", number);
-		return ARM_MODE_ANY;
+		case 0:
+			return ARM_MODE_USR;
+		case 1:
+			return ARM_MODE_FIQ;
+		case 2:
+			return ARM_MODE_IRQ;
+		case 3:
+			return ARM_MODE_SVC;
+		case 4:
+			return ARM_MODE_ABT;
+		case 5:
+			return ARM_MODE_UND;
+		case 6:
+			return ARM_MODE_SYS;
+		case 7:
+			return ARM_MODE_MON;
+		default:
+			LOG_ERROR("mode index out of bounds %d", number);
+			return ARM_MODE_ANY;
 	}
 }
 
-static const char *arm_state_strings[] =
-{
+static const char *arm_state_strings[] = {
 	"ARM", "Thumb", "Jazelle", "ThumbEE",
 };
 
@@ -312,8 +311,7 @@ static const struct {
 /* map core mode (USR, FIQ, ...) and register number to
  * indices into the register cache
  */
-const int armv4_5_core_reg_map[8][17] =
-{
+const int armv4_5_core_reg_map[8][17] = {
 	{	/* USR */
 		0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
 	},
@@ -371,8 +369,8 @@ void arm_set_cpsr(struct arm *arm, uint32_t cpsr)
 
 	arm->map = &armv4_5_core_reg_map[num][0];
 	arm->spsr = (mode == ARM_MODE_USR || mode == ARM_MODE_SYS)
-			? NULL
-			: arm->core_cache->reg_list + arm->map[16];
+		? NULL
+		: arm->core_cache->reg_list + arm->map[16];
 
 	/* Older ARMs won't have the J bit */
 	enum arm_state state;
@@ -393,8 +391,8 @@ void arm_set_cpsr(struct arm *arm, uint32_t cpsr)
 	arm->core_state = state;
 
 	LOG_DEBUG("set CPSR %#8.8x: %s mode, %s state", (unsigned) cpsr,
-			arm_mode_name(mode),
-			arm_state_strings[arm->core_state]);
+		arm_mode_name(mode),
+		arm_state_strings[arm->core_state]);
 }
 
 /**
@@ -437,8 +435,7 @@ static const uint8_t arm_gdb_dummy_fp_value[12];
  * Modern ARM cores use Vector Floating Point (VFP), if they
  * have any floating point support.  VFP is not FPA-compatible.
  */
-struct reg arm_gdb_dummy_fp_reg =
-{
+struct reg arm_gdb_dummy_fp_reg = {
 	.name = "GDB dummy FPA register",
 	.value = (uint8_t *) arm_gdb_dummy_fp_value,
 	.valid = 1,
@@ -451,8 +448,7 @@ static const uint8_t arm_gdb_dummy_fps_value[4];
  * Dummy FPA status registers are required to support GDB on ARM.
  * Register packets require an obsolete FPA status register.
  */
-struct reg arm_gdb_dummy_fps_reg =
-{
+struct reg arm_gdb_dummy_fps_reg = {
 	.name = "GDB dummy FPA status register",
 	.value = (uint8_t *) arm_gdb_dummy_fps_value,
 	.valid = 1,
@@ -473,8 +469,7 @@ static int armv4_5_get_core_reg(struct reg *reg)
 	struct arm_reg *reg_arch_info = reg->arch_info;
 	struct target *target = reg_arch_info->target;
 
-	if (target->state != TARGET_HALTED)
-	{
+	if (target->state != TARGET_HALTED) {
 		LOG_ERROR("Target not halted");
 		return ERROR_TARGET_NOT_HALTED;
 	}
@@ -496,8 +491,7 @@ static int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf)
 	struct arm *armv4_5_target = target_to_arm(target);
 	uint32_t value = buf_get_u32(buf, 0, 32);
 
-	if (target->state != TARGET_HALTED)
-	{
+	if (target->state != TARGET_HALTED) {
 		LOG_ERROR("Target not halted");
 		return ERROR_TARGET_NOT_HALTED;
 	}
@@ -514,12 +508,12 @@ static int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf)
 		 * it won't hurt since CPSR is always flushed anyway.
 		 */
 		if (armv4_5_target->core_mode !=
-				(enum arm_mode)(value & 0x1f)) {
+			(enum arm_mode)(value & 0x1f)) {
 			LOG_DEBUG("changing ARM core mode to '%s'",
-					arm_mode_name(value & 0x1f));
+				arm_mode_name(value & 0x1f));
 			value &= ~((1 << 24) | (1 << 5));
 			armv4_5_target->write_core_reg(target, reg,
-					16, ARM_MODE_ANY, value);
+				16, ARM_MODE_ANY, value);
 		}
 	} else {
 		buf_set_u32(reg->value, 0, 32, value);
@@ -555,11 +549,10 @@ struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm)
 	cache->reg_list = reg_list;
 	cache->num_regs = 0;
 
-	for (i = 0; i < num_regs; i++)
-	{
+	for (i = 0; i < num_regs; i++) {
 		/* Skip registers this core doesn't expose */
 		if (arm_core_regs[i].mode == ARM_MODE_MON
-				&& arm->core_type != ARM_MODE_MON)
+			&& arm->core_type != ARM_MODE_MON)
 			continue;
 
 		/* REVISIT handle Cortex-M, which only shadows R13/SP */
@@ -588,26 +581,25 @@ int arm_arch_state(struct target *target)
 {
 	struct arm *arm = target_to_arm(target);
 
-	if (arm->common_magic != ARM_COMMON_MAGIC)
-	{
+	if (arm->common_magic != ARM_COMMON_MAGIC) {
 		LOG_ERROR("BUG: called for a non-ARM target");
 		return ERROR_FAIL;
 	}
 
 	LOG_USER("target halted in %s state due to %s, current mode: %s\n"
-			"cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "%s",
-			arm_state_strings[arm->core_state],
-			debug_reason_name(target),
-			arm_mode_name(arm->core_mode),
-			buf_get_u32(arm->cpsr->value, 0, 32),
-			buf_get_u32(arm->pc->value, 0, 32),
-			arm->is_semihosting ? ", semihosting" : "");
+		"cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "%s",
+		arm_state_strings[arm->core_state],
+		debug_reason_name(target),
+		arm_mode_name(arm->core_mode),
+		buf_get_u32(arm->cpsr->value, 0, 32),
+		buf_get_u32(arm->pc->value, 0, 32),
+		arm->is_semihosting ? ", semihosting" : "");
 
 	return ERROR_OK;
 }
 
 #define ARMV4_5_CORE_REG_MODENUM(cache, mode, num) \
-		cache->reg_list[armv4_5_core_reg_map[mode][num]]
+	(cache->reg_list[armv4_5_core_reg_map[mode][num]])
 
 COMMAND_HANDLER(handle_armv4_5_reg_command)
 {
@@ -615,33 +607,30 @@ COMMAND_HANDLER(handle_armv4_5_reg_command)
 	struct arm *arm = target_to_arm(target);
 	struct reg *regs;
 
-	if (!is_arm(arm))
-	{
+	if (!is_arm(arm)) {
 		command_print(CMD_CTX, "current target isn't an ARM");
 		return ERROR_FAIL;
 	}
 
-	if (target->state != TARGET_HALTED)
-	{
+	if (target->state != TARGET_HALTED) {
 		command_print(CMD_CTX, "error: target must be halted for register accesses");
 		return ERROR_FAIL;
 	}
 
-	if (arm->core_type != ARM_MODE_ANY)
-	{
-		command_print(CMD_CTX, "Microcontroller Profile not supported - use standard reg cmd");
+	if (arm->core_type != ARM_MODE_ANY) {
+		command_print(CMD_CTX,
+			"Microcontroller Profile not supported - use standard reg cmd");
 		return ERROR_OK;
 	}
 
-	if (!is_arm_mode(arm->core_mode))
-	{
+	if (!is_arm_mode(arm->core_mode)) {
 		LOG_ERROR("not a valid arm core mode - communication failure?");
 		return ERROR_FAIL;
 	}
 
 	if (!arm->full_context) {
 		command_print(CMD_CTX, "error: target doesn't support %s",
-				CMD_NAME);
+			CMD_NAME);
 		return ERROR_FAIL;
 	}
 
@@ -654,26 +643,26 @@ COMMAND_HANDLER(handle_armv4_5_reg_command)
 
 		/* label this bank of registers (or shadows) */
 		switch (arm_mode_data[mode].psr) {
-		case ARM_MODE_SYS:
-			continue;
-		case ARM_MODE_USR:
-			name = "System and User";
-			sep = "";
-			break;
-		case ARM_MODE_MON:
-			if (arm->core_type != ARM_MODE_MON)
+			case ARM_MODE_SYS:
 				continue;
+			case ARM_MODE_USR:
+				name = "System and User";
+				sep = "";
+				break;
+			case ARM_MODE_MON:
+				if (arm->core_type != ARM_MODE_MON)
+					continue;
 			/* FALLTHROUGH */
-		default:
-			name = arm_mode_data[mode].name;
-			shadow = "shadow ";
-			break;
+			default:
+				name = arm_mode_data[mode].name;
+				shadow = "shadow ";
+				break;
 		}
 		command_print(CMD_CTX, "%s%s mode %sregisters",
-				sep, name, shadow);
+			sep, name, shadow);
 
 		/* display N rows of up to 4 registers each */
-		for (unsigned i = 0; i < arm_mode_data[mode].n_indices;) {
+		for (unsigned i = 0; i < arm_mode_data[mode].n_indices; ) {
 			char output[80];
 			int output_len = 0;
 
@@ -693,8 +682,8 @@ COMMAND_HANDLER(handle_armv4_5_reg_command)
 				value = buf_get_u32(reg->value, 0, 32);
 				output_len += snprintf(output + output_len,
 						sizeof(output) - output_len,
-					       "%8s: %8.8" PRIx32 " ",
-					       reg->name, value);
+						"%8s: %8.8" PRIx32 " ",
+						reg->name, value);
 			}
 			command_print(CMD_CTX, "%s", output);
 		}
@@ -708,29 +697,22 @@ COMMAND_HANDLER(handle_armv4_5_core_state_command)
 	struct target *target = get_current_target(CMD_CTX);
 	struct arm *arm = target_to_arm(target);
 
-	if (!is_arm(arm))
-	{
+	if (!is_arm(arm)) {
 		command_print(CMD_CTX, "current target isn't an ARM");
 		return ERROR_FAIL;
 	}
 
-	if (arm->core_type == ARM_MODE_THREAD)
-	{
+	if (arm->core_type == ARM_MODE_THREAD) {
 		/* armv7m not supported */
 		command_print(CMD_CTX, "Unsupported Command");
 		return ERROR_OK;
 	}
 
-	if (CMD_ARGC > 0)
-	{
+	if (CMD_ARGC > 0) {
 		if (strcmp(CMD_ARGV[0], "arm") == 0)
-		{
 			arm->core_state = ARM_STATE_ARM;
-		}
 		if (strcmp(CMD_ARGV[0], "thumb") == 0)
-		{
 			arm->core_state = ARM_STATE_THUMB;
-		}
 	}
 
 	command_print(CMD_CTX, "core state: %s", arm_state_strings[arm->core_state]);
@@ -758,35 +740,34 @@ COMMAND_HANDLER(handle_arm_disassemble_command)
 		return ERROR_FAIL;
 	}
 
-	if (arm->core_type == ARM_MODE_THREAD)
-	{
+	if (arm->core_type == ARM_MODE_THREAD) {
 		/* armv7m is always thumb mode */
 		thumb = 1;
 	}
 
 	switch (CMD_ARGC) {
-	case 3:
-		if (strcmp(CMD_ARGV[2], "thumb") != 0)
-			goto usage;
-		thumb = 1;
+		case 3:
+			if (strcmp(CMD_ARGV[2], "thumb") != 0)
+				goto usage;
+			thumb = 1;
 		/* FALL THROUGH */
-	case 2:
-		COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], count);
+		case 2:
+			COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], count);
 		/* FALL THROUGH */
-	case 1:
-		COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
-		if (address & 0x01) {
-			if (!thumb) {
-				command_print(CMD_CTX, "Disassemble as Thumb");
-				thumb = 1;
+		case 1:
+			COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
+			if (address & 0x01) {
+				if (!thumb) {
+					command_print(CMD_CTX, "Disassemble as Thumb");
+					thumb = 1;
+				}
+				address &= ~1;
 			}
-			address &= ~1;
-		}
-		break;
-	default:
+			break;
+		default:
 usage:
-		count = 0;
-		retval = ERROR_COMMAND_SYNTAX_ERROR;
+			count = 0;
+			retval = ERROR_COMMAND_SYNTAX_ERROR;
 	}
 
 	while (count-- > 0) {
@@ -819,7 +800,7 @@ usage:
 	return retval;
 }
 
-static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
+static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
 {
 	struct command_context *context;
 	struct target *target;
@@ -827,7 +808,7 @@ static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
 	int retval;
 
 	context = current_command_context(interp);
-	assert( context != NULL);
+	assert(context != NULL);
 
 	target = get_current_target(context);
 	if (target == NULL) {
@@ -868,7 +849,7 @@ static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
 		return retval;
 	if (l & ~0xf) {
 		LOG_ERROR("%s: %s %d out of range", __func__,
-				"coprocessor", (int) l);
+			"coprocessor", (int) l);
 		return JIM_ERR;
 	}
 	cpnum = l;
@@ -878,7 +859,7 @@ static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
 		return retval;
 	if (l & ~0x7) {
 		LOG_ERROR("%s: %s %d out of range", __func__,
-				"op1", (int) l);
+			"op1", (int) l);
 		return JIM_ERR;
 	}
 	op1 = l;
@@ -888,7 +869,7 @@ static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
 		return retval;
 	if (l & ~0xf) {
 		LOG_ERROR("%s: %s %d out of range", __func__,
-				"CRn", (int) l);
+			"CRn", (int) l);
 		return JIM_ERR;
 	}
 	CRn = l;
@@ -898,7 +879,7 @@ static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
 		return retval;
 	if (l & ~0xf) {
 		LOG_ERROR("%s: %s %d out of range", __func__,
-				"CRm", (int) l);
+			"CRm", (int) l);
 		return JIM_ERR;
 	}
 	CRm = l;
@@ -908,7 +889,7 @@ static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
 		return retval;
 	if (l & ~0x7) {
 		LOG_ERROR("%s: %s %d out of range", __func__,
-				"op2", (int) l);
+			"op2", (int) l);
 		return JIM_ERR;
 	}
 	op2 = l;
@@ -925,19 +906,18 @@ static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
 	 */
 	if (argc == 7) {
 		retval = Jim_GetLong(interp, argv[6], &l);
-		if (retval != JIM_OK) {
+		if (retval != JIM_OK)
 			return retval;
-		}
 		value = l;
 
 		/* NOTE: parameters reordered! */
-		// ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2)
+		/* ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2) */
 		retval = arm->mcr(target, cpnum, op1, op2, CRn, CRm, value);
 		if (retval != ERROR_OK)
 			return JIM_ERR;
 	} else {
 		/* NOTE: parameters reordered! */
-		// ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2)
+		/* ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2) */
 		retval = arm->mrc(target, cpnum, op1, op2, CRn, CRm, &value);
 		if (retval != ERROR_OK)
 			return JIM_ERR;
@@ -964,20 +944,17 @@ COMMAND_HANDLER(handle_arm_semihosting_command)
 		return ERROR_FAIL;
 	}
 
-	if (!arm->setup_semihosting)
-	{
+	if (!arm->setup_semihosting) {
 		command_print(CMD_CTX, "semihosting not supported for current target");
 		return ERROR_FAIL;
 	}
 
-	if (CMD_ARGC > 0)
-	{
+	if (CMD_ARGC > 0) {
 		int semihosting;
 
 		COMMAND_PARSE_ENABLE(CMD_ARGV[0], semihosting);
 
-		if (!target_was_examined(target))
-		{
+		if (!target_was_examined(target)) {
 			LOG_ERROR("Target not examined yet");
 			return ERROR_FAIL;
 		}
@@ -992,8 +969,8 @@ COMMAND_HANDLER(handle_arm_semihosting_command)
 	}
 
 	command_print(CMD_CTX, "semihosting is %s",
-			arm->is_semihosting
-			? "enabled" : "disabled");
+		arm->is_semihosting
+		? "enabled" : "disabled");
 
 	return ERROR_OK;
 }
@@ -1055,19 +1032,18 @@ const struct command_registration arm_command_handlers[] = {
 };
 
 int arm_get_gdb_reg_list(struct target *target,
-		struct reg **reg_list[], int *reg_list_size)
+	struct reg **reg_list[], int *reg_list_size)
 {
 	struct arm *arm = target_to_arm(target);
 	int i;
 
-	if (!is_arm_mode(arm->core_mode))
-	{
+	if (!is_arm_mode(arm->core_mode)) {
 		LOG_ERROR("not a valid arm core mode - communication failure?");
 		return ERROR_FAIL;
 	}
 
 	*reg_list_size = 26;
-	*reg_list = malloc(sizeof(struct reg*) * (*reg_list_size));
+	*reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
 
 	for (i = 0; i < 16; i++)
 		(*reg_list)[i] = arm_reg_current(arm, i);
@@ -1082,30 +1058,31 @@ int arm_get_gdb_reg_list(struct target *target,
 }
 
 /* wait for execution to complete and check exit point */
-static int armv4_5_run_algorithm_completion(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info)
+static int armv4_5_run_algorithm_completion(struct target *target,
+	uint32_t exit_point,
+	int timeout_ms,
+	void *arch_info)
 {
 	int retval;
 	struct arm *arm = target_to_arm(target);
 
-	if ((retval = target_wait_state(target, TARGET_HALTED, timeout_ms)) != ERROR_OK)
-	{
+	retval = target_wait_state(target, TARGET_HALTED, timeout_ms);
+	if (retval != ERROR_OK)
 		return retval;
-	}
-	if (target->state != TARGET_HALTED)
-	{
-		if ((retval = target_halt(target)) != ERROR_OK)
+	if (target->state != TARGET_HALTED) {
+		retval = target_halt(target);
+		if (retval != ERROR_OK)
 			return retval;
-		if ((retval = target_wait_state(target, TARGET_HALTED, 500)) != ERROR_OK)
-		{
+		retval = target_wait_state(target, TARGET_HALTED, 500);
+		if (retval != ERROR_OK)
 			return retval;
-		}
 		return ERROR_TARGET_TIMEOUT;
 	}
 
 	/* fast exit: ARMv5+ code can use BKPT */
-	if (exit_point && buf_get_u32(arm->pc->value, 0, 32) != exit_point)
-	{
-		LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "",
+	if (exit_point && buf_get_u32(arm->pc->value, 0, 32) != exit_point) {
+		LOG_WARNING(
+			"target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "",
 			buf_get_u32(arm->pc->value, 0, 32));
 		return ERROR_TARGET_TIMEOUT;
 	}
@@ -1114,12 +1091,12 @@ static int armv4_5_run_algorithm_completion(struct target *target, uint32_t exit
 }
 
 int armv4_5_run_algorithm_inner(struct target *target,
-		int num_mem_params, struct mem_param *mem_params,
-		int num_reg_params, struct reg_param *reg_params,
-		uint32_t entry_point, uint32_t exit_point,
-		int timeout_ms, void *arch_info,
-		int (*run_it)(struct target *target, uint32_t exit_point,
-				int timeout_ms, void *arch_info))
+	int num_mem_params, struct mem_param *mem_params,
+	int num_reg_params, struct reg_param *reg_params,
+	uint32_t entry_point, uint32_t exit_point,
+	int timeout_ms, void *arch_info,
+	int (*run_it)(struct target *target, uint32_t exit_point,
+	int timeout_ms, void *arch_info))
 {
 	struct arm *arm = target_to_arm(target);
 	struct arm_algorithm *arm_algorithm_info = arch_info;
@@ -1132,27 +1109,23 @@ int armv4_5_run_algorithm_inner(struct target *target,
 
 	LOG_DEBUG("Running algorithm");
 
-	if (arm_algorithm_info->common_magic != ARM_COMMON_MAGIC)
-	{
+	if (arm_algorithm_info->common_magic != ARM_COMMON_MAGIC) {
 		LOG_ERROR("current target isn't an ARMV4/5 target");
 		return ERROR_TARGET_INVALID;
 	}
 
-	if (target->state != TARGET_HALTED)
-	{
+	if (target->state != TARGET_HALTED) {
 		LOG_WARNING("target not halted");
 		return ERROR_TARGET_NOT_HALTED;
 	}
 
-	if (!is_arm_mode(arm->core_mode))
-	{
+	if (!is_arm_mode(arm->core_mode)) {
 		LOG_ERROR("not a valid arm core mode - communication failure?");
 		return ERROR_FAIL;
 	}
 
 	/* armv5 and later can terminate with BKPT instruction; less overhead */
-	if (!exit_point && arm->is_armv4)
-	{
+	if (!exit_point && arm->is_armv4) {
 		LOG_ERROR("ARMv4 target needs HW breakpoint location");
 		return ERROR_FAIL;
 	}
@@ -1160,46 +1133,41 @@ int armv4_5_run_algorithm_inner(struct target *target,
 	/* save r0..pc, cpsr-or-spsr, and then cpsr-for-sure;
 	 * they'll be restored later.
 	 */
-	for (i = 0; i <= 16; i++)
-	{
+	for (i = 0; i <= 16; i++) {
 		struct reg *r;
 
 		r = &ARMV4_5_CORE_REG_MODE(arm->core_cache,
 				arm_algorithm_info->core_mode, i);
 		if (!r->valid)
 			arm->read_core_reg(target, r, i,
-					arm_algorithm_info->core_mode);
+				arm_algorithm_info->core_mode);
 		context[i] = buf_get_u32(r->value, 0, 32);
 	}
 	cpsr = buf_get_u32(arm->cpsr->value, 0, 32);
 
-	for (i = 0; i < num_mem_params; i++)
-	{
-		if ((retval = target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK)
-		{
+	for (i = 0; i < num_mem_params; i++) {
+		retval = target_write_buffer(target, mem_params[i].address, mem_params[i].size,
+				mem_params[i].value);
+		if (retval != ERROR_OK)
 			return retval;
-		}
 	}
 
-	for (i = 0; i < num_reg_params; i++)
-	{
+	for (i = 0; i < num_reg_params; i++) {
 		struct reg *reg = register_get_by_name(arm->core_cache, reg_params[i].reg_name, 0);
-		if (!reg)
-		{
+		if (!reg) {
 			LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
 			return ERROR_COMMAND_SYNTAX_ERROR;
 		}
 
-		if (reg->size != reg_params[i].size)
-		{
-			LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
+		if (reg->size != reg_params[i].size) {
+			LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size",
+				reg_params[i].reg_name);
 			return ERROR_COMMAND_SYNTAX_ERROR;
 		}
 
-		if ((retval = armv4_5_set_core_reg(reg, reg_params[i].value)) != ERROR_OK)
-		{
+		retval = armv4_5_set_core_reg(reg, reg_params[i].value);
+		if (retval != ERROR_OK)
 			return retval;
-		}
 	}
 
 	arm->core_state = arm_algorithm_info->core_state;
@@ -1207,35 +1175,33 @@ int armv4_5_run_algorithm_inner(struct target *target,
 		exit_breakpoint_size = 4;
 	else if (arm->core_state == ARM_STATE_THUMB)
 		exit_breakpoint_size = 2;
-	else
-	{
+	else {
 		LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
 		return ERROR_COMMAND_SYNTAX_ERROR;
 	}
 
-	if (arm_algorithm_info->core_mode != ARM_MODE_ANY)
-	{
+	if (arm_algorithm_info->core_mode != ARM_MODE_ANY) {
 		LOG_DEBUG("setting core_mode: 0x%2.2x",
-				arm_algorithm_info->core_mode);
+			arm_algorithm_info->core_mode);
 		buf_set_u32(arm->cpsr->value, 0, 5,
-				arm_algorithm_info->core_mode);
+			arm_algorithm_info->core_mode);
 		arm->cpsr->dirty = 1;
 		arm->cpsr->valid = 1;
 	}
 
 	/* terminate using a hardware or (ARMv5+) software breakpoint */
-	if (exit_point && (retval = breakpoint_add(target, exit_point,
-				exit_breakpoint_size, BKPT_HARD)) != ERROR_OK)
-	{
-		LOG_ERROR("can't add HW breakpoint to terminate algorithm");
-		return ERROR_TARGET_FAILURE;
+	if (exit_point) {
+		retval = breakpoint_add(target, exit_point,
+				exit_breakpoint_size, BKPT_HARD);
+		if (retval != ERROR_OK) {
+			LOG_ERROR("can't add HW breakpoint to terminate algorithm");
+			return ERROR_TARGET_FAILURE;
+		}
 	}
 
-	if ((retval = target_resume(target, 0, entry_point, 1, 1)) != ERROR_OK)
-	{
+	retval = target_resume(target, 0, entry_point, 1, 1);
+	if (retval != ERROR_OK)
 		return retval;
-	}
-	int retvaltemp;
 	retval = run_it(target, exit_point, timeout_ms, arch_info);
 
 	if (exit_point)
@@ -1244,31 +1210,32 @@ int armv4_5_run_algorithm_inner(struct target *target,
 	if (retval != ERROR_OK)
 		return retval;
 
-	for (i = 0; i < num_mem_params; i++)
-	{
-		if (mem_params[i].direction != PARAM_OUT)
-			if ((retvaltemp = target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK)
-			{
-					retval = retvaltemp;
-			}
+	for (i = 0; i < num_mem_params; i++) {
+		if (mem_params[i].direction != PARAM_OUT) {
+			int retvaltemp = target_read_buffer(target, mem_params[i].address,
+					mem_params[i].size,
+					mem_params[i].value);
+			if (retvaltemp != ERROR_OK)
+				retval = retvaltemp;
+		}
 	}
 
-	for (i = 0; i < num_reg_params; i++)
-	{
-		if (reg_params[i].direction != PARAM_OUT)
-		{
+	for (i = 0; i < num_reg_params; i++) {
+		if (reg_params[i].direction != PARAM_OUT) {
 
-			struct reg *reg = register_get_by_name(arm->core_cache, reg_params[i].reg_name, 0);
-			if (!reg)
-			{
+			struct reg *reg = register_get_by_name(arm->core_cache,
+					reg_params[i].reg_name,
+					0);
+			if (!reg) {
 				LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
 				retval = ERROR_COMMAND_SYNTAX_ERROR;
 				continue;
 			}
 
-			if (reg->size != reg_params[i].size)
-			{
-				LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
+			if (reg->size != reg_params[i].size) {
+				LOG_ERROR(
+					"BUG: register '%s' size doesn't match reg_params[i].size",
+					reg_params[i].reg_name);
 				retval = ERROR_COMMAND_SYNTAX_ERROR;
 				continue;
 			}
@@ -1278,20 +1245,20 @@ int armv4_5_run_algorithm_inner(struct target *target,
 	}
 
 	/* restore everything we saved before (17 or 18 registers) */
-	for (i = 0; i <= 16; i++)
-	{
+	for (i = 0; i <= 16; i++) {
 		uint32_t regvalue;
 		regvalue = buf_get_u32(ARMV4_5_CORE_REG_MODE(arm->core_cache,
 				arm_algorithm_info->core_mode, i).value, 0, 32);
-		if (regvalue != context[i])
-		{
+		if (regvalue != context[i]) {
 			LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "",
-					ARMV4_5_CORE_REG_MODE(arm->core_cache,
-					arm_algorithm_info->core_mode, i).name, context[i]);
+				ARMV4_5_CORE_REG_MODE(arm->core_cache,
+				arm_algorithm_info->core_mode, i).name, context[i]);
 			buf_set_u32(ARMV4_5_CORE_REG_MODE(arm->core_cache,
-					arm_algorithm_info->core_mode, i).value, 0, 32, context[i]);
-			ARMV4_5_CORE_REG_MODE(arm->core_cache, arm_algorithm_info->core_mode, i).valid = 1;
-			ARMV4_5_CORE_REG_MODE(arm->core_cache, arm_algorithm_info->core_mode, i).dirty = 1;
+				arm_algorithm_info->core_mode, i).value, 0, 32, context[i]);
+			ARMV4_5_CORE_REG_MODE(arm->core_cache, arm_algorithm_info->core_mode,
+				i).valid = 1;
+			ARMV4_5_CORE_REG_MODE(arm->core_cache, arm_algorithm_info->core_mode,
+				i).dirty = 1;
 		}
 	}
 
@@ -1303,9 +1270,26 @@ int armv4_5_run_algorithm_inner(struct target *target,
 	return retval;
 }
 
-int armv4_5_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info)
+int armv4_5_run_algorithm(struct target *target,
+	int num_mem_params,
+	struct mem_param *mem_params,
+	int num_reg_params,
+	struct reg_param *reg_params,
+	uint32_t entry_point,
+	uint32_t exit_point,
+	int timeout_ms,
+	void *arch_info)
 {
-	return armv4_5_run_algorithm_inner(target, num_mem_params, mem_params, num_reg_params, reg_params, entry_point, exit_point, timeout_ms, arch_info, armv4_5_run_algorithm_completion);
+	return armv4_5_run_algorithm_inner(target,
+			num_mem_params,
+			mem_params,
+			num_reg_params,
+			reg_params,
+			entry_point,
+			exit_point,
+			timeout_ms,
+			arch_info,
+			armv4_5_run_algorithm_completion);
 }
 
 /**
@@ -1313,7 +1297,7 @@ int armv4_5_run_algorithm(struct target *target, int num_mem_params, struct mem_
  *
  */
 int arm_checksum_memory(struct target *target,
-		uint32_t address, uint32_t count, uint32_t *checksum)
+	uint32_t address, uint32_t count, uint32_t *checksum)
 {
 	struct working_area *crc_algorithm;
 	struct arm_algorithm armv4_5_info;
@@ -1414,7 +1398,7 @@ int arm_checksum_memory(struct target *target,
  *
  */
 int arm_blank_check_memory(struct target *target,
-		uint32_t address, uint32_t count, uint32_t *blank)
+	uint32_t address, uint32_t count, uint32_t *blank)
 {
 	struct working_area *check_algorithm;
 	struct reg_param reg_params[3];
@@ -1444,7 +1428,7 @@ int arm_blank_check_memory(struct target *target,
 	for (i = 0; i < ARRAY_SIZE(check_code); i++) {
 		retval = target_write_u32(target,
 				check_algorithm->address
-						+ i * sizeof(uint32_t),
+				+ i * sizeof(uint32_t),
 				check_code[i]);
 		if (retval != ERROR_OK)
 			return retval;
@@ -1506,18 +1490,18 @@ static int arm_full_context(struct target *target)
 }
 
 static int arm_default_mrc(struct target *target, int cpnum,
-		uint32_t op1, uint32_t op2,
-		uint32_t CRn, uint32_t CRm,
-		uint32_t *value)
+	uint32_t op1, uint32_t op2,
+	uint32_t CRn, uint32_t CRm,
+	uint32_t *value)
 {
 	LOG_ERROR("%s doesn't implement MRC", target_type_name(target));
 	return ERROR_FAIL;
 }
 
 static int arm_default_mcr(struct target *target, int cpnum,
-		uint32_t op1, uint32_t op2,
-		uint32_t CRn, uint32_t CRm,
-		uint32_t value)
+	uint32_t op1, uint32_t op2,
+	uint32_t CRn, uint32_t CRm,
+	uint32_t value)
 {
 	LOG_ERROR("%s doesn't implement MCR", target_type_name(target));
 	return ERROR_FAIL;