X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm_simulator.c;h=b47606d633bb55a20852f50df3ab88881cc45ebc;hp=561b14f8f2c71bbbadf7738a0dcbae2cb0fdff95;hb=45af9d83c90134ec929599bf4a05360e8bd1e8be;hpb=237e894805dd757cc24029af1b4b1e824c51712b diff --git a/src/target/arm_simulator.c b/src/target/arm_simulator.c index 561b14f8f2..b47606d633 100644 --- a/src/target/arm_simulator.c +++ b/src/target/arm_simulator.c @@ -32,7 +32,7 @@ u32 arm_shift(u8 shift, u32 Rm, u32 shift_amount, u8 *carry) { - u32 return_value; + u32 return_value = 0; shift_amount &= 0xff; if (shift == 0x0) /* LSL */ @@ -269,13 +269,14 @@ int thumb_pass_branch_condition(u32 cpsr, u16 opcode) int arm_simulate_step(target_t *target, u32 *dry_run_pc) { armv4_5_common_t *armv4_5 = target->arch_info; - u32 opcode; u32 current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32); arm_instruction_t instruction; int instruction_size; if (armv4_5->core_state == ARMV4_5_STATE_ARM) { + u32 opcode; + /* get current instruction, and identify it */ target_read_u32(target, current_pc, &opcode); arm_evaluate_opcode(opcode, current_pc, &instruction); @@ -298,8 +299,10 @@ int arm_simulate_step(target_t *target, u32 *dry_run_pc) } else { - target_read_u32(target, current_pc, &opcode); - arm_evaluate_opcode(opcode, current_pc, &instruction); + u16 opcode; + + target_read_u16(target, current_pc, &opcode); + thumb_evaluate_opcode(opcode, current_pc, &instruction); instruction_size = 2; /* check condition code (only for branch instructions) */ @@ -463,7 +466,7 @@ int arm_simulate_step(target_t *target, u32 *dry_run_pc) /* load register instructions */ else if ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_LDRSH)) { - u32 load_address, modified_address, load_value; + u32 load_address = 0, modified_address = 0, load_value; u32 Rn = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.load_store.Rn).value, 0, 32); /* adjust Rn in case the PC is being read */