X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm_simulator.c;h=0a34cfcf4967fd207e6a2a84673b85aa7b9e1af4;hp=73aac962507f1d8f940b7efec14b9847d782c5f1;hb=1163435e19f316a4a97fd33f1467f5c1684db654;hpb=ab5ac33fd462c37e4cf5a6bc1fe5fd0631e44469 diff --git a/src/target/arm_simulator.c b/src/target/arm_simulator.c index 73aac96250..0a34cfcf49 100644 --- a/src/target/arm_simulator.c +++ b/src/target/arm_simulator.c @@ -24,12 +24,13 @@ #include "config.h" #endif +#include "arm.h" #include "armv4_5.h" #include "arm_disassembler.h" #include "arm_simulator.h" -#include "binarybuffer.h" +#include #include "register.h" -#include "log.h" +#include static uint32_t arm_shift(uint8_t shift, uint32_t Rm, @@ -135,7 +136,7 @@ static uint32_t arm_shifter_operand(struct arm_sim_interface *sim, uint32_t return_value; int instruction_size; - if (sim->get_state(sim) == ARMV4_5_STATE_ARM) + if (sim->get_state(sim) == ARM_STATE_ARM) instruction_size = 4; else instruction_size = 2; @@ -278,7 +279,7 @@ static int thumb_pass_branch_condition(uint32_t cpsr, uint16_t opcode) * if the dry_run_pc argument is provided, no state is changed, * but the new pc is stored in the variable pointed at by the argument */ -int arm_simulate_step_core(struct target *target, +static int arm_simulate_step_core(struct target *target, uint32_t *dry_run_pc, struct arm_sim_interface *sim) { uint32_t current_pc = sim->get_reg(sim, 15); @@ -286,7 +287,7 @@ int arm_simulate_step_core(struct target *target, int instruction_size; int retval = ERROR_OK; - if (sim->get_state(sim) == ARMV4_5_STATE_ARM) + if (sim->get_state(sim) == ARM_STATE_ARM) { uint32_t opcode; @@ -363,66 +364,66 @@ int arm_simulate_step_core(struct target *target, /* branch instructions */ if ((instruction.type >= ARM_B) && (instruction.type <= ARM_BLX)) { - uint32_t target; + uint32_t target_address; if (instruction.info.b_bl_bx_blx.reg_operand == -1) { - target = instruction.info.b_bl_bx_blx.target_address; + target_address = instruction.info.b_bl_bx_blx.target_address; } else { - target = sim->get_reg_mode(sim, instruction.info.b_bl_bx_blx.reg_operand); + target_address = sim->get_reg_mode(sim, instruction.info.b_bl_bx_blx.reg_operand); if (instruction.info.b_bl_bx_blx.reg_operand == 15) { - target += 2 * instruction_size; + target_address += 2 * instruction_size; } } if (dry_run_pc) { - *dry_run_pc = target & ~1; + *dry_run_pc = target_address & ~1; return ERROR_OK; } else { if (instruction.type == ARM_B) { - sim->set_reg(sim, 15, target); + sim->set_reg(sim, 15, target_address); } else if (instruction.type == ARM_BL) { uint32_t old_pc = sim->get_reg(sim, 15); - int T = (sim->get_state(sim) == ARMV4_5_STATE_THUMB); + int T = (sim->get_state(sim) == ARM_STATE_THUMB); sim->set_reg_mode(sim, 14, old_pc + 4 + T); - sim->set_reg(sim, 15, target); + sim->set_reg(sim, 15, target_address); } else if (instruction.type == ARM_BX) { - if (target & 0x1) + if (target_address & 0x1) { - sim->set_state(sim, ARMV4_5_STATE_THUMB); + sim->set_state(sim, ARM_STATE_THUMB); } else { - sim->set_state(sim, ARMV4_5_STATE_ARM); + sim->set_state(sim, ARM_STATE_ARM); } - sim->set_reg(sim, 15, target & 0xfffffffe); + sim->set_reg(sim, 15, target_address & 0xfffffffe); } else if (instruction.type == ARM_BLX) { uint32_t old_pc = sim->get_reg(sim, 15); - int T = (sim->get_state(sim) == ARMV4_5_STATE_THUMB); + int T = (sim->get_state(sim) == ARM_STATE_THUMB); sim->set_reg_mode(sim, 14, old_pc + 4 + T); - if (target & 0x1) + if (target_address & 0x1) { - sim->set_state(sim, ARMV4_5_STATE_THUMB); + sim->set_state(sim, ARM_STATE_THUMB); } else { - sim->set_state(sim, ARMV4_5_STATE_ARM); + sim->set_state(sim, ARM_STATE_ARM); } - sim->set_reg(sim, 15, target & 0xfffffffe); + sim->set_reg(sim, 15, target_address & 0xfffffffe); } return ERROR_OK; @@ -493,9 +494,9 @@ int arm_simulate_step_core(struct target *target, if (instruction.info.data_proc.Rd == 15) { sim->set_reg_mode(sim, 15, Rd & ~1); if (Rd & 1) - sim->set_state(sim, ARMV4_5_STATE_THUMB); + sim->set_state(sim, ARM_STATE_THUMB); else - sim->set_state(sim, ARMV4_5_STATE_ARM); + sim->set_state(sim, ARM_STATE_ARM); return ERROR_OK; } sim->set_reg_mode(sim, instruction.info.data_proc.Rd, Rd); @@ -605,9 +606,9 @@ int arm_simulate_step_core(struct target *target, if (instruction.info.load_store.Rd == 15) { sim->set_reg_mode(sim, 15, load_value & ~1); if (load_value & 1) - sim->set_state(sim, ARMV4_5_STATE_THUMB); + sim->set_state(sim, ARM_STATE_THUMB); else - sim->set_state(sim, ARMV4_5_STATE_ARM); + sim->set_state(sim, ARM_STATE_ARM); return ERROR_OK; } sim->set_reg_mode(sim, instruction.info.load_store.Rd, load_value); @@ -665,15 +666,12 @@ int arm_simulate_step_core(struct target *target, } else { - enum armv4_5_mode mode = sim->get_mode(sim); int update_cpsr = 0; if (instruction.info.load_store_multiple.S) { if (instruction.info.load_store_multiple.register_list & 0x8000) update_cpsr = 1; - else - mode = ARMV4_5_MODE_USR; } for (i = 0; i < 16; i++) @@ -684,9 +682,9 @@ int arm_simulate_step_core(struct target *target, uint32_t val = load_values[i]; sim->set_reg_mode(sim, i, val & ~1); if (val & 1) - sim->set_state(sim, ARMV4_5_STATE_THUMB); + sim->set_state(sim, ARM_STATE_THUMB); else - sim->set_state(sim, ARMV4_5_STATE_ARM); + sim->set_state(sim, ARM_STATE_ARM); } else { sim->set_reg_mode(sim, i, load_values[i]); } @@ -721,7 +719,6 @@ int arm_simulate_step_core(struct target *target, uint32_t Rn = sim->get_reg_mode(sim, instruction.info.load_store_multiple.Rn); int bits_set = 0; - enum armv4_5_mode mode = sim->get_mode(sim); for (i = 0; i < 16; i++) { @@ -729,11 +726,6 @@ int arm_simulate_step_core(struct target *target, bits_set++; } - if (instruction.info.load_store_multiple.S) - { - mode = ARMV4_5_MODE_USR; - } - switch (instruction.info.load_store_multiple.addressing_mode) { case 0: /* Increment after */ @@ -824,14 +816,14 @@ static uint32_t armv4_5_get_cpsr(struct arm_sim_interface *sim, int pos, int bit return buf_get_u32(armv4_5->cpsr->value, pos, bits); } -static enum armv4_5_state armv4_5_get_state(struct arm_sim_interface *sim) +static enum arm_state armv4_5_get_state(struct arm_sim_interface *sim) { struct arm *armv4_5 = (struct arm *)sim->user_data; return armv4_5->core_state; } -static void armv4_5_set_state(struct arm_sim_interface *sim, enum armv4_5_state mode) +static void armv4_5_set_state(struct arm_sim_interface *sim, enum arm_state mode) { struct arm *armv4_5 = (struct arm *)sim->user_data; @@ -839,7 +831,7 @@ static void armv4_5_set_state(struct arm_sim_interface *sim, enum armv4_5_state } -static enum armv4_5_mode armv4_5_get_mode(struct arm_sim_interface *sim) +static enum arm_mode armv4_5_get_mode(struct arm_sim_interface *sim) { struct arm *armv4_5 = (struct arm *)sim->user_data; @@ -850,7 +842,7 @@ static enum armv4_5_mode armv4_5_get_mode(struct arm_sim_interface *sim) int arm_simulate_step(struct target *target, uint32_t *dry_run_pc) { - struct arm *armv4_5 = target_to_armv4_5(target); + struct arm *armv4_5 = target_to_arm(target); struct arm_sim_interface sim; sim.user_data = armv4_5;