X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm_dpm.c;h=8e8cc17aebda5bbad5e1616fee89b32ba364a059;hp=18a9dcc74f771f985cd690fc0851e4a9302328b5;hb=1aac72d24339380f6e98c50dec4c96ab30537749;hpb=e6dc927e972bb2d91131b0193b676c531377f318 diff --git a/src/target/arm_dpm.c b/src/target/arm_dpm.c index 18a9dcc74f..8e8cc17aeb 100644 --- a/src/target/arm_dpm.c +++ b/src/target/arm_dpm.c @@ -21,10 +21,13 @@ #include "config.h" #endif -#include "armv4_5.h" /* REVISIT to become arm.h */ +#include "arm.h" #include "arm_dpm.h" -#include "jtag.h" +#include #include "register.h" +#include "breakpoints.h" +#include "target_type.h" +#include "arm_opcodes.h" /** @@ -32,18 +35,87 @@ * Implements various ARM DPM operations using architectural debug registers. * These routines layer over core-specific communication methods to cope with * implementation differences between cores like ARM1136 and Cortex-A8. + * + * The "Debug Programmers' Model" (DPM) for ARMv6 and ARMv7 is defined by + * Part C (Debug Architecture) of the ARM Architecture Reference Manual, + * ARMv7-A and ARMv7-R edition (ARM DDI 0406B). In OpenOCD, DPM operations + * are abstracted through internal programming interfaces to share code and + * to minimize needless differences in debug behavior between cores. + */ + +/*----------------------------------------------------------------------*/ + +/* + * Coprocessor support + */ + +/* Read coprocessor */ +static int dpm_mrc(struct target *target, int cpnum, + uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, + uint32_t *value) +{ + struct arm *arm = target_to_arm(target); + struct arm_dpm *dpm = arm->dpm; + int retval; + + retval = dpm->prepare(dpm); + if (retval != ERROR_OK) + return retval; + + LOG_DEBUG("MRC p%d, %d, r0, c%d, c%d, %d", cpnum, + (int) op1, (int) CRn, + (int) CRm, (int) op2); + + /* read coprocessor register into R0; return via DCC */ + retval = dpm->instr_read_data_r0(dpm, + ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2), + value); + + /* (void) */ dpm->finish(dpm); + return retval; +} + +static int dpm_mcr(struct target *target, int cpnum, + uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, + uint32_t value) +{ + struct arm *arm = target_to_arm(target); + struct arm_dpm *dpm = arm->dpm; + int retval; + + retval = dpm->prepare(dpm); + if (retval != ERROR_OK) + return retval; + + LOG_DEBUG("MCR p%d, %d, r0, c%d, c%d, %d", cpnum, + (int) op1, (int) CRn, + (int) CRm, (int) op2); + + /* read DCC into r0; then write coprocessor register from R0 */ + retval = dpm->instr_write_data_r0(dpm, + ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2), + value); + + /* (void) */ dpm->finish(dpm); + return retval; +} + +/*----------------------------------------------------------------------*/ + +/* + * Register access utilities */ /* Toggles between recorded core mode (USR, SVC, etc) and a temporary one. * Routines *must* restore the original mode before returning!! */ -static int dpm_modeswitch(struct arm_dpm *dpm, enum armv4_5_mode mode) +static int dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode) { int retval; uint32_t cpsr; /* restore previous mode */ - if (mode == ARMV4_5_MODE_ANY) + if (mode == ARM_MODE_ANY) cpsr = buf_get_u32(dpm->arm->cpsr->value, 0, 32); /* else force to the specified mode */ @@ -52,10 +124,8 @@ static int dpm_modeswitch(struct arm_dpm *dpm, enum armv4_5_mode mode) retval = dpm->instr_write_data_r0(dpm, ARMV4_5_MSR_GP(0, 0xf, 0), cpsr); - /* REVISIT on Cortex-A8, we need a Prefetch Flush operation too ... - cortex_a8_exec_opcode(target, - ARMV4_5_MCR(15, 0, 0, 7, 5, 4)); - */ + if (dpm->instr_cpsr_sync) + retval = dpm->instr_cpsr_sync(dpm); return retval; } @@ -84,14 +154,14 @@ static int dpm_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum) * is always right except in those broken-by-intent cases. */ switch (dpm->arm->core_state) { - case ARMV4_5_STATE_ARM: + case ARM_STATE_ARM: value -= 8; break; - case ARMV4_5_STATE_THUMB: + case ARM_STATE_THUMB: case ARM_STATE_THUMB_EE: value -= 4; break; - case ARMV4_5_STATE_JAZELLE: + case ARM_STATE_JAZELLE: /* core-specific ... ? */ LOG_WARNING("Jazelle PC adjustment unknown"); break; @@ -125,7 +195,7 @@ static int dpm_write_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum) switch (regnum) { case 0 ... 14: - /* load register from DCC: "MCR p14, 0, Rnum, c0, c5, 0" */ + /* load register from DCC: "MRC p14, 0, Rnum, c0, c5, 0" */ retval = dpm->instr_write_data_dcc(dpm, ARMV4_5_MRC(14, 0, regnum, 0, 5, 0), value); @@ -142,11 +212,8 @@ static int dpm_write_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum) ARMV4_5_MSR_GP(0, 0xf, regnum & 1), value); - /* REVISIT on Cortex-A8, we need a Prefetch Flush operation - * after writing CPSR ... - cortex_a8_exec_opcode(target, - ARMV4_5_MCR(15, 0, 0, 7, 5, 4)); - */ + if (regnum == 16 && dpm->instr_cpsr_sync) + retval = dpm->instr_cpsr_sync(dpm); break; } @@ -206,16 +273,73 @@ int arm_dpm_read_current_registers(struct arm_dpm *dpm) /* NOTE: SPSR ignored (if it's even relevant). */ + /* REVISIT the debugger can trigger various exceptions. See the + * ARMv7A architecture spec, section C5.7, for more info about + * what defenses are needed; v6 debug has the most issues. + */ + fail: /* (void) */ dpm->finish(dpm); return retval; } +/* Avoid needless I/O ... leave breakpoints and watchpoints alone + * unless they're removed, or need updating because of single-stepping + * or running debugger code. + */ +static int dpm_maybe_update_bpwp(struct arm_dpm *dpm, bool bpwp, + struct dpm_bpwp *xp, int *set_p) +{ + int retval = ERROR_OK; + bool disable; + + if (!set_p) { + if (!xp->dirty) + goto done; + xp->dirty = false; + /* removed or startup; we must disable it */ + disable = true; + } else if (bpwp) { + if (!xp->dirty) + goto done; + /* disabled, but we must set it */ + xp->dirty = disable = false; + *set_p = true; + } else { + if (!*set_p) + goto done; + /* set, but we must temporarily disable it */ + xp->dirty = disable = true; + *set_p = false; + } + + if (disable) + retval = dpm->bpwp_disable(dpm, xp->number); + else + retval = dpm->bpwp_enable(dpm, xp->number, + xp->address, xp->control); + + if (retval != ERROR_OK) + LOG_ERROR("%s: can't %s HW %spoint %d", + disable ? "disable" : "enable", + target_name(dpm->arm->target), + (xp->number < 16) ? "break" : "watch", + xp->number & 0xf); +done: + return retval; +} + +static int dpm_add_breakpoint(struct target *target, struct breakpoint *bp); + /** * Writes all modified core registers for all processor modes. In normal * operation this is called on exit from halting debug state. + * + * @param dpm: represents the processor + * @param bpwp: true ensures breakpoints and watchpoints are set, + * false ensures they are cleared */ -int arm_dpm_write_dirty_registers(struct arm_dpm *dpm) +int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp) { struct arm *arm = dpm->arm; struct reg_cache *cache = arm->core_cache; @@ -226,13 +350,43 @@ int arm_dpm_write_dirty_registers(struct arm_dpm *dpm) if (retval != ERROR_OK) goto done; + /* If we're managing hardware breakpoints for this core, enable + * or disable them as requested. + * + * REVISIT We don't yet manage them for ANY cores. Eventually + * we should be able to assume we handle them; but until then, + * cope with the hand-crafted breakpoint code. + */ + if (arm->target->type->add_breakpoint == dpm_add_breakpoint) { + for (unsigned i = 0; i < dpm->nbp; i++) { + struct dpm_bp *dbp = dpm->dbp + i; + struct breakpoint *bp = dbp->bp; + + retval = dpm_maybe_update_bpwp(dpm, bpwp, &dbp->bpwp, + bp ? &bp->set : NULL); + } + } + + /* enable/disable watchpoints */ + for (unsigned i = 0; i < dpm->nwp; i++) { + struct dpm_wp *dwp = dpm->dwp + i; + struct watchpoint *wp = dwp->wp; + + retval = dpm_maybe_update_bpwp(dpm, bpwp, &dwp->bpwp, + wp ? &wp->set : NULL); + } + + /* NOTE: writes to breakpoint and watchpoint registers might + * be queued, and need (efficient/batched) flushing later. + */ + /* Scan the registers until we find one that's both dirty and * eligible for flushing. Flush that and everything else that * shares the same core mode setting. Typically this won't * actually find anything to do... */ do { - enum armv4_5_mode mode = ARMV4_5_MODE_ANY; + enum arm_mode mode = ARM_MODE_ANY; did_write = false; @@ -254,7 +408,7 @@ int arm_dpm_write_dirty_registers(struct arm_dpm *dpm) /* may need to pick and set a mode */ if (!did_write) { - enum armv4_5_mode tmode; + enum arm_mode tmode; did_write = true; mode = tmode = r->mode; @@ -266,10 +420,10 @@ int arm_dpm_write_dirty_registers(struct arm_dpm *dpm) * we "know" core mode is accurate * since we haven't changed it yet */ - if (arm->core_mode == ARMV4_5_MODE_FIQ - && ARMV4_5_MODE_ANY + if (arm->core_mode == ARM_MODE_FIQ + && ARM_MODE_ANY != mode) - tmode = ARMV4_5_MODE_USR; + tmode = ARM_MODE_USR; break; case 16: /* SPSR */ @@ -278,7 +432,7 @@ int arm_dpm_write_dirty_registers(struct arm_dpm *dpm) } /* REVISIT error checks */ - if (tmode != ARMV4_5_MODE_ANY) + if (tmode != ARM_MODE_ANY) retval = dpm_modeswitch(dpm, tmode); } if (r->mode != mode) @@ -296,11 +450,11 @@ int arm_dpm_write_dirty_registers(struct arm_dpm *dpm) * or it's dirty. Must write PC to ensure the return address is * defined, and must not write it before CPSR. */ - retval = dpm_modeswitch(dpm, ARMV4_5_MODE_ANY); + retval = dpm_modeswitch(dpm, ARM_MODE_ANY); arm->cpsr->dirty = false; - retval = dpm_write_reg(dpm, &cache->reg_list[15], 15); - cache->reg_list[15].dirty = false; + retval = dpm_write_reg(dpm, arm->pc, 15); + arm->pc->dirty = false; /* flush R0 -- it's *very* dirty by now */ retval = dpm_write_reg(dpm, &cache->reg_list[0], 0); @@ -311,21 +465,21 @@ done: return retval; } -/* Returns ARMV4_5_MODE_ANY or temporary mode to use while reading the +/* Returns ARM_MODE_ANY or temporary mode to use while reading the * specified register ... works around flakiness from ARM core calls. * Caller already filtered out SPSR access; mode is never MODE_SYS * or MODE_ANY. */ -static enum armv4_5_mode dpm_mapmode(struct arm *arm, - unsigned num, enum armv4_5_mode mode) +static enum arm_mode dpm_mapmode(struct arm *arm, + unsigned num, enum arm_mode mode) { - enum armv4_5_mode amode = arm->core_mode; + enum arm_mode amode = arm->core_mode; /* don't switch if the mode is already correct */ - if (amode == ARMV4_5_MODE_SYS) - amode = ARMV4_5_MODE_USR; + if (amode == ARM_MODE_SYS) + amode = ARM_MODE_USR; if (mode == amode) - return ARMV4_5_MODE_ANY; + return ARM_MODE_ANY; switch (num) { /* don't switch for non-shadowed registers (r0..r7, r15/pc, cpsr) */ @@ -335,7 +489,7 @@ static enum armv4_5_mode dpm_mapmode(struct arm *arm, break; /* r8..r12 aren't shadowed for anything except FIQ */ case 8 ... 12: - if (mode == ARMV4_5_MODE_FIQ) + if (mode == ARM_MODE_FIQ) return mode; break; /* r13/sp, and r14/lr are always shadowed */ @@ -346,11 +500,18 @@ static enum armv4_5_mode dpm_mapmode(struct arm *arm, LOG_WARNING("invalid register #%u", num); break; } - return ARMV4_5_MODE_ANY; + return ARM_MODE_ANY; } + +/* + * Standard ARM register accessors ... there are three methods + * in "struct arm", to support individual read/write and bulk read + * of registers. + */ + static int arm_dpm_read_core_reg(struct target *target, struct reg *r, - int regnum, enum armv4_5_mode mode) + int regnum, enum arm_mode mode) { struct arm_dpm *dpm = target_to_arm(target)->dpm; int retval; @@ -359,7 +520,7 @@ static int arm_dpm_read_core_reg(struct target *target, struct reg *r, return ERROR_INVALID_ARGUMENTS; if (regnum == 16) { - if (mode != ARMV4_5_MODE_ANY) + if (mode != ARM_MODE_ANY) regnum = 17; } else mode = dpm_mapmode(dpm->arm, regnum, mode); @@ -372,7 +533,7 @@ static int arm_dpm_read_core_reg(struct target *target, struct reg *r, if (retval != ERROR_OK) return retval; - if (mode != ARMV4_5_MODE_ANY) { + if (mode != ARM_MODE_ANY) { retval = dpm_modeswitch(dpm, mode); if (retval != ERROR_OK) goto fail; @@ -381,8 +542,8 @@ static int arm_dpm_read_core_reg(struct target *target, struct reg *r, retval = dpm_read_reg(dpm, r, regnum); /* always clean up, regardless of error */ - if (mode != ARMV4_5_MODE_ANY) - /* (void) */ dpm_modeswitch(dpm, ARMV4_5_MODE_ANY); + if (mode != ARM_MODE_ANY) + /* (void) */ dpm_modeswitch(dpm, ARM_MODE_ANY); fail: /* (void) */ dpm->finish(dpm); @@ -390,7 +551,7 @@ fail: } static int arm_dpm_write_core_reg(struct target *target, struct reg *r, - int regnum, enum armv4_5_mode mode, uint32_t value) + int regnum, enum arm_mode mode, uint32_t value) { struct arm_dpm *dpm = target_to_arm(target)->dpm; int retval; @@ -400,7 +561,7 @@ static int arm_dpm_write_core_reg(struct target *target, struct reg *r, return ERROR_INVALID_ARGUMENTS; if (regnum == 16) { - if (mode != ARMV4_5_MODE_ANY) + if (mode != ARM_MODE_ANY) regnum = 17; } else mode = dpm_mapmode(dpm->arm, regnum, mode); @@ -413,7 +574,7 @@ static int arm_dpm_write_core_reg(struct target *target, struct reg *r, if (retval != ERROR_OK) return retval; - if (mode != ARMV4_5_MODE_ANY) { + if (mode != ARM_MODE_ANY) { retval = dpm_modeswitch(dpm, mode); if (retval != ERROR_OK) goto fail; @@ -422,8 +583,8 @@ static int arm_dpm_write_core_reg(struct target *target, struct reg *r, retval = dpm_write_reg(dpm, r, regnum); /* always clean up, regardless of error */ - if (mode != ARMV4_5_MODE_ANY) - /* (void) */ dpm_modeswitch(dpm, ARMV4_5_MODE_ANY); + if (mode != ARM_MODE_ANY) + /* (void) */ dpm_modeswitch(dpm, ARM_MODE_ANY); fail: /* (void) */ dpm->finish(dpm); @@ -443,7 +604,7 @@ static int arm_dpm_full_context(struct target *target) goto done; do { - enum armv4_5_mode mode = ARMV4_5_MODE_ANY; + enum arm_mode mode = ARM_MODE_ANY; did_read = false; @@ -470,8 +631,8 @@ static int arm_dpm_full_context(struct target *target) /* For R8..R12 when we've entered debug * state in FIQ mode... patch mode. */ - if (mode == ARMV4_5_MODE_ANY) - mode = ARMV4_5_MODE_USR; + if (mode == ARM_MODE_ANY) + mode = ARM_MODE_USR; /* REVISIT error checks */ retval = dpm_modeswitch(dpm, mode); @@ -488,15 +649,268 @@ static int arm_dpm_full_context(struct target *target) } while (did_read); - retval = dpm_modeswitch(dpm, ARMV4_5_MODE_ANY); + retval = dpm_modeswitch(dpm, ARM_MODE_ANY); /* (void) */ dpm->finish(dpm); done: return retval; } + +/*----------------------------------------------------------------------*/ + +/* + * Breakpoint and Watchpoint support. + * + * Hardware {break,watch}points are usually left active, to minimize + * debug entry/exit costs. When they are set or cleared, it's done in + * batches. Also, DPM-conformant hardware can update debug registers + * regardless of whether the CPU is running or halted ... though that + * fact isn't currently leveraged. + */ + +static int dpm_bpwp_setup(struct arm_dpm *dpm, struct dpm_bpwp *xp, + uint32_t addr, uint32_t length) +{ + uint32_t control; + + control = (1 << 0) /* enable */ + | (3 << 1); /* both user and privileged access */ + + /* Match 1, 2, or all 4 byte addresses in this word. + * + * FIXME: v7 hardware allows lengths up to 2 GB for BP and WP. + * Support larger length, when addr is suitably aligned. In + * particular, allow watchpoints on 8 byte "double" values. + * + * REVISIT allow watchpoints on unaligned 2-bit values; and on + * v7 hardware, unaligned 4-byte ones too. + */ + switch (length) { + case 1: + control |= (1 << (addr & 3)) << 5; + break; + case 2: + /* require 2-byte alignment */ + if (!(addr & 1)) { + control |= (3 << (addr & 2)) << 5; + break; + } + /* FALL THROUGH */ + case 4: + /* require 4-byte alignment */ + if (!(addr & 3)) { + control |= 0xf << 5; + break; + } + /* FALL THROUGH */ + default: + LOG_ERROR("unsupported {break,watch}point length/alignment"); + return ERROR_INVALID_ARGUMENTS; + } + + /* other shared control bits: + * bits 15:14 == 0 ... both secure and nonsecure states (v6.1+ only) + * bit 20 == 0 ... not linked to a context ID + * bit 28:24 == 0 ... not ignoring N LSBs (v7 only) + */ + + xp->address = addr & ~3; + xp->control = control; + xp->dirty = true; + + LOG_DEBUG("BPWP: addr %8.8x, control %x, number %d", + xp->address, control, xp->number); + + /* hardware is updated in write_dirty_registers() */ + return ERROR_OK; +} + +static int dpm_add_breakpoint(struct target *target, struct breakpoint *bp) +{ + struct arm *arm = target_to_arm(target); + struct arm_dpm *dpm = arm->dpm; + int retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + + if (bp->length < 2) + return ERROR_INVALID_ARGUMENTS; + if (!dpm->bpwp_enable) + return retval; + + /* FIXME we need a generic solution for software breakpoints. */ + if (bp->type == BKPT_SOFT) + LOG_DEBUG("using HW bkpt, not SW..."); + + for (unsigned i = 0; i < dpm->nbp; i++) { + if (!dpm->dbp[i].bp) { + retval = dpm_bpwp_setup(dpm, &dpm->dbp[i].bpwp, + bp->address, bp->length); + if (retval == ERROR_OK) + dpm->dbp[i].bp = bp; + break; + } + } + + return retval; +} + +static int dpm_remove_breakpoint(struct target *target, struct breakpoint *bp) +{ + struct arm *arm = target_to_arm(target); + struct arm_dpm *dpm = arm->dpm; + int retval = ERROR_INVALID_ARGUMENTS; + + for (unsigned i = 0; i < dpm->nbp; i++) { + if (dpm->dbp[i].bp == bp) { + dpm->dbp[i].bp = NULL; + dpm->dbp[i].bpwp.dirty = true; + + /* hardware is updated in write_dirty_registers() */ + retval = ERROR_OK; + break; + } + } + + return retval; +} + +static int dpm_watchpoint_setup(struct arm_dpm *dpm, unsigned index, + struct watchpoint *wp) +{ + int retval; + struct dpm_wp *dwp = dpm->dwp + index; + uint32_t control; + + /* this hardware doesn't support data value matching or masking */ + if (wp->value || wp->mask != ~(uint32_t)0) { + LOG_DEBUG("watchpoint values and masking not supported"); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + } + + retval = dpm_bpwp_setup(dpm, &dwp->bpwp, wp->address, wp->length); + if (retval != ERROR_OK) + return retval; + + control = dwp->bpwp.control; + switch (wp->rw) { + case WPT_READ: + control |= 1 << 3; + break; + case WPT_WRITE: + control |= 2 << 3; + break; + case WPT_ACCESS: + control |= 3 << 3; + break; + } + dwp->bpwp.control = control; + + dpm->dwp[index].wp = wp; + + return retval; +} + +static int dpm_add_watchpoint(struct target *target, struct watchpoint *wp) +{ + struct arm *arm = target_to_arm(target); + struct arm_dpm *dpm = arm->dpm; + int retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + + if (dpm->bpwp_enable) { + for (unsigned i = 0; i < dpm->nwp; i++) { + if (!dpm->dwp[i].wp) { + retval = dpm_watchpoint_setup(dpm, i, wp); + break; + } + } + } + + return retval; +} + +static int dpm_remove_watchpoint(struct target *target, struct watchpoint *wp) +{ + struct arm *arm = target_to_arm(target); + struct arm_dpm *dpm = arm->dpm; + int retval = ERROR_INVALID_ARGUMENTS; + + for (unsigned i = 0; i < dpm->nwp; i++) { + if (dpm->dwp[i].wp == wp) { + dpm->dwp[i].wp = NULL; + dpm->dwp[i].bpwp.dirty = true; + + /* hardware is updated in write_dirty_registers() */ + retval = ERROR_OK; + break; + } + } + + return retval; +} + +void arm_dpm_report_wfar(struct arm_dpm *dpm, uint32_t addr) +{ + switch (dpm->arm->core_state) { + case ARM_STATE_ARM: + addr -= 8; + break; + case ARM_STATE_THUMB: + case ARM_STATE_THUMB_EE: + addr -= 4; + break; + case ARM_STATE_JAZELLE: + /* ?? */ + break; + } + dpm->wp_pc = addr; +} + +/*----------------------------------------------------------------------*/ + +/* + * Other debug and support utilities + */ + +void arm_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dscr) +{ + struct target *target = dpm->arm->target; + + dpm->dscr = dscr; + + /* Examine debug reason */ + switch (DSCR_ENTRY(dscr)) { + case 6: /* Data abort (v6 only) */ + case 7: /* Prefetch abort (v6 only) */ + /* FALL THROUGH -- assume a v6 core in abort mode */ + case 0: /* HALT request from debugger */ + case 4: /* EDBGRQ */ + target->debug_reason = DBG_REASON_DBGRQ; + break; + case 1: /* HW breakpoint */ + case 3: /* SW BKPT */ + case 5: /* vector catch */ + target->debug_reason = DBG_REASON_BREAKPOINT; + break; + case 2: /* asynch watchpoint */ + case 10: /* precise watchpoint */ + target->debug_reason = DBG_REASON_WATCHPOINT; + break; + default: + target->debug_reason = DBG_REASON_UNDEFINED; + break; + } +} + +/*----------------------------------------------------------------------*/ + +/* + * Setup and management support. + */ + /** * Hooks up this DPM to its associated target; call only once. * Initially this only covers the register cache. + * + * Oh, and watchpoints. Yeah. */ int arm_dpm_setup(struct arm_dpm *dpm) { @@ -506,15 +920,52 @@ int arm_dpm_setup(struct arm_dpm *dpm) arm->dpm = dpm; + /* register access setup */ arm->full_context = arm_dpm_full_context; arm->read_core_reg = arm_dpm_read_core_reg; arm->write_core_reg = arm_dpm_write_core_reg; - cache = armv4_5_build_reg_cache(target, arm); + cache = arm_build_reg_cache(target, arm); if (!cache) return ERROR_FAIL; *register_get_last_cache_p(&target->reg_cache) = cache; + + /* coprocessor access setup */ + arm->mrc = dpm_mrc; + arm->mcr = dpm_mcr; + + /* breakpoint setup -- optional until it works everywhere */ + if (!target->type->add_breakpoint) { + target->type->add_breakpoint = dpm_add_breakpoint; + target->type->remove_breakpoint = dpm_remove_breakpoint; + } + + /* watchpoint setup */ + target->type->add_watchpoint = dpm_add_watchpoint; + target->type->remove_watchpoint = dpm_remove_watchpoint; + + /* FIXME add vector catch support */ + + dpm->nbp = 1 + ((dpm->didr >> 24) & 0xf); + dpm->dbp = calloc(dpm->nbp, sizeof *dpm->dbp); + + dpm->nwp = 1 + ((dpm->didr >> 28) & 0xf); + dpm->dwp = calloc(dpm->nwp, sizeof *dpm->dwp); + + if (!dpm->dbp || !dpm->dwp) { + free(dpm->dbp); + free(dpm->dwp); + return ERROR_FAIL; + } + + LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints", + target_name(target), dpm->nbp, dpm->nwp); + + /* REVISIT ... and some of those breakpoints could match + * execution context IDs... + */ + return ERROR_OK; } @@ -524,6 +975,21 @@ int arm_dpm_setup(struct arm_dpm *dpm) */ int arm_dpm_initialize(struct arm_dpm *dpm) { - /* FIXME -- nothing yet */ + /* Disable all breakpoints and watchpoints at startup. */ + if (dpm->bpwp_disable) { + unsigned i; + + for (i = 0; i < dpm->nbp; i++) { + dpm->dbp[i].bpwp.number = i; + (void) dpm->bpwp_disable(dpm, i); + } + for (i = 0; i < dpm->nwp; i++) { + dpm->dwp[i].bpwp.number = 16 + i; + (void) dpm->bpwp_disable(dpm, 16 + i); + } + } else + LOG_WARNING("%s: can't disable breakpoints and watchpoints", + target_name(dpm->arm->target)); + return ERROR_OK; }