X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm_disassembler.h;h=b73f24a8914cc23b87e6243358fe3b2945df0928;hp=d0fcabd863169886ff82bec582eac6487dab7b64;hb=c26bbf7a1b2a11e9cc369536332bff2faa223da8;hpb=53d1f9b2ca5718e4996e9cf3406f857d0ed26df2 diff --git a/src/target/arm_disassembler.h b/src/target/arm_disassembler.h index d0fcabd863..b73f24a891 100644 --- a/src/target/arm_disassembler.h +++ b/src/target/arm_disassembler.h @@ -13,25 +13,21 @@ * GNU General Public License for more details. * * * * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * + * along with this program. If not, see . * ***************************************************************************/ -#ifndef ARM_DISASSEMBLER_H -#define ARM_DISASSEMBLER_H -#include "types.h" +#ifndef OPENOCD_TARGET_ARM_DISASSEMBLER_H +#define OPENOCD_TARGET_ARM_DISASSEMBLER_H -enum arm_instruction_type -{ +enum arm_instruction_type { ARM_UNKNOWN_INSTUCTION, - + /* Branch instructions */ ARM_B, ARM_BL, ARM_BX, ARM_BLX, - + /* Data processing instructions */ ARM_AND, ARM_EOR, @@ -49,32 +45,32 @@ enum arm_instruction_type ARM_MOV, ARM_BIC, ARM_MVN, - + /* Load/store instructions */ ARM_LDR, ARM_LDRB, ARM_LDRT, ARM_LDRBT, - + ARM_LDRH, ARM_LDRSB, ARM_LDRSH, - + ARM_LDM, ARM_STR, ARM_STRB, ARM_STRT, ARM_STRBT, - + ARM_STRH, - + ARM_STM, - + /* Status register access instructions */ ARM_MRS, ARM_MSR, - + /* Multiply instructions */ ARM_MUL, ARM_MLA, @@ -82,29 +78,35 @@ enum arm_instruction_type ARM_SMLAL, ARM_UMULL, ARM_UMLAL, - + /* Miscellaneous instructions */ ARM_CLZ, - + + /* Exception return instructions */ + ARM_ERET, + /* Exception generating instructions */ ARM_BKPT, ARM_SWI, - + ARM_HVC, + ARM_SMC, + /* Coprocessor instructions */ ARM_CDP, ARM_LDC, ARM_STC, ARM_MCR, ARM_MRC, - + /* Semaphore instructions */ ARM_SWP, ARM_SWPB, - + /* Enhanced DSP extensions */ ARM_MCRR, ARM_MRRC, ARM_PLD, + ARM_DSB, ARM_QADD, ARM_QDADD, ARM_QSUB, @@ -120,84 +122,84 @@ enum arm_instruction_type ARM_UNDEFINED_INSTRUCTION = 0xffffffff, }; -typedef struct arm_b_bl_bx_blx_instr_s -{ +struct arm_b_bl_bx_blx_instr { int reg_operand; - u32 target_address; -} arm_b_bl_bx_blx_instr_t; + uint32_t target_address; +}; -union arm_shifter_operand -{ +union arm_shifter_operand { struct { - u32 immediate; + uint32_t immediate; } immediate; struct { - u8 Rm; - u8 shift; /* 0: LSL, 1: LSR, 2: ASR, 3: ROR, 4: RRX */ - u8 shift_imm; + uint8_t Rm; + uint8_t shift; /* 0: LSL, 1: LSR, 2: ASR, 3: ROR, 4: RRX */ + uint8_t shift_imm; } immediate_shift; struct { - u8 Rm; - u8 shift; - u8 Rs; + uint8_t Rm; + uint8_t shift; + uint8_t Rs; } register_shift; }; -typedef struct arm_data_proc_instr_s -{ +struct arm_data_proc_instr { int variant; /* 0: immediate, 1: immediate_shift, 2: register_shift */ - u8 S; - u8 Rn; - u8 Rd; + uint8_t S; + uint8_t Rn; + uint8_t Rd; union arm_shifter_operand shifter_operand; -} arm_data_proc_instr_t; +}; -typedef struct arm_load_store_instr_s -{ - u8 Rd; - u8 Rn; - u8 U; +struct arm_load_store_instr { + uint8_t Rd; + uint8_t Rn; + uint8_t U; int index_mode; /* 0: offset, 1: pre-indexed, 2: post-indexed */ int offset_mode; /* 0: immediate, 1: (scaled) register */ - union - { - u32 offset; + union { + uint32_t offset; struct { - u8 Rm; - u8 shift; /* 0: LSL, 1: LSR, 2: ASR, 3: ROR, 4: RRX */ - u8 shift_imm; + uint8_t Rm; + uint8_t shift; /* 0: LSL, 1: LSR, 2: ASR, 3: ROR, 4: RRX */ + uint8_t shift_imm; } reg; } offset; -} arm_load_store_instr_t; - -typedef struct arm_load_store_multiple_instr_s -{ - u8 Rn; - u32 register_list; - u8 addressing_mode; /* 0: IA, 1: IB, 2: DA, 3: DB */ - u8 S; - u8 W; -} arm_load_store_multiple_instr_t; - -typedef struct arm_instruction_s -{ +}; + +struct arm_load_store_multiple_instr { + uint8_t Rn; + uint32_t register_list; + uint8_t addressing_mode; /* 0: IA, 1: IB, 2: DA, 3: DB */ + uint8_t S; + uint8_t W; +}; + +struct arm_instruction { enum arm_instruction_type type; char text[128]; - u32 opcode; - + uint32_t opcode; + + /* return value ... Thumb-2 sizes vary */ + unsigned instruction_size; + union { - arm_b_bl_bx_blx_instr_t b_bl_bx_blx; - arm_data_proc_instr_t data_proc; - arm_load_store_instr_t load_store; - arm_load_store_multiple_instr_t load_store_multiple; + struct arm_b_bl_bx_blx_instr b_bl_bx_blx; + struct arm_data_proc_instr data_proc; + struct arm_load_store_instr load_store; + struct arm_load_store_multiple_instr load_store_multiple; } info; -} arm_instruction_t; +}; -extern int arm_evaluate_opcode(u32 opcode, u32 address, arm_instruction_t *instruction); -extern int thumb_evaluate_opcode(u16 opcode, u32 address, arm_instruction_t *instruction); -extern int arm_access_size(arm_instruction_t *instruction); +int arm_evaluate_opcode(uint32_t opcode, uint32_t address, + struct arm_instruction *instruction); +int thumb_evaluate_opcode(uint16_t opcode, uint32_t address, + struct arm_instruction *instruction); +int thumb2_opcode(struct target *target, uint32_t address, + struct arm_instruction *instruction); +int arm_access_size(struct arm_instruction *instruction); -#define COND(opcode) (arm_condition_strings[(opcode & 0xf0000000)>>28]) +#define COND(opcode) (arm_condition_strings[(opcode & 0xf0000000) >> 28]) -#endif /* ARM_DISASSEMBLER_H */ +#endif /* OPENOCD_TARGET_ARM_DISASSEMBLER_H */