X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm_disassembler.h;h=b73f24a8914cc23b87e6243358fe3b2945df0928;hp=22485602ed14486884eaad3a484c94ac7fc7048d;hb=c26bbf7a1b2a11e9cc369536332bff2faa223da8;hpb=d0e763ac7ef6aa17b17bd00ccdfbccfb4eacda69

diff --git a/src/target/arm_disassembler.h b/src/target/arm_disassembler.h
index 22485602ed..b73f24a891 100644
--- a/src/target/arm_disassembler.h
+++ b/src/target/arm_disassembler.h
@@ -16,8 +16,8 @@
  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  ***************************************************************************/
 
-#ifndef ARM_DISASSEMBLER_H
-#define ARM_DISASSEMBLER_H
+#ifndef OPENOCD_TARGET_ARM_DISASSEMBLER_H
+#define OPENOCD_TARGET_ARM_DISASSEMBLER_H
 
 enum arm_instruction_type {
 	ARM_UNKNOWN_INSTUCTION,
@@ -106,6 +106,7 @@ enum arm_instruction_type {
 	ARM_MCRR,
 	ARM_MRRC,
 	ARM_PLD,
+	ARM_DSB,
 	ARM_QADD,
 	ARM_QDADD,
 	ARM_QSUB,
@@ -201,4 +202,4 @@ int arm_access_size(struct arm_instruction *instruction);
 
 #define COND(opcode) (arm_condition_strings[(opcode & 0xf0000000) >> 28])
 
-#endif /* ARM_DISASSEMBLER_H */
+#endif /* OPENOCD_TARGET_ARM_DISASSEMBLER_H */