X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm_disassembler.h;h=6f8f65d448d2d1d0c6ff781337cf846fe2a17e40;hp=e7e3e95a2e05b37a225949b4852bf4e0bfba77d9;hb=5be455a710c57bbbbd49c2d671b42098db7be5dc;hpb=f9e091a2d3841d4b5e2f49f3b4337261974b2f2c

diff --git a/src/target/arm_disassembler.h b/src/target/arm_disassembler.h
index e7e3e95a2e..6f8f65d448 100644
--- a/src/target/arm_disassembler.h
+++ b/src/target/arm_disassembler.h
@@ -13,17 +13,13 @@
  *   GNU General Public License for more details.                          *
  *                                                                         *
  *   You should have received a copy of the GNU General Public License     *
- *   along with this program; if not, write to the                         *
- *   Free Software Foundation, Inc.,                                       *
- *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
+ *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  ***************************************************************************/
-#ifndef ARM_DISASSEMBLER_H
-#define ARM_DISASSEMBLER_H
 
-#include "types.h"
+#ifndef OPENOCD_TARGET_ARM_DISASSEMBLER_H
+#define OPENOCD_TARGET_ARM_DISASSEMBLER_H
 
-enum arm_instruction_type
-{
+enum arm_instruction_type {
 	ARM_UNKNOWN_INSTUCTION,
 
 	/* Branch instructions */
@@ -86,9 +82,14 @@ enum arm_instruction_type
 	/* Miscellaneous instructions */
 	ARM_CLZ,
 
+	/* Exception return instructions */
+	ARM_ERET,
+
 	/* Exception generating instructions */
 	ARM_BKPT,
 	ARM_SWI,
+	ARM_HVC,
+	ARM_SMC,
 
 	/* Coprocessor instructions */
 	ARM_CDP,
@@ -120,14 +121,12 @@ enum arm_instruction_type
 	ARM_UNDEFINED_INSTRUCTION = 0xffffffff,
 };
 
-struct arm_b_bl_bx_blx_instr
-{
+struct arm_b_bl_bx_blx_instr {
 	int reg_operand;
 	uint32_t target_address;
 };
 
-union arm_shifter_operand
-{
+union arm_shifter_operand {
 	struct {
 		uint32_t immediate;
 	} immediate;
@@ -143,8 +142,7 @@ union arm_shifter_operand
 	} register_shift;
 };
 
-struct arm_data_proc_instr
-{
+struct arm_data_proc_instr {
 	int variant; /* 0: immediate, 1: immediate_shift, 2: register_shift */
 	uint8_t S;
 	uint8_t Rn;
@@ -152,15 +150,13 @@ struct arm_data_proc_instr
 	union arm_shifter_operand shifter_operand;
 };
 
-typedef struct arm_load_store_instr_s
-{
+struct arm_load_store_instr {
 	uint8_t Rd;
 	uint8_t Rn;
 	uint8_t U;
 	int index_mode; /* 0: offset, 1: pre-indexed, 2: post-indexed */
 	int offset_mode; /* 0: immediate, 1: (scaled) register */
-	union
-	{
+	union {
 		uint32_t offset;
 		struct {
 			uint8_t Rm;
@@ -168,19 +164,17 @@ typedef struct arm_load_store_instr_s
 			uint8_t shift_imm;
 		} reg;
 	} offset;
-} arm_load_store_instr_t;
+};
 
-typedef struct arm_load_store_multiple_instr_s
-{
+struct arm_load_store_multiple_instr {
 	uint8_t Rn;
 	uint32_t register_list;
 	uint8_t addressing_mode; /* 0: IA, 1: IB, 2: DA, 3: DB */
 	uint8_t S;
 	uint8_t W;
-} arm_load_store_multiple_instr_t;
+};
 
-typedef struct arm_instruction_s
-{
+struct arm_instruction {
 	enum arm_instruction_type type;
 	char text[128];
 	uint32_t opcode;
@@ -191,20 +185,20 @@ typedef struct arm_instruction_s
 	union {
 		struct arm_b_bl_bx_blx_instr b_bl_bx_blx;
 		struct arm_data_proc_instr data_proc;
-		arm_load_store_instr_t load_store;
-		arm_load_store_multiple_instr_t load_store_multiple;
+		struct arm_load_store_instr load_store;
+		struct arm_load_store_multiple_instr load_store_multiple;
 	} info;
 
-} arm_instruction_t;
+};
 
 int arm_evaluate_opcode(uint32_t opcode, uint32_t address,
-		arm_instruction_t *instruction);
+		struct arm_instruction *instruction);
 int thumb_evaluate_opcode(uint16_t opcode, uint32_t address,
-		arm_instruction_t *instruction);
-int thumb2_opcode(target_t *target, uint32_t address,
-		arm_instruction_t *instruction);
-int arm_access_size(arm_instruction_t *instruction);
+		struct arm_instruction *instruction);
+int thumb2_opcode(struct target *target, uint32_t address,
+		struct arm_instruction *instruction);
+int arm_access_size(struct arm_instruction *instruction);
 
 #define COND(opcode) (arm_condition_strings[(opcode & 0xf0000000) >> 28])
 
-#endif /* ARM_DISASSEMBLER_H */
+#endif /* OPENOCD_TARGET_ARM_DISASSEMBLER_H */