X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm_disassembler.h;h=52fe24a01fbdaeea0e0ab56a5bf445751b18027a;hp=7d914bfd38710cbbd24fc37a6c07f0dd861ddf4c;hb=67f2f8393742bd88017b54ae0cfd833265bb1517;hpb=db7e77237c5a8104b527aeb23a2546b4bab92d8a diff --git a/src/target/arm_disassembler.h b/src/target/arm_disassembler.h index 7d914bfd38..52fe24a01f 100644 --- a/src/target/arm_disassembler.h +++ b/src/target/arm_disassembler.h @@ -25,13 +25,13 @@ enum arm_instruction_type { ARM_UNKNOWN_INSTUCTION, - + /* Branch instructions */ ARM_B, ARM_BL, ARM_BX, ARM_BLX, - + /* Data processing instructions */ ARM_AND, ARM_EOR, @@ -49,32 +49,32 @@ enum arm_instruction_type ARM_MOV, ARM_BIC, ARM_MVN, - + /* Load/store instructions */ ARM_LDR, ARM_LDRB, ARM_LDRT, ARM_LDRBT, - + ARM_LDRH, ARM_LDRSB, ARM_LDRSH, - + ARM_LDM, ARM_STR, ARM_STRB, ARM_STRT, ARM_STRBT, - + ARM_STRH, - + ARM_STM, - + /* Status register access instructions */ ARM_MRS, ARM_MSR, - + /* Multiply instructions */ ARM_MUL, ARM_MLA, @@ -82,25 +82,25 @@ enum arm_instruction_type ARM_SMLAL, ARM_UMULL, ARM_UMLAL, - + /* Miscellaneous instructions */ ARM_CLZ, - + /* Exception generating instructions */ ARM_BKPT, ARM_SWI, - + /* Coprocessor instructions */ ARM_CDP, ARM_LDC, ARM_STC, ARM_MCR, ARM_MRC, - + /* Semaphore instructions */ ARM_SWP, ARM_SWPB, - + /* Enhanced DSP extensions */ ARM_MCRR, ARM_MRRC, @@ -120,11 +120,11 @@ enum arm_instruction_type ARM_UNDEFINED_INSTRUCTION = 0xffffffff, }; -typedef struct arm_b_bl_bx_blx_instr_s +struct arm_b_bl_bx_blx_instr { int reg_operand; uint32_t target_address; -} arm_b_bl_bx_blx_instr_t; +}; union arm_shifter_operand { @@ -184,9 +184,12 @@ typedef struct arm_instruction_s enum arm_instruction_type type; char text[128]; uint32_t opcode; - + + /* return value ... Thumb-2 sizes vary */ + unsigned instruction_size; + union { - arm_b_bl_bx_blx_instr_t b_bl_bx_blx; + struct arm_b_bl_bx_blx_instr b_bl_bx_blx; arm_data_proc_instr_t data_proc; arm_load_store_instr_t load_store; arm_load_store_multiple_instr_t load_store_multiple; @@ -194,10 +197,14 @@ typedef struct arm_instruction_s } arm_instruction_t; -extern int arm_evaluate_opcode(uint32_t opcode, uint32_t address, arm_instruction_t *instruction); -extern int thumb_evaluate_opcode(uint16_t opcode, uint32_t address, arm_instruction_t *instruction); -extern int arm_access_size(arm_instruction_t *instruction); +int arm_evaluate_opcode(uint32_t opcode, uint32_t address, + arm_instruction_t *instruction); +int thumb_evaluate_opcode(uint16_t opcode, uint32_t address, + arm_instruction_t *instruction); +int thumb2_opcode(target_t *target, uint32_t address, + arm_instruction_t *instruction); +int arm_access_size(arm_instruction_t *instruction); -#define COND(opcode) (arm_condition_strings[(opcode & 0xf0000000)>>28]) +#define COND(opcode) (arm_condition_strings[(opcode & 0xf0000000) >> 28]) #endif /* ARM_DISASSEMBLER_H */