X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm_disassembler.c;h=f9e0227af8e952997a6dbad4d50bab738e559b5c;hp=04dcf4bac62d92ee9b20bdc00065cf41398c810b;hb=5ed126c4f90948fbf53d186dc4ef49018fb5ecfc;hpb=1f76f6999974a3a1765aaa96fecc3f2433e7b5b6

diff --git a/src/target/arm_disassembler.c b/src/target/arm_disassembler.c
index 04dcf4bac6..f9e0227af8 100644
--- a/src/target/arm_disassembler.c
+++ b/src/target/arm_disassembler.c
@@ -17,11 +17,15 @@
  *   Free Software Foundation, Inc.,                                       *
  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  ***************************************************************************/
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
 #include "arm_disassembler.h"
 
 #include "log.h"
 
-#include <strings.h>
+#include <string.h>
 
 /* textual represenation of the condition field */
 /* ALways (default) is ommitted (empty string) */
@@ -678,7 +682,7 @@ int evaluate_mul_and_extra_ld_st(u32 opcode, u32 address, arm_instruction_t *ins
 		/* Multiply (accumulate) long */
 		if ((opcode & 0x0f800000) == 0x00800000)
 		{
-			char* mnemonic;
+			char* mnemonic = NULL;
 			u8 Rm, Rs, RdHi, RdLow, S;
 			Rm = opcode & 0xf;
 			Rs = (opcode & 0xf00) >> 8;
@@ -837,7 +841,7 @@ int evaluate_misc_instr(u32 opcode, u32 address, arm_instruction_t *instruction)
 	if ((opcode & 0x0000000f0) == 0x00000050)
 	{
 		u8 Rm, Rd, Rn;
-		char *mnemonic;
+		char *mnemonic = NULL;
 		Rm = opcode & 0xf;
 		Rd = (opcode & 0xf000) >> 12;
 		Rn = (opcode & 0xf0000) >> 16;
@@ -963,7 +967,7 @@ int evaluate_misc_instr(u32 opcode, u32 address, arm_instruction_t *instruction)
 int evaluate_data_proc(u32 opcode, u32 address, arm_instruction_t *instruction)
 {
 	u8 I, op, S, Rn, Rd;
-	char *mnemonic;
+	char *mnemonic = NULL;
 	char shifter_operand[32];
 	
 	I = (opcode & 0x02000000) >> 25;
@@ -1158,7 +1162,7 @@ int evaluate_data_proc(u32 opcode, u32 address, arm_instruction_t *instruction)
 int evaluate_opcode(u32 opcode, u32 address, arm_instruction_t *instruction)
 {
 	/* clear fields, to avoid confusion */
-	bzero(instruction, sizeof(arm_instruction_t));
+	memset(instruction, 0, sizeof(arm_instruction_t));
 	instruction->opcode = opcode;
 	
 	/* catch opcodes with condition field [31:28] = b1111 */
@@ -1243,7 +1247,7 @@ int evaluate_opcode(u32 opcode, u32 address, arm_instruction_t *instruction)
 	}
 	
 	/* catch opcodes with [27:25] = b011 */
-	if ((opcode & 0x0e000000) == 0x04000000)
+	if ((opcode & 0x0e000000) == 0x06000000)
 	{
 		/* Undefined instruction */
 		if ((opcode & 0x00000010) == 0x00000010)