X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm_disassembler.c;h=2e87bb3c37f71d827eb1c601d6a34bd116739ca4;hp=1c275f54645a897e70c4cbede7f8806264838e94;hb=a28eaa85f73759bb189a46308642502c9fa5aa4b;hpb=237e894805dd757cc24029af1b4b1e824c51712b

diff --git a/src/target/arm_disassembler.c b/src/target/arm_disassembler.c
index 1c275f5464..2e87bb3c37 100644
--- a/src/target/arm_disassembler.c
+++ b/src/target/arm_disassembler.c
@@ -57,7 +57,7 @@ int evaluate_pld(u32 opcode, u32 address, arm_instruction_t *instruction)
 		return ERROR_OK;
 	}
 	
-	ERROR("should never reach this point");
+	LOG_ERROR("should never reach this point");
 	return -1;
 }
 
@@ -346,7 +346,7 @@ int evaluate_load_store(u32 opcode, u32 address, arm_instruction_t *instruction)
 		if (offset_12)
 			snprintf(offset, 32, ", #%s0x%x", (U) ? "" : "-", offset_12);
 		else
-			snprintf(offset, 32, "");
+			snprintf(offset, 32, "%s", "");
 		
 		instruction->info.load_store.offset_mode = 0;
 		instruction->info.load_store.offset.offset = offset_12;
@@ -1317,7 +1317,7 @@ int arm_evaluate_opcode(u32 opcode, u32 address, arm_instruction_t *instruction)
 			return evaluate_cdp_mcr_mrc(opcode, address, instruction);
 	}
 	
-	ERROR("should never reach this point");
+	LOG_ERROR("should never reach this point");
 	return -1;
 }
 
@@ -2076,7 +2076,41 @@ int thumb_evaluate_opcode(u16 opcode, u32 address, arm_instruction_t *instructio
 		}
 	}
 
-	ERROR("should never reach this point (opcode=%04x)",opcode);
+	LOG_ERROR("should never reach this point (opcode=%04x)",opcode);
 	return -1;
 }
 
+int arm_access_size(arm_instruction_t *instruction)
+{
+	if ((instruction->type == ARM_LDRB)
+		|| (instruction->type == ARM_LDRBT)
+		|| (instruction->type == ARM_LDRSB)
+		|| (instruction->type == ARM_STRB)
+		|| (instruction->type == ARM_STRBT))
+	{
+		return 1;
+	}
+	else if ((instruction->type == ARM_LDRH)
+		|| (instruction->type == ARM_LDRSH)
+		|| (instruction->type == ARM_STRH))
+	{
+		return 2;
+	}
+	else if ((instruction->type == ARM_LDR)
+		|| (instruction->type == ARM_LDRT)
+		|| (instruction->type == ARM_STR)
+		|| (instruction->type == ARM_STRT))
+	{
+		return 4;
+	}
+	else if ((instruction->type == ARM_LDRD)
+		|| (instruction->type == ARM_STRD))
+	{
+		return 8;
+	}
+	else
+	{
+		LOG_ERROR("BUG: instruction type %i isn't a load/store instruction", instruction->type);
+		return 0;
+	}
+}