X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm_adi_v5.h;h=13ced9f7ca78f1c5a5d21bfb7fbc1ae87cb9434f;hp=faf725fca816c52c19d2e9f0569ef6eca186f245;hb=150b7d26f213398d717bf46744811b48834a3744;hpb=c6ce183055acebcc1c5ef004f2f6f4a4042700dd diff --git a/src/target/arm_adi_v5.h b/src/target/arm_adi_v5.h index faf725fca8..13ced9f7ca 100644 --- a/src/target/arm_adi_v5.h +++ b/src/target/arm_adi_v5.h @@ -31,14 +31,9 @@ * resources accessed through a MEM-AP. */ +#include #include "arm_jtag.h" -/* FIXME remove these JTAG-specific decls when mem_ap_read_buf_u32() - * is no longer JTAG-specific - */ -#define JTAG_DP_DPACC 0xA -#define JTAG_DP_APACC 0xB - /* three-bit ACK values for SWD access (sent LSB first) */ #define SWD_ACK_OK 0x1 #define SWD_ACK_WAIT 0x2 @@ -52,18 +47,21 @@ /* A[3:0] for DP registers; A[1:0] are always zero. * - JTAG accesses all of these via JTAG_DP_DPACC, except for * IDCODE (JTAG_DP_IDCODE) and ABORT (JTAG_DP_ABORT). - * - SWD accesses these directly, sometimes needing SELECT.CTRLSEL + * - SWD accesses these directly, sometimes needing SELECT.DPBANKSEL */ -#define DP_IDCODE BANK_REG(0x0, 0x0) /* SWD: read */ -#define DP_ABORT BANK_REG(0x0, 0x0) /* SWD: write */ -#define DP_CTRL_STAT BANK_REG(0x0, 0x4) /* r/w */ -#define DP_RESEND BANK_REG(0x0, 0x8) /* SWD: read */ -#define DP_SELECT BANK_REG(0x0, 0x8) /* JTAG: r/w; SWD: write */ -#define DP_RDBUFF BANK_REG(0x0, 0xC) /* read-only */ -#define DP_WCR BANK_REG(0x1, 0x4) /* SWD: r/w */ - -#define WCR_TO_TRN(wcr) ((uint32_t)(1 + (3 & ((wcr)) >> 8))) /* 1..4 clocks */ -#define WCR_TO_PRESCALE(wcr) ((uint32_t)(7 & ((wcr)))) /* impl defined */ +#define DP_DPIDR BANK_REG(0x0, 0x0) /* DPv1+: ro */ +#define DP_ABORT BANK_REG(0x0, 0x0) /* DPv1+: SWD: wo */ +#define DP_CTRL_STAT BANK_REG(0x0, 0x4) /* DPv0+: rw */ +#define DP_DLCR BANK_REG(0x1, 0x4) /* DPv1+: SWD: rw */ +#define DP_TARGETID BANK_REG(0x2, 0x4) /* DPv2: ro */ +#define DP_DLPIDR BANK_REG(0x3, 0x4) /* DPv2: ro */ +#define DP_EVENTSTAT BANK_REG(0x4, 0x4) /* DPv2: ro */ +#define DP_RESEND BANK_REG(0x0, 0x8) /* DPv1+: SWD: ro */ +#define DP_SELECT BANK_REG(0x0, 0x8) /* DPv0+: JTAG: rw; SWD: wo */ +#define DP_RDBUFF BANK_REG(0x0, 0xC) /* DPv0+: ro */ +#define DP_TARGETSEL BANK_REG(0x0, 0xC) /* DPv2: SWD: wo */ + +#define DLCR_TO_TRN(dlcr) ((uint32_t)(1 + ((3 & (dlcr)) >> 8))) /* 1..4 clocks */ /* Fields of the DP's AP ABORT register */ #define DAPABORT (1UL << 0) @@ -131,6 +129,11 @@ #define IDR_JEP106_ARM 0x04760000 +#define DP_SELECT_APSEL 0xFF000000 +#define DP_SELECT_APBANK 0x000000F0 +#define DP_SELECT_DPBANK 0x0000000F +#define DP_SELECT_INVALID 0x00FFFF00 /* Reserved bits one */ + /** * This represents an ARM Debug Interface (v5) Access Port (AP). * Most common is a MEM-AP, for memory access. @@ -201,6 +204,9 @@ struct adiv5_ap { struct adiv5_dap { const struct dap_ops *ops; + /* dap transaction list for WAIT support */ + struct list_head cmd_journal; + struct jtag_tap *tap; /* Control config */ uint32_t dp_ctrl_stat; @@ -211,27 +217,10 @@ struct adiv5_dap { uint32_t apsel; /** - * Cache for DP_SELECT bits identifying the current AP. A DAP may - * connect to multiple APs, such as one MEM-AP for general access, - * another reserved for accessing debug modules, and a JTAG-DP. - * "-1" indicates no cached value. + * Cache for DP_SELECT register. A value of DP_SELECT_INVALID + * indicates no cached value and forces rewrite of the register. */ - uint32_t ap_current; - - /** - * Cache for DP_SELECT bits identifying the current four-word AP - * register bank. This caches AP register addresss bits 7:4; JTAG - * and SWD access primitves pass address bits 3:2; bits 1:0 are zero. - * "-1" indicates no cached value. - */ - uint32_t ap_bank_value; - - /** - * Cache for DP_SELECT bits identifying the current four-word DP - * register bank. This caches DP register addresss bits 7:4; JTAG - * and SWD access primitves pass address bits 3:2; bits 1:0 are zero. - */ - uint32_t dp_bank_value; + uint32_t select; /* information about current pending SWjDP-AHBAP transaction */ uint8_t ack; @@ -271,10 +260,10 @@ struct dap_ops { uint32_t data); /** AP register read. */ - int (*queue_ap_read)(struct adiv5_dap *dap, unsigned reg, + int (*queue_ap_read)(struct adiv5_ap *ap, unsigned reg, uint32_t *data); /** AP register write. */ - int (*queue_ap_write)(struct adiv5_dap *dap, unsigned reg, + int (*queue_ap_write)(struct adiv5_ap *ap, unsigned reg, uint32_t data); /** AP operation abort. */ @@ -282,6 +271,10 @@ struct dap_ops { /** Executes all queued DAP operations. */ int (*run)(struct adiv5_dap *dap); + + /** Executes all queued DAP operations but doesn't check + * sticky error conditions */ + int (*sync)(struct adiv5_dap *dap); }; /* @@ -342,34 +335,34 @@ static inline int dap_queue_dp_write(struct adiv5_dap *dap, /** * Queue an AP register read. * - * @param dap The DAP used for reading. + * @param ap The AP used for reading. * @param reg The number of the AP register being read. * @param data Pointer saying where to store the register's value * (in host endianness). * * @return ERROR_OK for success, else a fault code. */ -static inline int dap_queue_ap_read(struct adiv5_dap *dap, +static inline int dap_queue_ap_read(struct adiv5_ap *ap, unsigned reg, uint32_t *data) { - assert(dap->ops != NULL); - return dap->ops->queue_ap_read(dap, reg, data); + assert(ap->dap->ops != NULL); + return ap->dap->ops->queue_ap_read(ap, reg, data); } /** * Queue an AP register write. * - * @param dap The DAP used for writing. + * @param ap The AP used for writing. * @param reg The number of the AP register being written. * @param data Value being written (host endianness) * * @return ERROR_OK for success, else a fault code. */ -static inline int dap_queue_ap_write(struct adiv5_dap *dap, +static inline int dap_queue_ap_write(struct adiv5_ap *ap, unsigned reg, uint32_t data) { - assert(dap->ops != NULL); - return dap->ops->queue_ap_write(dap, reg, data); + assert(ap->dap->ops != NULL); + return ap->dap->ops->queue_ap_write(ap, reg, data); } /** @@ -405,6 +398,14 @@ static inline int dap_run(struct adiv5_dap *dap) return dap->ops->run(dap); } +static inline int dap_sync(struct adiv5_dap *dap) +{ + assert(dap->ops != NULL); + if (dap->ops->sync) + return dap->ops->sync(dap); + return ERROR_OK; +} + static inline int dap_dp_read_atomic(struct adiv5_dap *dap, unsigned reg, uint32_t *value) { @@ -446,49 +447,36 @@ static inline int dap_dp_poll_register(struct adiv5_dap *dap, unsigned reg, } } -/** Accessor for currently selected DAP-AP number (0..255) */ -static inline uint8_t dap_ap_get_select(struct adiv5_dap *swjdp) -{ - return (uint8_t)(swjdp->ap_current >> 24); -} - -/* AP selection applies to future AP transactions */ -void dap_ap_select(struct adiv5_dap *dap, uint8_t ap); - -/* Queued AP transactions */ -int dap_setup_accessport(struct adiv5_dap *swjdp, - uint32_t csw, uint32_t tar); - -/* Queued MEM-AP memory mapped single word transfers with selection of ap */ -int mem_ap_sel_read_u32(struct adiv5_ap *ap, +/* Queued MEM-AP memory mapped single word transfers. */ +int mem_ap_read_u32(struct adiv5_ap *ap, uint32_t address, uint32_t *value); -int mem_ap_sel_write_u32(struct adiv5_ap *ap, +int mem_ap_write_u32(struct adiv5_ap *ap, uint32_t address, uint32_t value); -/* Synchronous MEM-AP memory mapped single word transfers with selection of ap */ -int mem_ap_sel_read_atomic_u32(struct adiv5_ap *ap, +/* Synchronous MEM-AP memory mapped single word transfers. */ +int mem_ap_read_atomic_u32(struct adiv5_ap *ap, uint32_t address, uint32_t *value); -int mem_ap_sel_write_atomic_u32(struct adiv5_ap *ap, +int mem_ap_write_atomic_u32(struct adiv5_ap *ap, uint32_t address, uint32_t value); -/* Synchronous MEM-AP memory mapped bus block transfers with selection of ap */ -int mem_ap_sel_read_buf(struct adiv5_ap *ap, +/* Synchronous MEM-AP memory mapped bus block transfers. */ +int mem_ap_read_buf(struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address); -int mem_ap_sel_write_buf(struct adiv5_ap *ap, +int mem_ap_write_buf(struct adiv5_ap *ap, const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address); -/* Synchronous, non-incrementing buffer functions for accessing fifos, with - * selection of ap */ -int mem_ap_sel_read_buf_noincr(struct adiv5_ap *ap, +/* Synchronous, non-incrementing buffer functions for accessing fifos. */ +int mem_ap_read_buf_noincr(struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address); -int mem_ap_sel_write_buf_noincr(struct adiv5_ap *ap, +int mem_ap_write_buf_noincr(struct adiv5_ap *ap, const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address); /* Create DAP struct */ struct adiv5_dap *dap_init(void); /* Initialisation of the debug system, power domains and registers */ -int ahbap_debugport_init(struct adiv5_ap *ap); +int dap_dp_init(struct adiv5_dap *dap); +int mem_ap_init(struct adiv5_ap *ap); /* Probe the AP for ROM Table location */ int dap_get_debugbase(struct adiv5_ap *ap, @@ -499,6 +487,11 @@ int dap_find_ap(struct adiv5_dap *dap, enum ap_type type_to_find, struct adiv5_ap **ap_out); +static inline struct adiv5_ap *dap_ap(struct adiv5_dap *dap, uint8_t ap_num) +{ + return &dap->ap[ap_num]; +} + /* Lookup CoreSight component */ int dap_lookup_cs_component(struct adiv5_ap *ap, uint32_t dbgbase, uint8_t type, uint32_t *addr, int32_t *idx);