X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm_adi_v5.c;h=bf95057ff9839b1a98103d360b9b79dcc58f7069;hp=9ac6669915ba51b2ba64a54990e706b7da37f501;hb=dc575dc5bf8cb597a0e9a47794744ae6b1928087;hpb=333642fcff9901a8f20c02457756ca9715641139 diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c index 9ac6669915..bf95057ff9 100644 --- a/src/target/arm_adi_v5.c +++ b/src/target/arm_adi_v5.c @@ -81,7 +81,7 @@ int adi_jtag_dp_scan(swjdp_common_t *swjdp, uint8_t instr, uint8_t reg_addr, uin arm_jtag_set_instr(jtag_info, instr, NULL); /* Add specified number of tck clocks before accessing memory bus */ - if ((instr == DAP_IR_APACC) && ((reg_addr == AP_REG_DRW)||((reg_addr&0xF0) == AP_REG_BD0) )&& (swjdp->memaccess_tck != 0)) + if ((instr == DAP_IR_APACC) && ((reg_addr == AP_REG_DRW)||((reg_addr&0xF0) == AP_REG_BD0))&& (swjdp->memaccess_tck != 0)) jtag_add_runtest(swjdp->memaccess_tck, jtag_set_end_state(TAP_IDLE)); fields[0].tap = jtag_info->tap; @@ -112,7 +112,7 @@ int adi_jtag_dp_scan_u32(swjdp_common_t *swjdp, uint8_t instr, uint8_t reg_addr, arm_jtag_set_instr(jtag_info, instr, NULL); /* Add specified number of tck clocks before accessing memory bus */ - if ((instr == DAP_IR_APACC) && ((reg_addr == AP_REG_DRW)||((reg_addr&0xF0) == AP_REG_BD0) )&& (swjdp->memaccess_tck != 0)) + if ((instr == DAP_IR_APACC) && ((reg_addr == AP_REG_DRW)||((reg_addr&0xF0) == AP_REG_BD0))&& (swjdp->memaccess_tck != 0)) jtag_add_runtest(swjdp->memaccess_tck, jtag_set_end_state(TAP_IDLE)); fields[0].tap = jtag_info->tap; @@ -152,7 +152,7 @@ int scan_inout_check(swjdp_common_t *swjdp, uint8_t instr, uint8_t reg_addr, uin adi_jtag_dp_scan(swjdp, DAP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack); } - /* In TRANS_MODE_ATOMIC all DAP_IR_APACC transactions wait for ack=OK/FAULT and the check CTRL_STAT */ + /* In TRANS_MODE_ATOMIC all DAP_IR_APACC transactions wait for ack = OK/FAULT and the check CTRL_STAT */ if ((instr == DAP_IR_APACC) && (swjdp->trans_mode == TRANS_MODE_ATOMIC)) { return swjdp_transaction_endcheck(swjdp); @@ -165,12 +165,12 @@ int scan_inout_check_u32(swjdp_common_t *swjdp, uint8_t instr, uint8_t reg_addr, { adi_jtag_dp_scan_u32(swjdp, instr, reg_addr, RnW, outvalue, NULL, NULL); - if ((RnW==DPAP_READ) && (invalue != NULL)) + if ((RnW == DPAP_READ) && (invalue != NULL)) { adi_jtag_dp_scan_u32(swjdp, DAP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack); } - /* In TRANS_MODE_ATOMIC all DAP_IR_APACC transactions wait for ack=OK/FAULT and then check CTRL_STAT */ + /* In TRANS_MODE_ATOMIC all DAP_IR_APACC transactions wait for ack = OK/FAULT and then check CTRL_STAT */ if ((instr == DAP_IR_APACC) && (swjdp->trans_mode == TRANS_MODE_ATOMIC)) { return swjdp_transaction_endcheck(swjdp); @@ -195,7 +195,7 @@ int swjdp_transaction_endcheck(swjdp_common_t *swjdp) https://lists.berlios.de/pipermail/openocd-development/2008-September/003107.html */ - if ((retval=jtag_execute_queue())!=ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) { LOG_ERROR("BUG: Why does this fail the first time????"); } @@ -203,14 +203,14 @@ int swjdp_transaction_endcheck(swjdp_common_t *swjdp) #endif scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat); - if ((retval=jtag_execute_queue())!=ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) return retval; swjdp->ack = swjdp->ack & 0x7; if (swjdp->ack != 2) { - long long then=timeval_ms(); + long long then = timeval_ms(); while (swjdp->ack != 2) { if (swjdp->ack == 1) @@ -228,7 +228,7 @@ int swjdp_transaction_endcheck(swjdp_common_t *swjdp) } scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat); - if ((retval=jtag_execute_queue())!=ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) return retval; swjdp->ack = swjdp->ack & 0x7; } @@ -240,7 +240,7 @@ int swjdp_transaction_endcheck(swjdp_common_t *swjdp) /* Check for STICKYERR and STICKYORUN */ if (ctrlstat & (SSTICKYORUN | SSTICKYERR)) { - LOG_DEBUG("swjdp: CTRL/STAT error 0x%x", ctrlstat); + LOG_DEBUG("swjdp: CTRL/STAT error 0x%" PRIx32 "", ctrlstat); /* Check power to debug regions */ if ((ctrlstat & 0xf0000000) != 0xf0000000) { @@ -251,7 +251,7 @@ int swjdp_transaction_endcheck(swjdp_common_t *swjdp) uint32_t mem_ap_csw, mem_ap_tar; /* Print information about last AHBAP access */ - LOG_ERROR("AHBAP Cached values: dp_select 0x%x, ap_csw 0x%x, ap_tar 0x%x", swjdp->dp_select_value, swjdp->ap_csw_value, swjdp->ap_tar_value); + LOG_ERROR("AHBAP Cached values: dp_select 0x%" PRIx32 ", ap_csw 0x%" PRIx32 ", ap_tar 0x%" PRIx32 "", swjdp->dp_select_value, swjdp->ap_csw_value, swjdp->ap_tar_value); if (ctrlstat & SSTICKYORUN) LOG_ERROR("SWJ-DP OVERRUN - check clock or reduce jtag speed"); @@ -261,19 +261,19 @@ int swjdp_transaction_endcheck(swjdp_common_t *swjdp) /* Clear Sticky Error Bits */ scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_WRITE, swjdp->dp_ctrl_stat | SSTICKYORUN | SSTICKYERR, NULL); scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat); - if ((retval=jtag_execute_queue())!=ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) return retval; - LOG_DEBUG("swjdp: status 0x%x", ctrlstat); + LOG_DEBUG("swjdp: status 0x%" PRIx32 "", ctrlstat); dap_ap_read_reg_u32(swjdp, AP_REG_CSW, &mem_ap_csw); dap_ap_read_reg_u32(swjdp, AP_REG_TAR, &mem_ap_tar); - if ((retval=jtag_execute_queue())!=ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) return retval; - LOG_ERROR("Read MEM_AP_CSW 0x%x, MEM_AP_TAR 0x%x", mem_ap_csw, mem_ap_tar); + LOG_ERROR("Read MEM_AP_CSW 0x%" PRIx32 ", MEM_AP_TAR 0x%" PRIx32 "", mem_ap_csw, mem_ap_tar); } - if ((retval=jtag_execute_queue())!=ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) return retval; return ERROR_JTAG_DEVICE_ERROR; } @@ -300,7 +300,7 @@ int dap_dp_read_reg(swjdp_common_t *swjdp, uint32_t *value, uint8_t reg_addr) int dap_ap_select(swjdp_common_t *swjdp,uint8_t apsel) { uint32_t select; - select = (apsel<<24) & 0xFF000000; + select = (apsel << 24) & 0xFF000000; if (select != swjdp->apsel) { @@ -374,13 +374,13 @@ int dap_setup_accessport(swjdp_common_t *swjdp, uint32_t csw, uint32_t tar) if (csw != swjdp->ap_csw_value) { /* LOG_DEBUG("swjdp : Set CSW %x",csw); */ - dap_ap_write_reg_u32(swjdp, AP_REG_CSW, csw ); + dap_ap_write_reg_u32(swjdp, AP_REG_CSW, csw); swjdp->ap_csw_value = csw; } if (tar != swjdp->ap_tar_value) { /* LOG_DEBUG("swjdp : Set TAR %x",tar); */ - dap_ap_write_reg_u32(swjdp, AP_REG_TAR, tar ); + dap_ap_write_reg_u32(swjdp, AP_REG_TAR, tar); swjdp->ap_tar_value = tar; } if (csw & CSW_ADDRINC_MASK) @@ -404,7 +404,7 @@ int mem_ap_read_u32(swjdp_common_t *swjdp, uint32_t address, uint32_t *value) swjdp->trans_mode = TRANS_MODE_COMPOSITE; dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0); - dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value ); + dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value); return ERROR_OK; } @@ -428,7 +428,7 @@ int mem_ap_write_u32(swjdp_common_t *swjdp, uint32_t address, uint32_t value) swjdp->trans_mode = TRANS_MODE_COMPOSITE; dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0); - dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value ); + dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value); return ERROR_OK; } @@ -467,7 +467,7 @@ int mem_ap_write_buf_u32(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint uint32_t outvalue; memcpy(&outvalue, pBuffer, sizeof(uint32_t)); - for (i = 0; i < 4; i++ ) + for (i = 0; i < 4; i++) { *((uint8_t*)pBuffer + (adr & 0x3)) = outvalue; outvalue >>= 8; @@ -492,7 +492,7 @@ int mem_ap_write_buf_u32(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint for (writecount = 0; writecount < blocksize; writecount++) { - dap_ap_write_reg(swjdp, AP_REG_DRW, buffer + 4 * writecount ); + dap_ap_write_reg(swjdp, AP_REG_DRW, buffer + 4 * writecount); } if (swjdp_transaction_endcheck(swjdp) == ERROR_OK) @@ -508,7 +508,7 @@ int mem_ap_write_buf_u32(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint if (errorcount > 1) { - LOG_WARNING("Block write error address 0x%x, wcount 0x%x", address, wcount); + LOG_WARNING("Block write error address 0x%" PRIx32 ", wcount 0x%x", address, wcount); return ERROR_JTAG_DEVICE_ERROR; } } @@ -546,11 +546,11 @@ int mem_ap_write_buf_packed_u16(swjdp_common_t *swjdp, uint8_t *buffer, int coun { nbytes = MIN((writecount << 1), 4); - if (nbytes < 4 ) + if (nbytes < 4) { if (mem_ap_write_buf_u16(swjdp, buffer, nbytes, address) != ERROR_OK) { - LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count); + LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count); return ERROR_JTAG_DEVICE_ERROR; } @@ -561,7 +561,7 @@ int mem_ap_write_buf_packed_u16(swjdp_common_t *swjdp, uint8_t *buffer, int coun uint32_t outvalue; memcpy(&outvalue, buffer, sizeof(uint32_t)); - for (i = 0; i < nbytes; i++ ) + for (i = 0; i < nbytes; i++) { *((uint8_t*)buffer + (address & 0x3)) = outvalue; outvalue >>= 8; @@ -572,7 +572,7 @@ int mem_ap_write_buf_packed_u16(swjdp_common_t *swjdp, uint8_t *buffer, int coun dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue); if (swjdp_transaction_endcheck(swjdp) != ERROR_OK) { - LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count); + LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count); return ERROR_JTAG_DEVICE_ERROR; } } @@ -602,7 +602,7 @@ int mem_ap_write_buf_u16(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint uint16_t svalue; memcpy(&svalue, buffer, sizeof(uint16_t)); uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3); - dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue ); + dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue); retval = swjdp_transaction_endcheck(swjdp); count -= 2; address += 2; @@ -638,11 +638,11 @@ int mem_ap_write_buf_packed_u8(swjdp_common_t *swjdp, uint8_t *buffer, int count { nbytes = MIN(writecount, 4); - if (nbytes < 4 ) + if (nbytes < 4) { if (mem_ap_write_buf_u8(swjdp, buffer, nbytes, address) != ERROR_OK) { - LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count); + LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count); return ERROR_JTAG_DEVICE_ERROR; } @@ -653,7 +653,7 @@ int mem_ap_write_buf_packed_u8(swjdp_common_t *swjdp, uint8_t *buffer, int count uint32_t outvalue; memcpy(&outvalue, buffer, sizeof(uint32_t)); - for (i = 0; i < nbytes; i++ ) + for (i = 0; i < nbytes; i++) { *((uint8_t*)buffer + (address & 0x3)) = outvalue; outvalue >>= 8; @@ -664,7 +664,7 @@ int mem_ap_write_buf_packed_u8(swjdp_common_t *swjdp, uint8_t *buffer, int count dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue); if (swjdp_transaction_endcheck(swjdp) != ERROR_OK) { - LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count); + LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count); return ERROR_JTAG_DEVICE_ERROR; } } @@ -692,7 +692,7 @@ int mem_ap_write_buf_u8(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint3 { dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address); uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3); - dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue ); + dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue); retval = swjdp_transaction_endcheck(swjdp); count--; address++; @@ -756,7 +756,7 @@ int mem_ap_read_buf_u32(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint3 if (errorcount > 1) { - LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count); + LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count); return ERROR_JTAG_DEVICE_ERROR; } } @@ -770,7 +770,7 @@ int mem_ap_read_buf_u32(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint3 uint32_t data; memcpy(&data, pBuffer, sizeof(uint32_t)); - for (i = 0; i < 4; i++ ) + for (i = 0; i < 4; i++) { *((uint8_t*)pBuffer) = (data >> 8 * (adr & 0x3)); pBuffer++; @@ -810,16 +810,16 @@ int mem_ap_read_buf_packed_u16(swjdp_common_t *swjdp, uint8_t *buffer, int count do { - dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue ); + dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue); if (swjdp_transaction_endcheck(swjdp) != ERROR_OK) { - LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count); + LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count); return ERROR_JTAG_DEVICE_ERROR; } nbytes = MIN((readcount << 1), 4); - for (i = 0; i < nbytes; i++ ) + for (i = 0; i < nbytes; i++) { *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3)); buffer++; @@ -847,11 +847,11 @@ int mem_ap_read_buf_u16(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint3 while (count > 0) { dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address); - dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue ); + dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue); retval = swjdp_transaction_endcheck(swjdp); if (address & 0x1) { - for (i = 0; i < 2; i++ ) + for (i = 0; i < 2; i++) { *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3)); buffer++; @@ -902,16 +902,16 @@ int mem_ap_read_buf_packed_u8(swjdp_common_t *swjdp, uint8_t *buffer, int count, do { - dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue ); + dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue); if (swjdp_transaction_endcheck(swjdp) != ERROR_OK) { - LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count); + LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count); return ERROR_JTAG_DEVICE_ERROR; } nbytes = MIN(readcount, 4); - for (i = 0; i < nbytes; i++ ) + for (i = 0; i < nbytes; i++) { *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3)); buffer++; @@ -939,7 +939,7 @@ int mem_ap_read_buf_u8(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint32 while (count > 0) { dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address); - dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue ); + dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue); retval = swjdp_transaction_endcheck(swjdp); *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3)); count--; @@ -971,7 +971,7 @@ int ahbap_debugport_init(swjdp_common_t *swjdp) dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT); dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT); - if ((retval=jtag_execute_queue())!=ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) return retval; /* Check that we have debug power domains activated */ @@ -979,7 +979,7 @@ int ahbap_debugport_init(swjdp_common_t *swjdp) { LOG_DEBUG("swjdp: wait CDBGPWRUPACK"); dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT); - if ((retval=jtag_execute_queue())!=ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) return retval; alive_sleep(10); } @@ -988,7 +988,7 @@ int ahbap_debugport_init(swjdp_common_t *swjdp) { LOG_DEBUG("swjdp: wait CSYSPWRUPACK"); dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT); - if ((retval=jtag_execute_queue())!=ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) return retval; alive_sleep(10); } @@ -1002,7 +1002,7 @@ int ahbap_debugport_init(swjdp_common_t *swjdp) dap_ap_read_reg_u32(swjdp, 0xFC, &idreg); dap_ap_read_reg_u32(swjdp, 0xF8, &romaddr); - LOG_DEBUG("AHB-AP ID Register 0x%x, Debug ROM Address 0x%x", idreg, romaddr); + LOG_DEBUG("AHB-AP ID Register 0x%" PRIx32 ", Debug ROM Address 0x%" PRIx32 "", idreg, romaddr); return ERROR_OK; } @@ -1027,8 +1027,8 @@ int dap_info_command(struct command_context_s *cmd_ctx, swjdp_common_t *swjdp, i dap_ap_read_reg_u32(swjdp, 0xFC, &apid); swjdp_transaction_endcheck(swjdp); /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */ - mem_ap = ((apid&0x10000)&&((apid&0x0F)!=0)); - command_print(cmd_ctx, "ap identification register 0x%8.8x", apid); + mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0)); + command_print(cmd_ctx, "ap identification register 0x%8.8" PRIx32 "", apid); if (apid) { switch (apid&0x0F) @@ -1046,14 +1046,14 @@ int dap_info_command(struct command_context_s *cmd_ctx, swjdp_common_t *swjdp, i command_print(cmd_ctx, "\tUnknown AP-type"); break; } - command_print(cmd_ctx, "ap debugbase 0x%8.8x", dbgbase); + command_print(cmd_ctx, "ap debugbase 0x%8.8" PRIx32 "", dbgbase); } else { command_print(cmd_ctx, "No AP found at this apsel 0x%x", apsel); } - romtable_present = ((mem_ap)&&(dbgbase != 0xFFFFFFFF)); + romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF)); if (romtable_present) { uint32_t cid0,cid1,cid2,cid3,memtype,romentry; @@ -1065,50 +1065,50 @@ int dap_info_command(struct command_context_s *cmd_ctx, swjdp_common_t *swjdp, i } else { - command_print(cmd_ctx, "\tROM table in legacy format" ); + command_print(cmd_ctx, "\tROM table in legacy format"); } /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */ - mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFF0, &cid0); - mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFF4, &cid1); - mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFF8, &cid2); - mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFFC, &cid3); - mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFCC, &memtype); + mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF0, &cid0); + mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF4, &cid1); + mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF8, &cid2); + mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFFC, &cid3); + mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFCC, &memtype); swjdp_transaction_endcheck(swjdp); - command_print(cmd_ctx, "\tCID3 0x%x, CID2 0x%x, CID1 0x%x, CID0, 0x%x",cid3,cid2,cid1,cid0); + command_print(cmd_ctx, "\tCID3 0x%" PRIx32 ", CID2 0x%" PRIx32 ", CID1 0x%" PRIx32 " CID0, 0x%" PRIx32,cid3,cid2,cid1,cid0); if (memtype&0x01) { command_print(cmd_ctx, "\tMEMTYPE system memory present on bus"); } else { - command_print(cmd_ctx, "\tMEMTYPE system memory not present. Dedicated debug bus" ); + command_print(cmd_ctx, "\tMEMTYPE system memory not present. Dedicated debug bus"); } - /* Now we read ROM table entries from dbgbase&0xFFFFF000)|0x000 until we get 0x00000000 */ + /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */ entry_offset = 0; do { - mem_ap_read_atomic_u32(swjdp, (dbgbase&0xFFFFF000)|entry_offset, &romentry); - command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%x",entry_offset,romentry); + mem_ap_read_atomic_u32(swjdp, (dbgbase&0xFFFFF000) | entry_offset, &romentry); + command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "",entry_offset,romentry); if (romentry&0x01) { uint32_t c_cid0,c_cid1,c_cid2,c_cid3,c_pid0,c_pid1,c_pid2,c_pid3,c_pid4,component_start; - uint32_t component_base = (uint32_t)((dbgbase&0xFFFFF000)+(int)(romentry&0xFFFFF000)); - mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFE0, &c_pid0); - mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFE4, &c_pid1); - mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFE8, &c_pid2); - mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFEC, &c_pid3); - mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFD0, &c_pid4); - mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFF0, &c_cid0); - mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFF4, &c_cid1); - mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFF8, &c_cid2); - mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFFC, &c_cid3); - component_start = component_base - 0x1000*(c_pid4>>4); - command_print(cmd_ctx, "\t\tComponent base address 0x%x, pid4 0x%x, start address 0x%x",component_base,c_pid4,component_start); - command_print(cmd_ctx, "\t\tComponent cid1 0x%x, class is %s",c_cid1,class_description[(c_cid1>>4)&0xF]); /* Se ARM DDI 0314 C Table 2.2 */ - command_print(cmd_ctx, "\t\tCID3 0x%x, CID2 0x%x, CID1 0x%x, CID0, 0x%x",c_cid3,c_cid2,c_cid1,c_cid0); - command_print(cmd_ctx, "\t\tPID3 0x%x, PID2 0x%x, PID1 0x%x, PID0, 0x%x",c_pid3,c_pid2,c_pid1,c_pid0); - /* For CoreSight components, (c_cid1>>4)&0xF==9 , we also read 0xFC8 DevId and 0xFCC DevType */ + uint32_t component_base = (uint32_t)((dbgbase&0xFFFFF000) + (int)(romentry&0xFFFFF000)); + mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000) | 0xFE0, &c_pid0); + mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000) | 0xFE4, &c_pid1); + mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000) | 0xFE8, &c_pid2); + mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000) | 0xFEC, &c_pid3); + mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000) | 0xFD0, &c_pid4); + mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000) | 0xFF0, &c_cid0); + mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000) | 0xFF4, &c_cid1); + mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000) | 0xFF8, &c_cid2); + mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000) | 0xFFC, &c_cid3); + component_start = component_base - 0x1000*(c_pid4 >> 4); + command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32 ", pid4 0x%" PRIx32 ", start address 0x%" PRIx32 "",component_base,c_pid4,component_start); + command_print(cmd_ctx, "\t\tComponent cid1 0x%" PRIx32 ", class is %s",c_cid1,class_description[(c_cid1 >> 4)&0xF]); /* Se ARM DDI 0314 C Table 2.2 */ + command_print(cmd_ctx, "\t\tCID3 0x%" PRIx32 ", CID2 0x%" PRIx32 ", CID1 0x%" PRIx32 ", CID0, 0x%" PRIx32 "",c_cid3,c_cid2,c_cid1,c_cid0); + command_print(cmd_ctx, "\t\tPID3 0x%" PRIx32 ", PID2 0x%" PRIx32 ", PID1 0x%" PRIx32 ", PID0, 0x%" PRIx32 "",c_pid3,c_pid2,c_pid1,c_pid0); + /* For CoreSight components, (c_cid1 >> 4)&0xF == 9 , we also read 0xFC8 DevId and 0xFCC DevType */ } else { @@ -1118,7 +1118,7 @@ int dap_info_command(struct command_context_s *cmd_ctx, swjdp_common_t *swjdp, i command_print(cmd_ctx, "\t\tEnd of ROM table"); } entry_offset += 4; - } while (romentry>0); + } while (romentry > 0); } else {