X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm_adi_v5.c;h=b17fd410f353453b01519672382bf0040cec3776;hp=c0d664d236daaf8c6ee6129bce09c99d954f8194;hb=927e53f8d5e6ebaf52be82cb7300cbbb471a92bb;hpb=4668bd264cfe64c3e3ddd0f75cb5bf2e5e85f717 diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c index c0d664d236..b17fd410f3 100644 --- a/src/target/arm_adi_v5.c +++ b/src/target/arm_adi_v5.c @@ -69,11 +69,11 @@ #include "config.h" #endif +#include "jtag/interface.h" #include "arm.h" #include "arm_adi_v5.h" #include - /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */ /* @@ -100,12 +100,11 @@ static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address * @param apsel Number of the AP to (implicitly) use with further * transactions. This normally identifies a MEM-AP. */ -void dap_ap_select(struct adiv5_dap *dap,uint8_t ap) +void dap_ap_select(struct adiv5_dap *dap, uint8_t ap) { uint32_t new_ap = (ap << 24) & 0xFF000000; - if (new_ap != dap->ap_current) - { + if (new_ap != dap->ap_current) { dap->ap_current = new_ap; /* Switching AP invalidates cached values. * Values MUST BE UPDATED BEFORE AP ACCESS. @@ -140,16 +139,14 @@ int dap_setup_accessport(struct adiv5_dap *dap, uint32_t csw, uint32_t tar) int retval; csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT; - if (csw != dap->ap_csw_value) - { + if (csw != dap->ap_csw_value) { /* LOG_DEBUG("DAP: Set CSW %x",csw); */ retval = dap_queue_ap_write(dap, AP_REG_CSW, csw); if (retval != ERROR_OK) return retval; dap->ap_csw_value = csw; } - if (tar != dap->ap_tar_value) - { + if (tar != dap->ap_tar_value) { /* LOG_DEBUG("DAP: Set TAR %x",tar); */ retval = dap_queue_ap_write(dap, AP_REG_TAR, tar); if (retval != ERROR_OK) @@ -265,32 +262,30 @@ int mem_ap_write_atomic_u32(struct adiv5_dap *dap, uint32_t address, /***************************************************************************** * * -* mem_ap_write_buf(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address) * +* mem_ap_write_buf(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address, bool addr_incr) * * * * Write a buffer in target order (little endian) * * * *****************************************************************************/ -int mem_ap_write_buf_u32(struct adiv5_dap *dap, const uint8_t *buffer, int count, uint32_t address) +int mem_ap_write_buf_u32(struct adiv5_dap *dap, const uint8_t *buffer, int count, uint32_t address, bool addr_incr) { int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK; uint32_t adr = address; - const uint8_t* pBuffer = buffer; + const uint8_t *pBuffer = buffer; + uint32_t incr_flag = CSW_ADDRINC_OFF; count >>= 2; wcount = count; /* if we have an unaligned access - reorder data */ - if (adr & 0x3u) - { - for (writecount = 0; writecount < count; writecount++) - { + if (adr & 0x3u) { + for (writecount = 0; writecount < count; writecount++) { int i; uint32_t outvalue; memcpy(&outvalue, pBuffer, sizeof(uint32_t)); - for (i = 0; i < 4; i++) - { - *((uint8_t*)pBuffer + (adr & 0x3)) = outvalue; + for (i = 0; i < 4; i++) { + *((uint8_t *)pBuffer + (adr & 0x3)) = outvalue; outvalue >>= 8; adr++; } @@ -298,8 +293,7 @@ int mem_ap_write_buf_u32(struct adiv5_dap *dap, const uint8_t *buffer, int count } } - while (wcount > 0) - { + while (wcount > 0) { /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/ blocksize = max_tar_block_size(dap->tar_autoincr_block, address); if (wcount < blocksize) @@ -309,31 +303,31 @@ int mem_ap_write_buf_u32(struct adiv5_dap *dap, const uint8_t *buffer, int count if (blocksize == 0) blocksize = 1; - retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_SINGLE, address); + if (addr_incr) + incr_flag = CSW_ADDRINC_SINGLE; + + retval = dap_setup_accessport(dap, CSW_32BIT | incr_flag, address); if (retval != ERROR_OK) return retval; - for (writecount = 0; writecount < blocksize; writecount++) - { - retval = dap_queue_ap_write(dap, AP_REG_DRW, - *(uint32_t *) ((void *) (buffer + 4 * writecount))); + for (writecount = 0; writecount < blocksize; writecount++) { + uint32_t tmp; + tmp = buf_get_u32(buffer + 4 * writecount, 0, 32); + retval = dap_queue_ap_write(dap, AP_REG_DRW, tmp); if (retval != ERROR_OK) break; } - if ((retval = dap_run(dap)) == ERROR_OK) - { + retval = dap_run(dap); + if (retval == ERROR_OK) { wcount = wcount - blocksize; - address = address + 4 * blocksize; + if (addr_incr) + address = address + 4 * blocksize; buffer = buffer + 4 * blocksize; - } - else - { + } else errorcount++; - } - if (errorcount > 1) - { + if (errorcount > 1) { LOG_WARNING("Block write error address 0x%" PRIx32 ", wcount 0x%x", address, wcount); return retval; } @@ -350,8 +344,7 @@ static int mem_ap_write_buf_packed_u16(struct adiv5_dap *dap, wcount = count >> 1; - while (wcount > 0) - { + while (wcount > 0) { int nbytes; /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/ @@ -369,16 +362,13 @@ static int mem_ap_write_buf_packed_u16(struct adiv5_dap *dap, return retval; writecount = blocksize; - do - { + do { nbytes = MIN((writecount << 1), 4); - if (nbytes < 4) - { + if (nbytes < 4) { retval = mem_ap_write_buf_u16(dap, buffer, nbytes, address); - if (retval != ERROR_OK) - { + if (retval != ERROR_OK) { LOG_WARNING("Block write error address " "0x%" PRIx32 ", count 0x%x", address, count); @@ -386,15 +376,12 @@ static int mem_ap_write_buf_packed_u16(struct adiv5_dap *dap, } address += nbytes >> 1; - } - else - { + } else { uint32_t outvalue; memcpy(&outvalue, buffer, sizeof(uint32_t)); - for (i = 0; i < nbytes; i++) - { - *((uint8_t*)buffer + (address & 0x3)) = outvalue; + for (i = 0; i < nbytes; i++) { + *((uint8_t *)buffer + (address & 0x3)) = outvalue; outvalue >>= 8; address++; } @@ -405,8 +392,8 @@ static int mem_ap_write_buf_packed_u16(struct adiv5_dap *dap, if (retval != ERROR_OK) break; - if ((retval = dap_run(dap)) != ERROR_OK) - { + retval = dap_run(dap); + if (retval != ERROR_OK) { LOG_WARNING("Block write error address " "0x%" PRIx32 ", count 0x%x", address, count); @@ -431,8 +418,7 @@ int mem_ap_write_buf_u16(struct adiv5_dap *dap, const uint8_t *buffer, int count if (count >= 4) return mem_ap_write_buf_packed_u16(dap, buffer, count, address); - while (count > 0) - { + while (count > 0) { retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address); if (retval != ERROR_OK) return retval; @@ -463,8 +449,7 @@ static int mem_ap_write_buf_packed_u8(struct adiv5_dap *dap, wcount = count; - while (wcount > 0) - { + while (wcount > 0) { int nbytes; /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/ @@ -478,15 +463,12 @@ static int mem_ap_write_buf_packed_u8(struct adiv5_dap *dap, return retval; writecount = blocksize; - do - { + do { nbytes = MIN(writecount, 4); - if (nbytes < 4) - { + if (nbytes < 4) { retval = mem_ap_write_buf_u8(dap, buffer, nbytes, address); - if (retval != ERROR_OK) - { + if (retval != ERROR_OK) { LOG_WARNING("Block write error address " "0x%" PRIx32 ", count 0x%x", address, count); @@ -494,15 +476,12 @@ static int mem_ap_write_buf_packed_u8(struct adiv5_dap *dap, } address += nbytes; - } - else - { + } else { uint32_t outvalue; memcpy(&outvalue, buffer, sizeof(uint32_t)); - for (i = 0; i < nbytes; i++) - { - *((uint8_t*)buffer + (address & 0x3)) = outvalue; + for (i = 0; i < nbytes; i++) { + *((uint8_t *)buffer + (address & 0x3)) = outvalue; outvalue >>= 8; address++; } @@ -513,8 +492,8 @@ static int mem_ap_write_buf_packed_u8(struct adiv5_dap *dap, if (retval != ERROR_OK) break; - if ((retval = dap_run(dap)) != ERROR_OK) - { + retval = dap_run(dap); + if (retval != ERROR_OK) { LOG_WARNING("Block write error address " "0x%" PRIx32 ", count 0x%x", address, count); @@ -539,8 +518,7 @@ int mem_ap_write_buf_u8(struct adiv5_dap *dap, const uint8_t *buffer, int count, if (count >= 4) return mem_ap_write_buf_packed_u8(dap, buffer, count, address); - while (count > 0) - { + while (count > 0) { retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address); if (retval != ERROR_OK) return retval; @@ -574,20 +552,21 @@ extern int adi_jtag_dp_scan(struct adiv5_dap *dap, * @param buffer where the words will be stored (in host byte order). * @param count How many words to read. * @param address Memory address from which to read words; all the + * @param addr_incr if true, increment the source address for each u32 * words must be readable by the currently selected MEM-AP. */ int mem_ap_read_buf_u32(struct adiv5_dap *dap, uint8_t *buffer, - int count, uint32_t address) + int count, uint32_t address, bool addr_incr) { int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK; uint32_t adr = address; - uint8_t* pBuffer = buffer; + uint8_t *pBuffer = buffer; + uint32_t incr_flag = CSW_ADDRINC_OFF; count >>= 2; wcount = count; - while (wcount > 0) - { + while (wcount > 0) { /* Adjust to read blocks within boundaries aligned to the * TAR autoincrement size (at least 2^10). Autoincrement * mode avoids an extra per-word roundtrip to update TAR. @@ -601,7 +580,10 @@ int mem_ap_read_buf_u32(struct adiv5_dap *dap, uint8_t *buffer, if (blocksize == 0) blocksize = 1; - retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_SINGLE, + if (addr_incr) + incr_flag = CSW_ADDRINC_SINGLE; + + retval = dap_setup_accessport(dap, CSW_32BIT | incr_flag, address); if (retval != ERROR_OK) return retval; @@ -618,8 +600,7 @@ int mem_ap_read_buf_u32(struct adiv5_dap *dap, uint8_t *buffer, DPAP_READ, 0, NULL, NULL); if (retval != ERROR_OK) return retval; - for (readcount = 0; readcount < blocksize - 1; readcount++) - { + for (readcount = 0; readcount < blocksize - 1; readcount++) { /* Scan out next read; scan in posted value for the * previous one. Assumes read is acked "OK/FAULT", * and CTRL_STAT says that meant "OK". @@ -641,11 +622,9 @@ int mem_ap_read_buf_u32(struct adiv5_dap *dap, uint8_t *buffer, return retval; retval = dap_run(dap); - if (retval != ERROR_OK) - { + if (retval != ERROR_OK) { errorcount++; - if (errorcount <= 1) - { + if (errorcount <= 1) { /* try again */ continue; } @@ -653,22 +632,20 @@ int mem_ap_read_buf_u32(struct adiv5_dap *dap, uint8_t *buffer, return retval; } wcount = wcount - blocksize; - address += 4 * blocksize; + if (addr_incr) + address += 4 * blocksize; buffer += 4 * blocksize; } /* if we have an unaligned access - reorder data */ - if (adr & 0x3u) - { - for (readcount = 0; readcount < count; readcount++) - { + if (adr & 0x3u) { + for (readcount = 0; readcount < count; readcount++) { int i; uint32_t data; memcpy(&data, pBuffer, sizeof(uint32_t)); - for (i = 0; i < 4; i++) - { - *((uint8_t*)pBuffer) = + for (i = 0; i < 4; i++) { + *((uint8_t *)pBuffer) = (data >> 8 * (adr & 0x3)); pBuffer++; adr++; @@ -688,8 +665,7 @@ static int mem_ap_read_buf_packed_u16(struct adiv5_dap *dap, wcount = count >> 1; - while (wcount > 0) - { + while (wcount > 0) { int nbytes; /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/ @@ -706,22 +682,20 @@ static int mem_ap_read_buf_packed_u16(struct adiv5_dap *dap, blocksize = 1; readcount = blocksize; - do - { + do { retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue); if (retval != ERROR_OK) return retval; - if ((retval = dap_run(dap)) != ERROR_OK) - { + retval = dap_run(dap); + if (retval != ERROR_OK) { LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count); return retval; } nbytes = MIN((readcount << 1), 4); - for (i = 0; i < nbytes; i++) - { - *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3)); + for (i = 0; i < nbytes; i++) { + *((uint8_t *)buffer) = (invalue >> 8 * (address & 0x3)); buffer++; address++; } @@ -751,8 +725,7 @@ int mem_ap_read_buf_u16(struct adiv5_dap *dap, uint8_t *buffer, if (count >= 4) return mem_ap_read_buf_packed_u16(dap, buffer, count, address); - while (count > 0) - { + while (count > 0) { retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address); if (retval != ERROR_OK) return retval; @@ -764,17 +737,13 @@ int mem_ap_read_buf_u16(struct adiv5_dap *dap, uint8_t *buffer, if (retval != ERROR_OK) break; - if (address & 0x1) - { - for (i = 0; i < 2; i++) - { - *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3)); + if (address & 0x1) { + for (i = 0; i < 2; i++) { + *((uint8_t *)buffer) = (invalue >> 8 * (address & 0x3)); buffer++; address++; } - } - else - { + } else { uint16_t svalue = (invalue >> 8 * (address & 0x3)); memcpy(buffer, &svalue, sizeof(uint16_t)); address += 2; @@ -801,8 +770,7 @@ static int mem_ap_read_buf_packed_u8(struct adiv5_dap *dap, wcount = count; - while (wcount > 0) - { + while (wcount > 0) { int nbytes; /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/ @@ -816,22 +784,20 @@ static int mem_ap_read_buf_packed_u8(struct adiv5_dap *dap, return retval; readcount = blocksize; - do - { + do { retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue); if (retval != ERROR_OK) return retval; - if ((retval = dap_run(dap)) != ERROR_OK) - { + retval = dap_run(dap); + if (retval != ERROR_OK) { LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count); return retval; } nbytes = MIN(readcount, 4); - for (i = 0; i < nbytes; i++) - { - *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3)); + for (i = 0; i < nbytes; i++) { + *((uint8_t *)buffer) = (invalue >> 8 * (address & 0x3)); buffer++; address++; } @@ -861,8 +827,7 @@ int mem_ap_read_buf_u8(struct adiv5_dap *dap, uint8_t *buffer, if (count >= 4) return mem_ap_read_buf_packed_u8(dap, buffer, count, address); - while (count > 0) - { + while (count > 0) { retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address); if (retval != ERROR_OK) return retval; @@ -873,7 +838,7 @@ int mem_ap_read_buf_u8(struct adiv5_dap *dap, uint8_t *buffer, if (retval != ERROR_OK) break; - *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3)); + *((uint8_t *)buffer) = (invalue >> 8 * (address & 0x3)); count--; address++; buffer++; @@ -927,11 +892,18 @@ int mem_ap_sel_read_buf_u16(struct adiv5_dap *swjdp, uint8_t ap, return mem_ap_read_buf_u16(swjdp, buffer, count, address); } +int mem_ap_sel_read_buf_u32_noincr(struct adiv5_dap *swjdp, uint8_t ap, + uint8_t *buffer, int count, uint32_t address) +{ + dap_ap_select(swjdp, ap); + return mem_ap_read_buf_u32(swjdp, buffer, count, address, false); +} + int mem_ap_sel_read_buf_u32(struct adiv5_dap *swjdp, uint8_t ap, uint8_t *buffer, int count, uint32_t address) { dap_ap_select(swjdp, ap); - return mem_ap_read_buf_u32(swjdp, buffer, count, address); + return mem_ap_read_buf_u32(swjdp, buffer, count, address, true); } int mem_ap_sel_write_buf_u8(struct adiv5_dap *swjdp, uint8_t ap, @@ -952,7 +924,14 @@ int mem_ap_sel_write_buf_u32(struct adiv5_dap *swjdp, uint8_t ap, const uint8_t *buffer, int count, uint32_t address) { dap_ap_select(swjdp, ap); - return mem_ap_write_buf_u32(swjdp, buffer, count, address); + return mem_ap_write_buf_u32(swjdp, buffer, count, address, true); +} + +int mem_ap_sel_write_buf_u32_noincr(struct adiv5_dap *swjdp, uint8_t ap, + const uint8_t *buffer, int count, uint32_t address) +{ + dap_ap_select(swjdp, ap); + return mem_ap_write_buf_u32(swjdp, buffer, count, address, false); } #define MDM_REG_STAT 0x00 @@ -999,9 +978,8 @@ int dap_syssec_kinetis_mdmap(struct adiv5_dap *dap) return retval; dap_run(dap); - if ( val != 0x001C0000 ) - { - LOG_DEBUG("id doesn't match %08X != 0x001C0000",val); + if (val != 0x001C0000) { + LOG_DEBUG("id doesn't match %08X != 0x001C0000", val); dap_ap_select(dap, 0); return ERROR_FAIL; } @@ -1015,40 +993,25 @@ int dap_syssec_kinetis_mdmap(struct adiv5_dap *dap) return retval; dap_run(dap); - LOG_DEBUG("MDM_REG_STAT %08X",val); + LOG_DEBUG("MDM_REG_STAT %08X", val); - if ( (val & (MDM_STAT_SYSSEC|MDM_STAT_FREADY)) != (MDM_STAT_FREADY) ) - { + if ((val & (MDM_STAT_SYSSEC|MDM_STAT_FREADY)) != (MDM_STAT_FREADY)) { LOG_DEBUG("MDMAP: system is secured, masserase needed"); - if ( !(val & MDM_STAT_FMEEN) ) - { + if (!(val & MDM_STAT_FMEEN)) LOG_DEBUG("MDMAP: masserase is disabled"); - } - else - { + else { /* we need to assert reset */ - if ( jtag_reset_config & RESET_HAS_SRST ) - { + if (jtag_reset_config & RESET_HAS_SRST) { /* default to asserting srst */ - if (jtag_reset_config & RESET_SRST_PULLS_TRST) - { - jtag_add_reset(1, 1); - } - else - { - jtag_add_reset(0, 1); - } - } - else - { + adapter_assert_reset(); + } else { LOG_DEBUG("SRST not configured"); dap_ap_select(dap, 0); return ERROR_FAIL; } - while(1) - { + while (1) { retval = dap_queue_ap_write(dap, MDM_REG_CTRL, MEM_CTRL_FMEIP); if (retval != ERROR_OK) return retval; @@ -1058,14 +1021,13 @@ int dap_syssec_kinetis_mdmap(struct adiv5_dap *dap) if (retval != ERROR_OK) return retval; dap_run(dap); - LOG_DEBUG("MDM_REG_STAT %08X",val); + LOG_DEBUG("MDM_REG_STAT %08X", val); - if ( (val&1)) + if ((val & 1)) break; } - while(1) - { + while (1) { retval = dap_queue_ap_write(dap, MDM_REG_CTRL, 0); if (retval != ERROR_OK) return retval; @@ -1075,15 +1037,15 @@ int dap_syssec_kinetis_mdmap(struct adiv5_dap *dap) if (retval != ERROR_OK) return retval; dap_run(dap); - LOG_DEBUG("MDM_REG_STAT %08X",val); + LOG_DEBUG("MDM_REG_STAT %08X", val); /* read control register and wait for ready */ retval = dap_queue_ap_read(dap, MDM_REG_CTRL, &val); if (retval != ERROR_OK) return retval; dap_run(dap); - LOG_DEBUG("MDM_REG_CTRL %08X",val); + LOG_DEBUG("MDM_REG_CTRL %08X", val); - if ( val == 0x00 ) + if (val == 0x00) break; } } @@ -1107,7 +1069,6 @@ static struct dap_syssec_filter dap_syssec_filter_data[] = { { 0x4BA00477, dap_syssec_kinetis_mdmap } }; - /** * */ @@ -1116,15 +1077,12 @@ int dap_syssec(struct adiv5_dap *dap) unsigned int i; struct jtag_tap *tap; - for(i=0;ijtag_info->tap; - while (tap != NULL) - { - if ( tap->hasidcode && (dap_syssec_filter_data[i].idcode == tap->idcode) ) - { - LOG_DEBUG("DAP: mdmap_init for idcode: %08x",tap->idcode); + while (tap != NULL) { + if (tap->hasidcode && (dap_syssec_filter_data[i].idcode == tap->idcode)) { + LOG_DEBUG("DAP: mdmap_init for idcode: %08x", tap->idcode); dap_syssec_filter_data[i].dap_init(dap); } tap = tap->next_tap; @@ -1202,28 +1160,29 @@ int ahbap_debugport_init(struct adiv5_dap *dap) retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat); if (retval != ERROR_OK) return retval; - if ((retval = dap_run(dap)) != ERROR_OK) + retval = dap_run(dap); + if (retval != ERROR_OK) return retval; /* Check that we have debug power domains activated */ - while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10)) - { + while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10)) { LOG_DEBUG("DAP: wait CDBGPWRUPACK"); retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat); if (retval != ERROR_OK) return retval; - if ((retval = dap_run(dap)) != ERROR_OK) + retval = dap_run(dap); + if (retval != ERROR_OK) return retval; alive_sleep(10); } - while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10)) - { + while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10)) { LOG_DEBUG("DAP: wait CSYSPWRUPACK"); retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat); if (retval != ERROR_OK) return retval; - if ((retval = dap_run(dap)) != ERROR_OK) + retval = dap_run(dap); + if (retval != ERROR_OK) return retval; alive_sleep(10); } @@ -1248,16 +1207,15 @@ int ahbap_debugport_init(struct adiv5_dap *dap) /* CID interpretation -- see ARM IHI 0029B section 3 * and ARM IHI 0031A table 13-3. */ -static const char *class_description[16] ={ +static const char *class_description[16] = { "Reserved", "ROM table", "Reserved", "Reserved", "Reserved", "Reserved", "Reserved", "Reserved", "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block", "Reserved", "OptimoDE DESS", - "Generic IP component", "PrimeCell or System component" + "Generic IP component", "PrimeCell or System component" }; -static bool -is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0) +static bool is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0) { return cid3 == 0xb1 && cid2 == 0x05 && ((cid1 & 0x0f) == 0) && cid0 == 0x0d; @@ -1320,8 +1278,7 @@ int dap_lookup_cs_component(struct adiv5_dap *dap, int ap, ap_old = dap->ap_current; dap_ap_select(dap, ap); - do - { + do { retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) | entry_offset, &romentry); if (retval != ERROR_OK) @@ -1334,6 +1291,8 @@ int dap_lookup_cs_component(struct adiv5_dap *dap, int ap, retval = mem_ap_read_atomic_u32(dap, (component_base & 0xfffff000) | 0xfcc, &devtype); + if (retval != ERROR_OK) + return retval; if ((devtype & 0xff) == type) { *addr = component_base; retval = ERROR_OK; @@ -1367,10 +1326,8 @@ static int dap_info_command(struct command_context *cmd_ctx, /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */ mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0)); command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid); - if (apid) - { - switch (apid&0x0F) - { + if (apid) { + switch (apid&0x0F) { case 0: command_print(cmd_ctx, "\tType is JTAG-AP"); break; @@ -1389,18 +1346,13 @@ static int dap_info_command(struct command_context *cmd_ctx, * not a ROM table ... or have no such components at all. */ if (mem_ap) - command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32, - dbgbase); - } - else - { + command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32, dbgbase); + } else command_print(cmd_ctx, "No AP found at this ap 0x%x", ap); - } romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF)); - if (romtable_present) - { - uint32_t cid0,cid1,cid2,cid3,memtype,romentry; + if (romtable_present) { + uint32_t cid0, cid1, cid2, cid3, memtype, romentry; uint16_t entry_offset; /* bit 16 of apid indicates a memory access port */ @@ -1444,78 +1396,61 @@ static int dap_info_command(struct command_context *cmd_ctx, /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */ entry_offset = 0; - do - { + do { retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) | entry_offset, &romentry); if (retval != ERROR_OK) return retval; - command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "",entry_offset,romentry); - if (romentry&0x01) - { + command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "", entry_offset, romentry); + if (romentry & 0x01) { uint32_t c_cid0, c_cid1, c_cid2, c_cid3; uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4; uint32_t component_base; unsigned part_num; char *type, *full; - component_base = (dbgbase & 0xFFFFF000) - + (romentry & 0xFFFFF000); + component_base = (dbgbase & 0xFFFFF000) + (romentry & 0xFFFFF000); /* IDs are in last 4K section */ - - - retval = mem_ap_read_atomic_u32(dap, - component_base + 0xFE0, &c_pid0); + retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE0, &c_pid0); if (retval != ERROR_OK) return retval; c_pid0 &= 0xff; - retval = mem_ap_read_atomic_u32(dap, - component_base + 0xFE4, &c_pid1); + retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE4, &c_pid1); if (retval != ERROR_OK) return retval; c_pid1 &= 0xff; - retval = mem_ap_read_atomic_u32(dap, - component_base + 0xFE8, &c_pid2); + retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE8, &c_pid2); if (retval != ERROR_OK) return retval; c_pid2 &= 0xff; - retval = mem_ap_read_atomic_u32(dap, - component_base + 0xFEC, &c_pid3); + retval = mem_ap_read_atomic_u32(dap, component_base + 0xFEC, &c_pid3); if (retval != ERROR_OK) return retval; c_pid3 &= 0xff; - retval = mem_ap_read_atomic_u32(dap, - component_base + 0xFD0, &c_pid4); + retval = mem_ap_read_atomic_u32(dap, component_base + 0xFD0, &c_pid4); if (retval != ERROR_OK) return retval; c_pid4 &= 0xff; - retval = mem_ap_read_atomic_u32(dap, - component_base + 0xFF0, &c_cid0); + retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF0, &c_cid0); if (retval != ERROR_OK) return retval; c_cid0 &= 0xff; - retval = mem_ap_read_atomic_u32(dap, - component_base + 0xFF4, &c_cid1); + retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF4, &c_cid1); if (retval != ERROR_OK) return retval; c_cid1 &= 0xff; - retval = mem_ap_read_atomic_u32(dap, - component_base + 0xFF8, &c_cid2); + retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF8, &c_cid2); if (retval != ERROR_OK) return retval; c_cid2 &= 0xff; - retval = mem_ap_read_atomic_u32(dap, - component_base + 0xFFC, &c_cid3); + retval = mem_ap_read_atomic_u32(dap, component_base + 0xFFC, &c_cid3); if (retval != ERROR_OK) return retval; c_cid3 &= 0xff; - - command_print(cmd_ctx, - "\t\tComponent base address 0x%" PRIx32 - ", start address 0x%" PRIx32, - component_base, + command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32 "," + "start address 0x%" PRIx32, component_base, /* component may take multiple 4K pages */ component_base - 0x1000*(c_pid4 >> 4)); command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s", @@ -1638,7 +1573,7 @@ static int dap_info_command(struct command_context *cmd_ctx, if (!is_dap_cid_ok(cid3, cid2, cid1, cid0)) command_print(cmd_ctx, - "\t\tCID3 0%2.2x" + "\t\tCID3 0%2.2x" ", CID2 0%2.2x" ", CID1 0%2.2x" ", CID0 0%2.2x", @@ -1677,11 +1612,15 @@ static int dap_info_command(struct command_context *cmd_ctx, type = "Cortex-M3 FBP"; full = "(Flash Patch and Breakpoint)"; break; + case 0x00c: + type = "Cortex-M4 SCS"; + full = "(System Control Space)"; + break; case 0x00d: type = "CoreSight ETM11"; full = "(Embedded Trace)"; break; - // case 0x113: what? + /* case 0x113: what? */ case 0x120: /* from OMAP3 memmap */ type = "TI SDTI"; full = "(System Debug Trace Interface)"; @@ -1726,10 +1665,18 @@ static int dap_info_command(struct command_context *cmd_ctx, type = "Cortex-M3 ETM"; full = "(Embedded Trace)"; break; + case 0x925: + type = "Cortex-M4 ETM"; + full = "(Embedded Trace)"; + break; case 0x930: type = "Cortex-R4 ETM"; full = "(Embedded Trace)"; break; + case 0x9a1: + type = "Cortex-M4 TPUI"; + full = "(Trace Port Interface Unit)"; + break; case 0xc08: type = "Cortex-A8 Debug"; full = "(Debug Unit)"; @@ -1741,9 +1688,7 @@ static int dap_info_command(struct command_context *cmd_ctx, } command_print(cmd_ctx, "\t\tPart is %s %s", type, full); - } - else - { + } else { if (romentry) command_print(cmd_ctx, "\t\tComponent not present"); else @@ -1751,11 +1696,8 @@ static int dap_info_command(struct command_context *cmd_ctx, } entry_offset += 4; } while (romentry > 0); - } - else - { + } else command_print(cmd_ctx, "\tNo ROM table present"); - } dap_ap_select(dap, ap_old); return ERROR_OK; @@ -1975,9 +1917,8 @@ const struct command_registration dap_command_handlers[] = { .name = "dap", .mode = COMMAND_EXEC, .help = "DAP command group", + .usage = "", .chain = dap_commands, }, COMMAND_REGISTRATION_DONE }; - -