X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm_adi_v5.c;h=7f4bc58c22e10f6144d228661bfddf8c1eda8c93;hp=5ce96779420785b037cacc05c2edcd499afa281a;hb=23402315ce01071f30d7ec0c5ca7563ce41f1cc6;hpb=8f41f7c7d5673a9616d0f1ec94617768f5b73234 diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c index 5ce9677942..7f4bc58c22 100644 --- a/src/target/arm_adi_v5.c +++ b/src/target/arm_adi_v5.c @@ -29,8 +29,8 @@ * * * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A * * * - * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316A * - * Cortex-M3(tm) TRM, ARM DDI 0337C * + * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D * + * Cortex-M3(tm) TRM, ARM DDI 0337G * * * ***************************************************************************/ @@ -38,14 +38,8 @@ #include "config.h" #endif -#include "replacements.h" - #include "arm_adi_v5.h" -#include "jtag.h" -#include "log.h" #include "time_support.h" -#include -#include /* * Transaction Mode: @@ -58,99 +52,108 @@ * are immediatley available. */ + +/* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */ + +/* + uint32_t tar_block_size(uint32_t address) + Return the largest block starting at address that does not cross a tar block size alignment boundary +*/ +static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address) +{ + return (tar_autoincr_block - ((tar_autoincr_block - 1) & address)) >> 2; +} + /*************************************************************************** * * * DPACC and APACC scanchain access through JTAG-DP * * * ***************************************************************************/ -/* Scan out and in from target ordered u8 buffers */ -int adi_jtag_dp_scan(arm_jtag_t *jtag_info, u8 instr, u8 reg_addr, u8 RnW, u8 *outvalue, u8 *invalue, u8 *ack) +/* Scan out and in from target ordered uint8_t buffers */ +int adi_jtag_dp_scan(struct swjdp_common *swjdp, uint8_t instr, uint8_t reg_addr, uint8_t RnW, uint8_t *outvalue, uint8_t *invalue, uint8_t *ack) { - scan_field_t fields[2]; - u8 out_addr_buf; + struct arm_jtag *jtag_info = swjdp->jtag_info; + struct scan_field fields[2]; + uint8_t out_addr_buf; - jtag_add_end_state(TAP_IDLE); + jtag_set_end_state(TAP_IDLE); arm_jtag_set_instr(jtag_info, instr, NULL); + /* Add specified number of tck clocks before accessing memory bus */ + if ((instr == DAP_IR_APACC) && ((reg_addr == AP_REG_DRW)||((reg_addr&0xF0) == AP_REG_BD0))&& (swjdp->memaccess_tck != 0)) + jtag_add_runtest(swjdp->memaccess_tck, jtag_set_end_state(TAP_IDLE)); + fields[0].tap = jtag_info->tap; fields[0].num_bits = 3; buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1)); fields[0].out_value = &out_addr_buf; - fields[0].in_value = ack; - - fields[0].in_handler = NULL; - - fields[1].tap = jtag_info->tap; fields[1].num_bits = 32; fields[1].out_value = outvalue; - fields[1].in_value = invalue; - fields[1].in_handler = NULL; - - - - jtag_add_dr_scan(2, fields, TAP_INVALID); + jtag_add_dr_scan(2, fields, jtag_get_end_state()); return ERROR_OK; } -/* Scan out and in from host ordered u32 variables */ -int adi_jtag_dp_scan_u32(arm_jtag_t *jtag_info, u8 instr, u8 reg_addr, u8 RnW, u32 outvalue, u32 *invalue, u8 *ack) +/* Scan out and in from host ordered uint32_t variables */ +int adi_jtag_dp_scan_u32(struct swjdp_common *swjdp, uint8_t instr, uint8_t reg_addr, uint8_t RnW, uint32_t outvalue, uint32_t *invalue, uint8_t *ack) { - scan_field_t fields[2]; - u8 out_value_buf[4]; - u8 out_addr_buf; + struct arm_jtag *jtag_info = swjdp->jtag_info; + struct scan_field fields[2]; + uint8_t out_value_buf[4]; + uint8_t out_addr_buf; - jtag_add_end_state(TAP_IDLE); + jtag_set_end_state(TAP_IDLE); arm_jtag_set_instr(jtag_info, instr, NULL); + /* Add specified number of tck clocks before accessing memory bus */ + if ((instr == DAP_IR_APACC) && ((reg_addr == AP_REG_DRW)||((reg_addr&0xF0) == AP_REG_BD0))&& (swjdp->memaccess_tck != 0)) + jtag_add_runtest(swjdp->memaccess_tck, jtag_set_end_state(TAP_IDLE)); + fields[0].tap = jtag_info->tap; fields[0].num_bits = 3; buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1)); fields[0].out_value = &out_addr_buf; fields[0].in_value = ack; - fields[0].in_handler = NULL; - fields[1].tap = jtag_info->tap; fields[1].num_bits = 32; buf_set_u32(out_value_buf, 0, 32, outvalue); fields[1].out_value = out_value_buf; fields[1].in_value = NULL; - fields[1].in_handler = NULL; if (invalue) { - u8 tmp[4]; - fields[1].in_value = tmp; - jtag_add_dr_scan_now(2, fields, TAP_INVALID); + fields[1].in_value = (uint8_t *)invalue; + jtag_add_dr_scan(2, fields, jtag_get_end_state()); - *invalue=le_to_h_u32(in_buf); + jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t) invalue); } else { - jtag_add_dr_scan(2, fields, TAP_INVALID); + jtag_add_dr_scan(2, fields, jtag_get_end_state()); } return ERROR_OK; } /* scan_inout_check adds one extra inscan for DPAP_READ commands to read variables */ -int scan_inout_check(swjdp_common_t *swjdp, u8 instr, u8 reg_addr, u8 RnW, u8 *outvalue, u8 *invalue) +int scan_inout_check(struct swjdp_common *swjdp, uint8_t instr, uint8_t reg_addr, uint8_t RnW, uint8_t *outvalue, uint8_t *invalue) { - adi_jtag_dp_scan(swjdp->jtag_info, instr, reg_addr, RnW, outvalue, NULL, NULL); + adi_jtag_dp_scan(swjdp, instr, reg_addr, RnW, outvalue, NULL, NULL); + if ((RnW == DPAP_READ) && (invalue != NULL)) { - adi_jtag_dp_scan(swjdp->jtag_info, SWJDP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack); + adi_jtag_dp_scan(swjdp, DAP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack); } - /* In TRANS_MODE_ATOMIC all SWJDP_IR_APACC transactions wait for ack=OK/FAULT and the check CTRL_STAT */ - if ((instr == SWJDP_IR_APACC) && (swjdp->trans_mode == TRANS_MODE_ATOMIC)) + /* In TRANS_MODE_ATOMIC all DAP_IR_APACC transactions wait for ack = OK/FAULT and the check CTRL_STAT */ + if ((instr == DAP_IR_APACC) && (swjdp->trans_mode == TRANS_MODE_ATOMIC)) { return swjdp_transaction_endcheck(swjdp); } @@ -158,16 +161,17 @@ int scan_inout_check(swjdp_common_t *swjdp, u8 instr, u8 reg_addr, u8 RnW, u8 *o return ERROR_OK; } -int scan_inout_check_u32(swjdp_common_t *swjdp, u8 instr, u8 reg_addr, u8 RnW, u32 outvalue, u32 *invalue) +int scan_inout_check_u32(struct swjdp_common *swjdp, uint8_t instr, uint8_t reg_addr, uint8_t RnW, uint32_t outvalue, uint32_t *invalue) { - adi_jtag_dp_scan_u32(swjdp->jtag_info, instr, reg_addr, RnW, outvalue, NULL, NULL); - if ((RnW==DPAP_READ) && (invalue != NULL)) + adi_jtag_dp_scan_u32(swjdp, instr, reg_addr, RnW, outvalue, NULL, NULL); + + if ((RnW == DPAP_READ) && (invalue != NULL)) { - adi_jtag_dp_scan_u32(swjdp->jtag_info, SWJDP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack); + adi_jtag_dp_scan_u32(swjdp, DAP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack); } - /* In TRANS_MODE_ATOMIC all SWJDP_IR_APACC transactions wait for ack=OK/FAULT and then check CTRL_STAT */ - if ((instr == SWJDP_IR_APACC) && (swjdp->trans_mode == TRANS_MODE_ATOMIC)) + /* In TRANS_MODE_ATOMIC all DAP_IR_APACC transactions wait for ack = OK/FAULT and then check CTRL_STAT */ + if ((instr == DAP_IR_APACC) && (swjdp->trans_mode == TRANS_MODE_ATOMIC)) { return swjdp_transaction_endcheck(swjdp); } @@ -175,38 +179,38 @@ int scan_inout_check_u32(swjdp_common_t *swjdp, u8 instr, u8 reg_addr, u8 RnW, u return ERROR_OK; } -int swjdp_transaction_endcheck(swjdp_common_t *swjdp) +int swjdp_transaction_endcheck(struct swjdp_common *swjdp) { int retval; - u32 ctrlstat; + uint32_t ctrlstat; /* too expensive to call keep_alive() here */ #if 0 /* Danger!!!! BROKEN!!!! */ - scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat); + scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat); /* Danger!!!! BROKEN!!!! Why will jtag_execute_queue() fail here???? R956 introduced the check on return value here and now Michael Schwingen reports that this code no longer works.... https://lists.berlios.de/pipermail/openocd-development/2008-September/003107.html */ - if ((retval=jtag_execute_queue())!=ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) { LOG_ERROR("BUG: Why does this fail the first time????"); } /* Why??? second time it works??? */ #endif - scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat); - if ((retval=jtag_execute_queue())!=ERROR_OK) + scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat); + if ((retval = jtag_execute_queue()) != ERROR_OK) return retval; swjdp->ack = swjdp->ack & 0x7; if (swjdp->ack != 2) { - long long then=timeval_ms(); + long long then = timeval_ms(); while (swjdp->ack != 2) { if (swjdp->ack == 1) @@ -223,8 +227,8 @@ int swjdp_transaction_endcheck(swjdp_common_t *swjdp) return ERROR_JTAG_DEVICE_ERROR; } - scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat); - if ((retval=jtag_execute_queue())!=ERROR_OK) + scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat); + if ((retval = jtag_execute_queue()) != ERROR_OK) return retval; swjdp->ack = swjdp->ack & 0x7; } @@ -236,7 +240,7 @@ int swjdp_transaction_endcheck(swjdp_common_t *swjdp) /* Check for STICKYERR and STICKYORUN */ if (ctrlstat & (SSTICKYORUN | SSTICKYERR)) { - LOG_DEBUG("swjdp: CTRL/STAT error 0x%x", ctrlstat); + LOG_DEBUG("swjdp: CTRL/STAT error 0x%" PRIx32 "", ctrlstat); /* Check power to debug regions */ if ((ctrlstat & 0xf0000000) != 0xf0000000) { @@ -244,10 +248,10 @@ int swjdp_transaction_endcheck(swjdp_common_t *swjdp) } else { - u32 mem_ap_csw, mem_ap_tar; + uint32_t mem_ap_csw, mem_ap_tar; /* Print information about last AHBAP access */ - LOG_ERROR("AHBAP Cached values: dp_select 0x%x, ap_csw 0x%x, ap_tar 0x%x", swjdp->dp_select_value, swjdp->ap_csw_value, swjdp->ap_tar_value); + LOG_ERROR("AHBAP Cached values: dp_select 0x%" PRIx32 ", ap_csw 0x%" PRIx32 ", ap_tar 0x%" PRIx32 "", swjdp->dp_select_value, swjdp->ap_csw_value, swjdp->ap_tar_value); if (ctrlstat & SSTICKYORUN) LOG_ERROR("SWJ-DP OVERRUN - check clock or reduce jtag speed"); @@ -255,21 +259,21 @@ int swjdp_transaction_endcheck(swjdp_common_t *swjdp) LOG_ERROR("SWJ-DP STICKY ERROR"); /* Clear Sticky Error Bits */ - scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_WRITE, swjdp->dp_ctrl_stat | SSTICKYORUN | SSTICKYERR, NULL); - scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat); - if ((retval=jtag_execute_queue())!=ERROR_OK) + scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_WRITE, swjdp->dp_ctrl_stat | SSTICKYORUN | SSTICKYERR, NULL); + scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat); + if ((retval = jtag_execute_queue()) != ERROR_OK) return retval; - LOG_DEBUG("swjdp: status 0x%x", ctrlstat); + LOG_DEBUG("swjdp: status 0x%" PRIx32 "", ctrlstat); dap_ap_read_reg_u32(swjdp, AP_REG_CSW, &mem_ap_csw); dap_ap_read_reg_u32(swjdp, AP_REG_TAR, &mem_ap_tar); - if ((retval=jtag_execute_queue())!=ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) return retval; - LOG_ERROR("Read MEM_AP_CSW 0x%x, MEM_AP_TAR 0x%x", mem_ap_csw, mem_ap_tar); + LOG_ERROR("Read MEM_AP_CSW 0x%" PRIx32 ", MEM_AP_TAR 0x%" PRIx32 "", mem_ap_csw, mem_ap_tar); } - if ((retval=jtag_execute_queue())!=ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) return retval; return ERROR_JTAG_DEVICE_ERROR; } @@ -283,25 +287,25 @@ int swjdp_transaction_endcheck(swjdp_common_t *swjdp) * * ***************************************************************************/ -int dap_dp_write_reg(swjdp_common_t *swjdp, u32 value, u8 reg_addr) +int dap_dp_write_reg(struct swjdp_common *swjdp, uint32_t value, uint8_t reg_addr) { - return scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, reg_addr, DPAP_WRITE, value, NULL); + return scan_inout_check_u32(swjdp, DAP_IR_DPACC, reg_addr, DPAP_WRITE, value, NULL); } -int dap_dp_read_reg(swjdp_common_t *swjdp, u32 *value, u8 reg_addr) +int dap_dp_read_reg(struct swjdp_common *swjdp, uint32_t *value, uint8_t reg_addr) { - return scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, reg_addr, DPAP_READ, 0, value); + return scan_inout_check_u32(swjdp, DAP_IR_DPACC, reg_addr, DPAP_READ, 0, value); } -int dap_ap_select(swjdp_common_t *swjdp,u8 apsel) +int dap_ap_select(struct swjdp_common *swjdp,uint8_t apsel) { - u32 select; - select = (apsel<<24) & 0xFF000000; + uint32_t select; + select = (apsel << 24) & 0xFF000000; if (select != swjdp->apsel) { swjdp->apsel = select; - /* Switchin AP invalidates cached values */ + /* Switching AP invalidates cached values */ swjdp->dp_select_value = -1; swjdp->ap_csw_value = -1; swjdp->ap_tar_value = -1; @@ -310,9 +314,9 @@ int dap_ap_select(swjdp_common_t *swjdp,u8 apsel) return ERROR_OK; } -int dap_dp_bankselect(swjdp_common_t *swjdp,u32 ap_reg) +int dap_dp_bankselect(struct swjdp_common *swjdp,uint32_t ap_reg) { - u32 select; + uint32_t select; select = (ap_reg & 0x000000F0); if (select != swjdp->dp_select_value) @@ -324,36 +328,36 @@ int dap_dp_bankselect(swjdp_common_t *swjdp,u32 ap_reg) return ERROR_OK; } -int dap_ap_write_reg(swjdp_common_t *swjdp, u32 reg_addr, u8* out_value_buf) +int dap_ap_write_reg(struct swjdp_common *swjdp, uint32_t reg_addr, uint8_t* out_value_buf) { dap_dp_bankselect(swjdp, reg_addr); - scan_inout_check(swjdp, SWJDP_IR_APACC, reg_addr, DPAP_WRITE, out_value_buf, NULL); + scan_inout_check(swjdp, DAP_IR_APACC, reg_addr, DPAP_WRITE, out_value_buf, NULL); return ERROR_OK; } -int dap_ap_read_reg(swjdp_common_t *swjdp, u32 reg_addr, u8 *in_value_buf) +int dap_ap_read_reg(struct swjdp_common *swjdp, uint32_t reg_addr, uint8_t *in_value_buf) { dap_dp_bankselect(swjdp, reg_addr); - scan_inout_check(swjdp, SWJDP_IR_APACC, reg_addr, DPAP_READ, 0, in_value_buf); + scan_inout_check(swjdp, DAP_IR_APACC, reg_addr, DPAP_READ, 0, in_value_buf); return ERROR_OK; } -int dap_ap_write_reg_u32(swjdp_common_t *swjdp, u32 reg_addr, u32 value) +int dap_ap_write_reg_u32(struct swjdp_common *swjdp, uint32_t reg_addr, uint32_t value) { - u8 out_value_buf[4]; + uint8_t out_value_buf[4]; buf_set_u32(out_value_buf, 0, 32, value); dap_dp_bankselect(swjdp, reg_addr); - scan_inout_check(swjdp, SWJDP_IR_APACC, reg_addr, DPAP_WRITE, out_value_buf, NULL); + scan_inout_check(swjdp, DAP_IR_APACC, reg_addr, DPAP_WRITE, out_value_buf, NULL); return ERROR_OK; } -int dap_ap_read_reg_u32(swjdp_common_t *swjdp, u32 reg_addr, u32 *value) +int dap_ap_read_reg_u32(struct swjdp_common *swjdp, uint32_t reg_addr, uint32_t *value) { dap_dp_bankselect(swjdp, reg_addr); - scan_inout_check_u32(swjdp, SWJDP_IR_APACC, reg_addr, DPAP_READ, 0, value); + scan_inout_check_u32(swjdp, DAP_IR_APACC, reg_addr, DPAP_READ, 0, value); return ERROR_OK; } @@ -364,19 +368,19 @@ int dap_ap_read_reg_u32(swjdp_common_t *swjdp, u32 reg_addr, u32 *value) * * ***************************************************************************/ -int dap_setup_accessport(swjdp_common_t *swjdp, u32 csw, u32 tar) +int dap_setup_accessport(struct swjdp_common *swjdp, uint32_t csw, uint32_t tar) { csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT; if (csw != swjdp->ap_csw_value) { /* LOG_DEBUG("swjdp : Set CSW %x",csw); */ - dap_ap_write_reg_u32(swjdp, AP_REG_CSW, csw ); + dap_ap_write_reg_u32(swjdp, AP_REG_CSW, csw); swjdp->ap_csw_value = csw; } if (tar != swjdp->ap_tar_value) { /* LOG_DEBUG("swjdp : Set TAR %x",tar); */ - dap_ap_write_reg_u32(swjdp, AP_REG_TAR, tar ); + dap_ap_write_reg_u32(swjdp, AP_REG_TAR, tar); swjdp->ap_tar_value = tar; } if (csw & CSW_ADDRINC_MASK) @@ -389,23 +393,23 @@ int dap_setup_accessport(swjdp_common_t *swjdp, u32 csw, u32 tar) /***************************************************************************** * * -* mem_ap_read_u32(swjdp_common_t *swjdp, u32 address, u32 *value) * +* mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value) * * * -* Read a u32 value from memory or system register * -* Functionally equivalent to target_read_u32(target, address, u32 *value), * +* Read a uint32_t value from memory or system register * +* Functionally equivalent to target_read_u32(target, address, uint32_t *value), * * but with less overhead * *****************************************************************************/ -int mem_ap_read_u32(swjdp_common_t *swjdp, u32 address, u32 *value) +int mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value) { swjdp->trans_mode = TRANS_MODE_COMPOSITE; dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0); - dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value ); + dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value); return ERROR_OK; } -int mem_ap_read_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 *value) +int mem_ap_read_atomic_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value) { mem_ap_read_u32(swjdp, address, value); @@ -414,22 +418,22 @@ int mem_ap_read_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 *value) /***************************************************************************** * * -* mem_ap_write_u32(swjdp_common_t *swjdp, u32 address, u32 value) * +* mem_ap_write_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value) * * * -* Write a u32 value to memory or memory mapped register * +* Write a uint32_t value to memory or memory mapped register * * * *****************************************************************************/ -int mem_ap_write_u32(swjdp_common_t *swjdp, u32 address, u32 value) +int mem_ap_write_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value) { swjdp->trans_mode = TRANS_MODE_COMPOSITE; dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0); - dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value ); + dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value); return ERROR_OK; } -int mem_ap_write_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 value) +int mem_ap_write_atomic_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value) { mem_ap_write_u32(swjdp, address, value); @@ -438,16 +442,16 @@ int mem_ap_write_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 value) /***************************************************************************** * * -* mem_ap_write_buf(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address) * +* mem_ap_write_buf(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) * * * * Write a buffer in target order (little endian) * * * *****************************************************************************/ -int mem_ap_write_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address) +int mem_ap_write_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) { int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK; - u32 adr = address; - u8* pBuffer = buffer; + uint32_t adr = address; + uint8_t* pBuffer = buffer; swjdp->trans_mode = TRANS_MODE_COMPOSITE; @@ -460,23 +464,23 @@ int mem_ap_write_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 addre for (writecount = 0; writecount < count; writecount++) { int i; - u32 outvalue; - memcpy(&outvalue, pBuffer, sizeof(u32)); + uint32_t outvalue; + memcpy(&outvalue, pBuffer, sizeof(uint32_t)); - for (i = 0; i < 4; i++ ) + for (i = 0; i < 4; i++) { - *((u8*)pBuffer + (adr & 0x3)) = outvalue; + *((uint8_t*)pBuffer + (adr & 0x3)) = outvalue; outvalue >>= 8; adr++; } - pBuffer += sizeof(u32); + pBuffer += sizeof(uint32_t); } } while (wcount > 0) { - /* Adjust to write blocks within 4K aligned boundaries */ - blocksize = (0x1000 - (0xFFF & address)) >> 2; + /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/ + blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address); if (wcount < blocksize) blocksize = wcount; @@ -488,7 +492,7 @@ int mem_ap_write_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 addre for (writecount = 0; writecount < blocksize; writecount++) { - dap_ap_write_reg(swjdp, AP_REG_DRW, buffer + 4 * writecount ); + dap_ap_write_reg(swjdp, AP_REG_DRW, buffer + 4 * writecount); } if (swjdp_transaction_endcheck(swjdp) == ERROR_OK) @@ -504,7 +508,7 @@ int mem_ap_write_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 addre if (errorcount > 1) { - LOG_WARNING("Block write error address 0x%x, wcount 0x%x", address, wcount); + LOG_WARNING("Block write error address 0x%" PRIx32 ", wcount 0x%x", address, wcount); return ERROR_JTAG_DEVICE_ERROR; } } @@ -512,7 +516,7 @@ int mem_ap_write_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 addre return retval; } -int mem_ap_write_buf_packed_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address) +int mem_ap_write_buf_packed_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) { int retval = ERROR_OK; int wcount, blocksize, writecount, i; @@ -525,8 +529,8 @@ int mem_ap_write_buf_packed_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u3 { int nbytes; - /* Adjust to read within 4K block boundaries */ - blocksize = (0x1000 - (0xFFF & address)) >> 1; + /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/ + blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address); if (wcount < blocksize) blocksize = wcount; @@ -542,11 +546,11 @@ int mem_ap_write_buf_packed_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u3 { nbytes = MIN((writecount << 1), 4); - if (nbytes < 4 ) + if (nbytes < 4) { if (mem_ap_write_buf_u16(swjdp, buffer, nbytes, address) != ERROR_OK) { - LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count); + LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count); return ERROR_JTAG_DEVICE_ERROR; } @@ -554,21 +558,21 @@ int mem_ap_write_buf_packed_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u3 } else { - u32 outvalue; - memcpy(&outvalue, buffer, sizeof(u32)); + uint32_t outvalue; + memcpy(&outvalue, buffer, sizeof(uint32_t)); - for (i = 0; i < nbytes; i++ ) + for (i = 0; i < nbytes; i++) { - *((u8*)buffer + (address & 0x3)) = outvalue; + *((uint8_t*)buffer + (address & 0x3)) = outvalue; outvalue >>= 8; address++; } - memcpy(&outvalue, buffer, sizeof(u32)); + memcpy(&outvalue, buffer, sizeof(uint32_t)); dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue); if (swjdp_transaction_endcheck(swjdp) != ERROR_OK) { - LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count); + LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count); return ERROR_JTAG_DEVICE_ERROR; } } @@ -583,7 +587,7 @@ int mem_ap_write_buf_packed_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u3 return retval; } -int mem_ap_write_buf_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address) +int mem_ap_write_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) { int retval = ERROR_OK; @@ -595,10 +599,10 @@ int mem_ap_write_buf_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 addre while (count > 0) { dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address); - u16 svalue; - memcpy(&svalue, buffer, sizeof(u16)); - u32 outvalue = (u32)svalue << 8 * (address & 0x3); - dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue ); + uint16_t svalue; + memcpy(&svalue, buffer, sizeof(uint16_t)); + uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3); + dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue); retval = swjdp_transaction_endcheck(swjdp); count -= 2; address += 2; @@ -608,7 +612,7 @@ int mem_ap_write_buf_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 addre return retval; } -int mem_ap_write_buf_packed_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address) +int mem_ap_write_buf_packed_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) { int retval = ERROR_OK; int wcount, blocksize, writecount, i; @@ -621,8 +625,8 @@ int mem_ap_write_buf_packed_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 { int nbytes; - /* Adjust to read within 4K block boundaries */ - blocksize = (0x1000 - (0xFFF & address)); + /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/ + blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address); if (wcount < blocksize) blocksize = wcount; @@ -634,11 +638,11 @@ int mem_ap_write_buf_packed_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 { nbytes = MIN(writecount, 4); - if (nbytes < 4 ) + if (nbytes < 4) { if (mem_ap_write_buf_u8(swjdp, buffer, nbytes, address) != ERROR_OK) { - LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count); + LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count); return ERROR_JTAG_DEVICE_ERROR; } @@ -646,21 +650,21 @@ int mem_ap_write_buf_packed_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 } else { - u32 outvalue; - memcpy(&outvalue, buffer, sizeof(u32)); + uint32_t outvalue; + memcpy(&outvalue, buffer, sizeof(uint32_t)); - for (i = 0; i < nbytes; i++ ) + for (i = 0; i < nbytes; i++) { - *((u8*)buffer + (address & 0x3)) = outvalue; + *((uint8_t*)buffer + (address & 0x3)) = outvalue; outvalue >>= 8; address++; } - memcpy(&outvalue, buffer, sizeof(u32)); + memcpy(&outvalue, buffer, sizeof(uint32_t)); dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue); if (swjdp_transaction_endcheck(swjdp) != ERROR_OK) { - LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count); + LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count); return ERROR_JTAG_DEVICE_ERROR; } } @@ -675,7 +679,7 @@ int mem_ap_write_buf_packed_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 return retval; } -int mem_ap_write_buf_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address) +int mem_ap_write_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) { int retval = ERROR_OK; @@ -687,8 +691,8 @@ int mem_ap_write_buf_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 addres while (count > 0) { dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address); - u32 outvalue = (u32)*buffer << 8 * (address & 0x3); - dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue ); + uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3); + dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue); retval = swjdp_transaction_endcheck(swjdp); count--; address++; @@ -700,16 +704,16 @@ int mem_ap_write_buf_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 addres /********************************************************************************* * * -* mem_ap_read_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address) * +* mem_ap_read_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) * * * * Read block fast in target order (little endian) into a buffer * * * **********************************************************************************/ -int mem_ap_read_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address) +int mem_ap_read_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) { int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK; - u32 adr = address; - u8* pBuffer = buffer; + uint32_t adr = address; + uint8_t* pBuffer = buffer; swjdp->trans_mode = TRANS_MODE_COMPOSITE; @@ -718,8 +722,8 @@ int mem_ap_read_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 addres while (wcount > 0) { - /* Adjust to read within 4K block boundaries */ - blocksize = (0x1000 - (0xFFF & address)) >> 2; + /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/ + blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address); if (wcount < blocksize) blocksize = wcount; @@ -730,15 +734,15 @@ int mem_ap_read_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 addres dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address); /* Scan out first read */ - adi_jtag_dp_scan(swjdp->jtag_info, SWJDP_IR_APACC, AP_REG_DRW, DPAP_READ, 0, NULL, NULL); + adi_jtag_dp_scan(swjdp, DAP_IR_APACC, AP_REG_DRW, DPAP_READ, 0, NULL, NULL); for (readcount = 0; readcount < blocksize - 1; readcount++) { /* Scan out read instruction and scan in previous value */ - adi_jtag_dp_scan(swjdp->jtag_info, SWJDP_IR_APACC, AP_REG_DRW, DPAP_READ, 0, buffer + 4 * readcount, &swjdp->ack); + adi_jtag_dp_scan(swjdp, DAP_IR_APACC, AP_REG_DRW, DPAP_READ, 0, buffer + 4 * readcount, &swjdp->ack); } /* Scan in last value */ - adi_jtag_dp_scan(swjdp->jtag_info, SWJDP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, buffer + 4 * readcount, &swjdp->ack); + adi_jtag_dp_scan(swjdp, DAP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, buffer + 4 * readcount, &swjdp->ack); if (swjdp_transaction_endcheck(swjdp) == ERROR_OK) { wcount = wcount - blocksize; @@ -752,7 +756,7 @@ int mem_ap_read_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 addres if (errorcount > 1) { - LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count); + LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count); return ERROR_JTAG_DEVICE_ERROR; } } @@ -763,12 +767,12 @@ int mem_ap_read_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 addres for (readcount = 0; readcount < count; readcount++) { int i; - u32 data; - memcpy(&data, pBuffer, sizeof(u32)); + uint32_t data; + memcpy(&data, pBuffer, sizeof(uint32_t)); - for (i = 0; i < 4; i++ ) + for (i = 0; i < 4; i++) { - *((u8*)pBuffer) = (data >> 8 * (adr & 0x3)); + *((uint8_t*)pBuffer) = (data >> 8 * (adr & 0x3)); pBuffer++; adr++; } @@ -778,9 +782,9 @@ int mem_ap_read_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 addres return retval; } -int mem_ap_read_buf_packed_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address) +int mem_ap_read_buf_packed_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) { - u32 invalue; + uint32_t invalue; int retval = ERROR_OK; int wcount, blocksize, readcount, i; @@ -792,8 +796,8 @@ int mem_ap_read_buf_packed_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 { int nbytes; - /* Adjust to read within 4K block boundaries */ - blocksize = (0x1000 - (0xFFF & address)) >> 1; + /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/ + blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address); if (wcount < blocksize) blocksize = wcount; @@ -806,18 +810,18 @@ int mem_ap_read_buf_packed_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 do { - dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue ); + dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue); if (swjdp_transaction_endcheck(swjdp) != ERROR_OK) { - LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count); + LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count); return ERROR_JTAG_DEVICE_ERROR; } nbytes = MIN((readcount << 1), 4); - for (i = 0; i < nbytes; i++ ) + for (i = 0; i < nbytes; i++) { - *((u8*)buffer) = (invalue >> 8 * (address & 0x3)); + *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3)); buffer++; address++; } @@ -830,9 +834,9 @@ int mem_ap_read_buf_packed_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 return retval; } -int mem_ap_read_buf_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address) +int mem_ap_read_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) { - u32 invalue, i; + uint32_t invalue, i; int retval = ERROR_OK; if (count >= 4) @@ -843,21 +847,21 @@ int mem_ap_read_buf_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 addres while (count > 0) { dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address); - dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue ); + dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue); retval = swjdp_transaction_endcheck(swjdp); if (address & 0x1) { - for (i = 0; i < 2; i++ ) + for (i = 0; i < 2; i++) { - *((u8*)buffer) = (invalue >> 8 * (address & 0x3)); + *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3)); buffer++; address++; } } else { - u16 svalue = (invalue >> 8 * (address & 0x3)); - memcpy(buffer, &svalue, sizeof(u16)); + uint16_t svalue = (invalue >> 8 * (address & 0x3)); + memcpy(buffer, &svalue, sizeof(uint16_t)); address += 2; buffer += 2; } @@ -867,9 +871,15 @@ int mem_ap_read_buf_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 addres return retval; } -int mem_ap_read_buf_packed_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address) +/* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many + * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s? + * + * The solution is to arrange for a large out/in scan in this loop and + * and convert data afterwards. + */ +int mem_ap_read_buf_packed_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) { - u32 invalue; + uint32_t invalue; int retval = ERROR_OK; int wcount, blocksize, readcount, i; @@ -881,8 +891,8 @@ int mem_ap_read_buf_packed_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 { int nbytes; - /* Adjust to read within 4K block boundaries */ - blocksize = (0x1000 - (0xFFF & address)); + /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/ + blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address); if (wcount < blocksize) blocksize = wcount; @@ -892,18 +902,18 @@ int mem_ap_read_buf_packed_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 do { - dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue ); + dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue); if (swjdp_transaction_endcheck(swjdp) != ERROR_OK) { - LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count); + LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count); return ERROR_JTAG_DEVICE_ERROR; } nbytes = MIN(readcount, 4); - for (i = 0; i < nbytes; i++ ) + for (i = 0; i < nbytes; i++) { - *((u8*)buffer) = (invalue >> 8 * (address & 0x3)); + *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3)); buffer++; address++; } @@ -916,9 +926,9 @@ int mem_ap_read_buf_packed_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 return retval; } -int mem_ap_read_buf_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address) +int mem_ap_read_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) { - u32 invalue; + uint32_t invalue; int retval = ERROR_OK; if (count >= 4) @@ -929,9 +939,9 @@ int mem_ap_read_buf_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address while (count > 0) { dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address); - dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue ); + dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue); retval = swjdp_transaction_endcheck(swjdp); - *((u8*)buffer) = (invalue >> 8 * (address & 0x3)); + *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3)); count--; address++; buffer++; @@ -940,10 +950,10 @@ int mem_ap_read_buf_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address return retval; } -int ahbap_debugport_init(swjdp_common_t *swjdp) +int ahbap_debugport_init(struct swjdp_common *swjdp) { - u32 idreg, romaddr, dummy; - u32 ctrlstat; + uint32_t idreg, romaddr, dummy; + uint32_t ctrlstat; int cnt = 0; int retval; @@ -961,7 +971,7 @@ int ahbap_debugport_init(swjdp_common_t *swjdp) dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT); dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT); - if ((retval=jtag_execute_queue())!=ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) return retval; /* Check that we have debug power domains activated */ @@ -969,7 +979,7 @@ int ahbap_debugport_init(swjdp_common_t *swjdp) { LOG_DEBUG("swjdp: wait CDBGPWRUPACK"); dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT); - if ((retval=jtag_execute_queue())!=ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) return retval; alive_sleep(10); } @@ -978,7 +988,7 @@ int ahbap_debugport_init(swjdp_common_t *swjdp) { LOG_DEBUG("swjdp: wait CSYSPWRUPACK"); dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT); - if ((retval=jtag_execute_queue())!=ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) return retval; alive_sleep(10); } @@ -992,24 +1002,33 @@ int ahbap_debugport_init(swjdp_common_t *swjdp) dap_ap_read_reg_u32(swjdp, 0xFC, &idreg); dap_ap_read_reg_u32(swjdp, 0xF8, &romaddr); - LOG_DEBUG("AHB-AP ID Register 0x%x, Debug ROM Address 0x%x", idreg, romaddr); + LOG_DEBUG("AHB-AP ID Register 0x%" PRIx32 ", Debug ROM Address 0x%" PRIx32 "", idreg, romaddr); return ERROR_OK; } +/* CID interpretation -- see ARM IHI 0029B section 3 */ +static const char *class_description[16] ={ + "Reserved", "ROM table", "Reserved", "Reserved", + "Reserved", "Reserved", "Reserved", "Reserved", + "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block", + "Reserved", "DESS", "Generic IP component", "PrimeCell or System component" +}; -char * class_description[16] ={ - "Reserved", - "ROM table","Reserved","Reserved","Reserved","Reserved","Reserved","Reserved","Reserved", - "CoreSight component","Reserved","Peripheral Test Block","Reserved","DESS","Generic IP component","Non standard layout"}; +static bool +is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0) +{ + return cid3 == 0xb1 && cid2 == 0x05 + && ((cid1 & 0x0f) == 0) && cid0 == 0x0d; +} -int dap_info_command(struct command_context_s *cmd_ctx, swjdp_common_t *swjdp, int apsel) +int dap_info_command(struct command_context *cmd_ctx, struct swjdp_common *swjdp, int apsel) { - u32 dbgbase,apid; + uint32_t dbgbase,apid; int romtable_present = 0; - u8 mem_ap; - u32 apselold; + uint8_t mem_ap; + uint32_t apselold; apselold = swjdp->apsel; dap_ap_select(swjdp, apsel); @@ -1017,8 +1036,8 @@ int dap_info_command(struct command_context_s *cmd_ctx, swjdp_common_t *swjdp, i dap_ap_read_reg_u32(swjdp, 0xFC, &apid); swjdp_transaction_endcheck(swjdp); /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */ - mem_ap = ((apid&0x10000)&&((apid&0x0F)!=0)); - command_print(cmd_ctx, "ap identification register 0x%8.8x", apid); + mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0)); + command_print(cmd_ctx, "ap identification register 0x%8.8" PRIx32 "", apid); if (apid) { switch (apid&0x0F) @@ -1036,69 +1055,295 @@ int dap_info_command(struct command_context_s *cmd_ctx, swjdp_common_t *swjdp, i command_print(cmd_ctx, "\tUnknown AP-type"); break; } - command_print(cmd_ctx, "ap debugbase 0x%8.8x", dbgbase); + command_print(cmd_ctx, "ap debugbase 0x%8.8" PRIx32 "", dbgbase); } else { command_print(cmd_ctx, "No AP found at this apsel 0x%x", apsel); } - romtable_present = ((mem_ap)&&(dbgbase != 0xFFFFFFFF)); + romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF)); if (romtable_present) { - u32 cid0,cid1,cid2,cid3,memtype,romentry; - u16 entry_offset; + uint32_t cid0,cid1,cid2,cid3,memtype,romentry; + uint16_t entry_offset; + /* bit 16 of apid indicates a memory access port */ - if (dbgbase&0x02) - { + if (dbgbase & 0x02) command_print(cmd_ctx, "\tValid ROM table present"); - } else - { - command_print(cmd_ctx, "\tROM table in legacy format" ); - } + command_print(cmd_ctx, "\tROM table in legacy format"); + /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */ - mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFF0, &cid0); - mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFF4, &cid1); - mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFF8, &cid2); - mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFFC, &cid3); - mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFCC, &memtype); + mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF0, &cid0); + mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF4, &cid1); + mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF8, &cid2); + mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFFC, &cid3); + mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFCC, &memtype); swjdp_transaction_endcheck(swjdp); - command_print(cmd_ctx, "\tCID3 0x%x, CID2 0x%x, CID1 0x%x, CID0, 0x%x",cid3,cid2,cid1,cid0); - if (memtype&0x01) - { + if (!is_dap_cid_ok(cid3, cid2, cid1, cid0)) + command_print(cmd_ctx, "\tCID3 0x%2.2" PRIx32 + ", CID2 0x%2.2" PRIx32 + ", CID1 0x%2.2" PRIx32 + ", CID0 0x%2.2" PRIx32, + cid3, cid2, cid1, cid0); + if (memtype & 0x01) command_print(cmd_ctx, "\tMEMTYPE system memory present on bus"); - } else - { - command_print(cmd_ctx, "\tMEMTYPE system memory not present. Dedicated debug bus" ); - } + command_print(cmd_ctx, "\tMEMTYPE System memory not present. " + "Dedicated debug bus."); - /* Now we read ROM table entries from dbgbase&0xFFFFF000)|0x000 until we get 0x00000000 */ + /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */ entry_offset = 0; do { - mem_ap_read_atomic_u32(swjdp, (dbgbase&0xFFFFF000)|entry_offset, &romentry); - command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%x",entry_offset,romentry); + mem_ap_read_atomic_u32(swjdp, (dbgbase&0xFFFFF000) | entry_offset, &romentry); + command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "",entry_offset,romentry); if (romentry&0x01) { - u32 c_cid0,c_cid1,c_cid2,c_cid3,c_pid0,c_pid1,c_pid2,c_pid3,c_pid4,component_start; - u32 component_base = (u32)((dbgbase&0xFFFFF000)+(int)(romentry&0xFFFFF000)); - mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFE0, &c_pid0); - mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFE4, &c_pid1); - mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFE8, &c_pid2); - mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFEC, &c_pid3); - mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFD0, &c_pid4); - mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFF0, &c_cid0); - mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFF4, &c_cid1); - mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFF8, &c_cid2); - mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFFC, &c_cid3); - component_start = component_base - 0x1000*(c_pid4>>4); - command_print(cmd_ctx, "\t\tComponent base address 0x%x, pid4 0x%x, start address 0x%x",component_base,c_pid4,component_start); - command_print(cmd_ctx, "\t\tComponent cid1 0x%x, class is %s",c_cid1,class_description[(c_cid1>>4)&0xF]); /* Se ARM DDI 0314 C Table 2.2 */ - command_print(cmd_ctx, "\t\tCID3 0x%x, CID2 0x%x, CID1 0x%x, CID0, 0x%x",c_cid3,c_cid2,c_cid1,c_cid0); - command_print(cmd_ctx, "\t\tPID3 0x%x, PID2 0x%x, PID1 0x%x, PID0, 0x%x",c_pid3,c_pid2,c_pid1,c_pid0); - /* For CoreSight components, (c_cid1>>4)&0xF==9 , we also read 0xFC8 DevId and 0xFCC DevType */ + uint32_t c_cid0, c_cid1, c_cid2, c_cid3; + uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4; + uint32_t component_start, component_base; + unsigned part_num; + char *type, *full; + + component_base = (uint32_t)((dbgbase & 0xFFFFF000) + + (int)(romentry & 0xFFFFF000)); + mem_ap_read_atomic_u32(swjdp, + (component_base & 0xFFFFF000) | 0xFE0, &c_pid0); + mem_ap_read_atomic_u32(swjdp, + (component_base & 0xFFFFF000) | 0xFE4, &c_pid1); + mem_ap_read_atomic_u32(swjdp, + (component_base & 0xFFFFF000) | 0xFE8, &c_pid2); + mem_ap_read_atomic_u32(swjdp, + (component_base & 0xFFFFF000) | 0xFEC, &c_pid3); + mem_ap_read_atomic_u32(swjdp, + (component_base & 0xFFFFF000) | 0xFD0, &c_pid4); + mem_ap_read_atomic_u32(swjdp, + (component_base & 0xFFFFF000) | 0xFF0, &c_cid0); + mem_ap_read_atomic_u32(swjdp, + (component_base & 0xFFFFF000) | 0xFF4, &c_cid1); + mem_ap_read_atomic_u32(swjdp, + (component_base & 0xFFFFF000) | 0xFF8, &c_cid2); + mem_ap_read_atomic_u32(swjdp, + (component_base & 0xFFFFF000) | 0xFFC, &c_cid3); + component_start = component_base - 0x1000*(c_pid4 >> 4); + + command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32 + ", start address 0x%" PRIx32, + component_base, component_start); + command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s", + (int) (c_cid1 >> 4) & 0xf, + /* See ARM IHI 0029B Table 3-3 */ + class_description[(c_cid1 >> 4) & 0xf]); + + /* CoreSight component? */ + if (((c_cid1 >> 4) & 0x0f) == 9) { + uint32_t devtype; + unsigned minor; + char *major = "Reserved", *subtype = "Reserved"; + + mem_ap_read_atomic_u32(swjdp, + (component_base & 0xfffff000) | 0xfcc, + &devtype); + minor = (devtype >> 4) & 0x0f; + switch (devtype & 0x0f) { + case 0: + major = "Miscellaneous"; + switch (minor) { + case 0: + subtype = "other"; + break; + case 4: + subtype = "Validation component"; + break; + } + break; + case 1: + major = "Trace Sink"; + switch (minor) { + case 0: + subtype = "other"; + break; + case 1: + subtype = "Port"; + break; + case 2: + subtype = "Buffer"; + break; + } + break; + case 2: + major = "Trace Link"; + switch (minor) { + case 0: + subtype = "other"; + break; + case 1: + subtype = "Funnel, router"; + break; + case 2: + subtype = "Filter"; + break; + case 3: + subtype = "FIFO, buffer"; + break; + } + break; + case 3: + major = "Trace Source"; + switch (minor) { + case 0: + subtype = "other"; + break; + case 1: + subtype = "Processor"; + break; + case 2: + subtype = "DSP"; + break; + case 3: + subtype = "Engine/Coprocessor"; + break; + case 4: + subtype = "Bus"; + break; + } + break; + case 4: + major = "Debug Control"; + switch (minor) { + case 0: + subtype = "other"; + break; + case 1: + subtype = "Trigger Matrix"; + break; + case 2: + subtype = "Debug Auth"; + break; + } + break; + case 5: + major = "Debug Logic"; + switch (minor) { + case 0: + subtype = "other"; + break; + case 1: + subtype = "Processor"; + break; + case 2: + subtype = "DSP"; + break; + case 3: + subtype = "Engine/Coprocessor"; + break; + } + break; + } + command_print(cmd_ctx, "\t\tType is 0x%2.2x, %s, %s", + (unsigned) (devtype & 0xff), + major, subtype); + /* REVISIT also show 0xfc8 DevId */ + } + + if (!is_dap_cid_ok(cid3, cid2, cid1, cid0)) + command_print(cmd_ctx, "\t\tCID3 0x%2.2" PRIx32 + ", CID2 0x%2.2" PRIx32 + ", CID1 0x%2.2" PRIx32 + ", CID0 0x%2.2" PRIx32, + c_cid3, c_cid2, c_cid1, c_cid0); + command_print(cmd_ctx, "\t\tPeripheral ID[4..0] = hex " + "%2.2x %2.2x %2.2x %2.2x %2.2x", + (int) c_pid4, + (int) c_pid3, (int) c_pid2, + (int) c_pid1, (int) c_pid0); + + /* Part number interpretations are from Cortex + * core specs, the CoreSight components TRM + * (ARM DDI 0314H), and ETM specs; also from + * chip observation (e.g. TI SDTI). + */ + part_num = c_pid0 & 0xff; + part_num |= (c_pid1 & 0x0f) << 8; + switch (part_num) { + case 0x000: + type = "Cortex-M3 NVIC"; + full = "(Interrupt Controller)"; + break; + case 0x001: + type = "Cortex-M3 ITM"; + full = "(Instrumentation Trace Module)"; + break; + case 0x002: + type = "Cortex-M3 DWT"; + full = "(Data Watchpoint and Trace)"; + break; + case 0x003: + type = "Cortex-M3 FBP"; + full = "(Flash Patch and Breakpoint)"; + break; + case 0x00d: + type = "CoreSight ETM11"; + full = "(Embedded Trace)"; + break; + // case 0x113: what? + case 0x120: /* from OMAP3 memmap */ + type = "TI SDTI"; + full = "(System Debug Trace Interface)"; + break; + case 0x343: /* from OMAP3 memmap */ + type = "TI DAPCTL"; + full = ""; + break; + case 0x4e0: + type = "Cortex-M3 ETM"; + full = "(Embedded Trace)"; + break; + case 0x906: + type = "Coresight CTI"; + full = "(Cross Trigger)"; + break; + case 0x907: + type = "Coresight ETB"; + full = "(Trace Buffer)"; + break; + case 0x908: + type = "Coresight CSTF"; + full = "(Trace Funnel)"; + break; + case 0x910: + type = "CoreSight ETM9"; + full = "(Embedded Trace)"; + break; + case 0x912: + type = "Coresight TPIU"; + full = "(Trace Port Interface Unit)"; + break; + case 0x921: + type = "Cortex-A8 ETM"; + full = "(Embedded Trace)"; + break; + case 0x922: + type = "Cortex-A8 CTI"; + full = "(Cross Trigger)"; + break; + case 0x923: + type = "Cortex-M3 TPIU"; + full = "(Trace Port Interface Unit)"; + break; + case 0xc08: + type = "Cortex-A8 Debug"; + full = "(Debug Unit)"; + break; + default: + type = "-*- unrecognized -*-"; + full = ""; + break; + } + command_print(cmd_ctx, "\t\tPart is %s %s", + type, full); } else { @@ -1108,7 +1353,7 @@ int dap_info_command(struct command_context_s *cmd_ctx, swjdp_common_t *swjdp, i command_print(cmd_ctx, "\t\tEnd of ROM table"); } entry_offset += 4; - } while (romentry>0); + } while (romentry > 0); } else { @@ -1119,3 +1364,108 @@ int dap_info_command(struct command_context_s *cmd_ctx, swjdp_common_t *swjdp, i return ERROR_OK; } +DAP_COMMAND_HANDLER(dap_baseaddr_command) +{ + uint32_t apsel, apselsave, baseaddr; + int retval; + + apselsave = swjdp->apsel; + switch (CMD_ARGC) { + case 0: + apsel = swjdp->apsel; + break; + case 1: + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel); + break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; + } + + if (apselsave != apsel) + dap_ap_select(swjdp, apsel); + + dap_ap_read_reg_u32(swjdp, 0xF8, &baseaddr); + retval = swjdp_transaction_endcheck(swjdp); + command_print(cmd_ctx, "0x%8.8" PRIx32, baseaddr); + + if (apselsave != apsel) + dap_ap_select(swjdp, apselsave); + + return retval; +} + +DAP_COMMAND_HANDLER(dap_memaccess_command) +{ + uint32_t memaccess_tck; + + switch (CMD_ARGC) { + case 0: + memaccess_tck = swjdp->memaccess_tck; + break; + case 1: + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck); + break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; + } + swjdp->memaccess_tck = memaccess_tck; + + command_print(cmd_ctx, "memory bus access delay set to %" PRIi32 " tck", + swjdp->memaccess_tck); + + return ERROR_OK; +} + +DAP_COMMAND_HANDLER(dap_apsel_command) +{ + uint32_t apsel, apid; + int retval; + + switch (CMD_ARGC) { + case 0: + apsel = 0; + break; + case 1: + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel); + break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; + } + + dap_ap_select(swjdp, apsel); + dap_ap_read_reg_u32(swjdp, 0xFC, &apid); + retval = swjdp_transaction_endcheck(swjdp); + command_print(cmd_ctx, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32, + apsel, apid); + + return retval; +} + +DAP_COMMAND_HANDLER(dap_apid_command) +{ + uint32_t apsel, apselsave, apid; + int retval; + + apselsave = swjdp->apsel; + switch (CMD_ARGC) { + case 0: + apsel = swjdp->apsel; + break; + case 1: + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel); + break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; + } + + if (apselsave != apsel) + dap_ap_select(swjdp, apsel); + + dap_ap_read_reg_u32(swjdp, 0xFC, &apid); + retval = swjdp_transaction_endcheck(swjdp); + command_print(cmd_ctx, "0x%8.8" PRIx32, apid); + if (apselsave != apsel) + dap_ap_select(swjdp, apselsave); + + return retval; +}