X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm_adi_v5.c;h=3d0b8f8146dce2de11cba19fc234a0e8a7b98868;hp=a58c0a7cbf0279ab996e38a73ae3f70790e20833;hb=2861877b32a7a2f4022a1c3d9b66c9b4879878ac;hpb=aea6815462d3302f7f8b6576f59320d5f5985642 diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c index a58c0a7cbf..3d0b8f8146 100644 --- a/src/target/arm_adi_v5.c +++ b/src/target/arm_adi_v5.c @@ -29,8 +29,8 @@ * * * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A * * * - * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316A * - * Cortex-M3(tm) TRM, ARM DDI 0337C * + * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D * + * Cortex-M3(tm) TRM, ARM DDI 0337G * * * ***************************************************************************/ @@ -71,17 +71,17 @@ static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address ***************************************************************************/ /* Scan out and in from target ordered uint8_t buffers */ -int adi_jtag_dp_scan(swjdp_common_t *swjdp, uint8_t instr, uint8_t reg_addr, uint8_t RnW, uint8_t *outvalue, uint8_t *invalue, uint8_t *ack) +int adi_jtag_dp_scan(struct swjdp_common *swjdp, uint8_t instr, uint8_t reg_addr, uint8_t RnW, uint8_t *outvalue, uint8_t *invalue, uint8_t *ack) { - arm_jtag_t *jtag_info = swjdp->jtag_info; - scan_field_t fields[2]; + struct arm_jtag *jtag_info = swjdp->jtag_info; + struct scan_field fields[2]; uint8_t out_addr_buf; jtag_set_end_state(TAP_IDLE); arm_jtag_set_instr(jtag_info, instr, NULL); /* Add specified number of tck clocks before accessing memory bus */ - if ((instr == DAP_IR_APACC) && ((reg_addr == AP_REG_DRW)||((reg_addr&0xF0) == AP_REG_BD0) )&& (swjdp->memaccess_tck != 0)) + if ((instr == DAP_IR_APACC) && ((reg_addr == AP_REG_DRW)||((reg_addr&0xF0) == AP_REG_BD0))&& (swjdp->memaccess_tck != 0)) jtag_add_runtest(swjdp->memaccess_tck, jtag_set_end_state(TAP_IDLE)); fields[0].tap = jtag_info->tap; @@ -101,10 +101,10 @@ int adi_jtag_dp_scan(swjdp_common_t *swjdp, uint8_t instr, uint8_t reg_addr, uin } /* Scan out and in from host ordered uint32_t variables */ -int adi_jtag_dp_scan_u32(swjdp_common_t *swjdp, uint8_t instr, uint8_t reg_addr, uint8_t RnW, uint32_t outvalue, uint32_t *invalue, uint8_t *ack) +int adi_jtag_dp_scan_u32(struct swjdp_common *swjdp, uint8_t instr, uint8_t reg_addr, uint8_t RnW, uint32_t outvalue, uint32_t *invalue, uint8_t *ack) { - arm_jtag_t *jtag_info = swjdp->jtag_info; - scan_field_t fields[2]; + struct arm_jtag *jtag_info = swjdp->jtag_info; + struct scan_field fields[2]; uint8_t out_value_buf[4]; uint8_t out_addr_buf; @@ -112,7 +112,7 @@ int adi_jtag_dp_scan_u32(swjdp_common_t *swjdp, uint8_t instr, uint8_t reg_addr, arm_jtag_set_instr(jtag_info, instr, NULL); /* Add specified number of tck clocks before accessing memory bus */ - if ((instr == DAP_IR_APACC) && ((reg_addr == AP_REG_DRW)||((reg_addr&0xF0) == AP_REG_BD0) )&& (swjdp->memaccess_tck != 0)) + if ((instr == DAP_IR_APACC) && ((reg_addr == AP_REG_DRW)||((reg_addr&0xF0) == AP_REG_BD0))&& (swjdp->memaccess_tck != 0)) jtag_add_runtest(swjdp->memaccess_tck, jtag_set_end_state(TAP_IDLE)); fields[0].tap = jtag_info->tap; @@ -143,7 +143,7 @@ int adi_jtag_dp_scan_u32(swjdp_common_t *swjdp, uint8_t instr, uint8_t reg_addr, } /* scan_inout_check adds one extra inscan for DPAP_READ commands to read variables */ -int scan_inout_check(swjdp_common_t *swjdp, uint8_t instr, uint8_t reg_addr, uint8_t RnW, uint8_t *outvalue, uint8_t *invalue) +int scan_inout_check(struct swjdp_common *swjdp, uint8_t instr, uint8_t reg_addr, uint8_t RnW, uint8_t *outvalue, uint8_t *invalue) { adi_jtag_dp_scan(swjdp, instr, reg_addr, RnW, outvalue, NULL, NULL); @@ -152,7 +152,7 @@ int scan_inout_check(swjdp_common_t *swjdp, uint8_t instr, uint8_t reg_addr, uin adi_jtag_dp_scan(swjdp, DAP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack); } - /* In TRANS_MODE_ATOMIC all DAP_IR_APACC transactions wait for ack=OK/FAULT and the check CTRL_STAT */ + /* In TRANS_MODE_ATOMIC all DAP_IR_APACC transactions wait for ack = OK/FAULT and the check CTRL_STAT */ if ((instr == DAP_IR_APACC) && (swjdp->trans_mode == TRANS_MODE_ATOMIC)) { return swjdp_transaction_endcheck(swjdp); @@ -161,16 +161,16 @@ int scan_inout_check(swjdp_common_t *swjdp, uint8_t instr, uint8_t reg_addr, uin return ERROR_OK; } -int scan_inout_check_u32(swjdp_common_t *swjdp, uint8_t instr, uint8_t reg_addr, uint8_t RnW, uint32_t outvalue, uint32_t *invalue) +int scan_inout_check_u32(struct swjdp_common *swjdp, uint8_t instr, uint8_t reg_addr, uint8_t RnW, uint32_t outvalue, uint32_t *invalue) { adi_jtag_dp_scan_u32(swjdp, instr, reg_addr, RnW, outvalue, NULL, NULL); - if ((RnW==DPAP_READ) && (invalue != NULL)) + if ((RnW == DPAP_READ) && (invalue != NULL)) { adi_jtag_dp_scan_u32(swjdp, DAP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack); } - /* In TRANS_MODE_ATOMIC all DAP_IR_APACC transactions wait for ack=OK/FAULT and then check CTRL_STAT */ + /* In TRANS_MODE_ATOMIC all DAP_IR_APACC transactions wait for ack = OK/FAULT and then check CTRL_STAT */ if ((instr == DAP_IR_APACC) && (swjdp->trans_mode == TRANS_MODE_ATOMIC)) { return swjdp_transaction_endcheck(swjdp); @@ -179,7 +179,7 @@ int scan_inout_check_u32(swjdp_common_t *swjdp, uint8_t instr, uint8_t reg_addr, return ERROR_OK; } -int swjdp_transaction_endcheck(swjdp_common_t *swjdp) +int swjdp_transaction_endcheck(struct swjdp_common *swjdp) { int retval; uint32_t ctrlstat; @@ -195,7 +195,7 @@ int swjdp_transaction_endcheck(swjdp_common_t *swjdp) https://lists.berlios.de/pipermail/openocd-development/2008-September/003107.html */ - if ((retval=jtag_execute_queue()) != ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) { LOG_ERROR("BUG: Why does this fail the first time????"); } @@ -203,14 +203,14 @@ int swjdp_transaction_endcheck(swjdp_common_t *swjdp) #endif scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat); - if ((retval=jtag_execute_queue()) != ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) return retval; swjdp->ack = swjdp->ack & 0x7; if (swjdp->ack != 2) { - long long then=timeval_ms(); + long long then = timeval_ms(); while (swjdp->ack != 2) { if (swjdp->ack == 1) @@ -228,7 +228,7 @@ int swjdp_transaction_endcheck(swjdp_common_t *swjdp) } scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat); - if ((retval=jtag_execute_queue()) != ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) return retval; swjdp->ack = swjdp->ack & 0x7; } @@ -261,19 +261,19 @@ int swjdp_transaction_endcheck(swjdp_common_t *swjdp) /* Clear Sticky Error Bits */ scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_WRITE, swjdp->dp_ctrl_stat | SSTICKYORUN | SSTICKYERR, NULL); scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat); - if ((retval=jtag_execute_queue()) != ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) return retval; LOG_DEBUG("swjdp: status 0x%" PRIx32 "", ctrlstat); dap_ap_read_reg_u32(swjdp, AP_REG_CSW, &mem_ap_csw); dap_ap_read_reg_u32(swjdp, AP_REG_TAR, &mem_ap_tar); - if ((retval=jtag_execute_queue()) != ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) return retval; LOG_ERROR("Read MEM_AP_CSW 0x%" PRIx32 ", MEM_AP_TAR 0x%" PRIx32 "", mem_ap_csw, mem_ap_tar); } - if ((retval=jtag_execute_queue()) != ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) return retval; return ERROR_JTAG_DEVICE_ERROR; } @@ -287,17 +287,17 @@ int swjdp_transaction_endcheck(swjdp_common_t *swjdp) * * ***************************************************************************/ -int dap_dp_write_reg(swjdp_common_t *swjdp, uint32_t value, uint8_t reg_addr) +int dap_dp_write_reg(struct swjdp_common *swjdp, uint32_t value, uint8_t reg_addr) { return scan_inout_check_u32(swjdp, DAP_IR_DPACC, reg_addr, DPAP_WRITE, value, NULL); } -int dap_dp_read_reg(swjdp_common_t *swjdp, uint32_t *value, uint8_t reg_addr) +int dap_dp_read_reg(struct swjdp_common *swjdp, uint32_t *value, uint8_t reg_addr) { return scan_inout_check_u32(swjdp, DAP_IR_DPACC, reg_addr, DPAP_READ, 0, value); } -int dap_ap_select(swjdp_common_t *swjdp,uint8_t apsel) +int dap_ap_select(struct swjdp_common *swjdp,uint8_t apsel) { uint32_t select; select = (apsel << 24) & 0xFF000000; @@ -314,7 +314,7 @@ int dap_ap_select(swjdp_common_t *swjdp,uint8_t apsel) return ERROR_OK; } -int dap_dp_bankselect(swjdp_common_t *swjdp,uint32_t ap_reg) +int dap_dp_bankselect(struct swjdp_common *swjdp,uint32_t ap_reg) { uint32_t select; select = (ap_reg & 0x000000F0); @@ -328,7 +328,7 @@ int dap_dp_bankselect(swjdp_common_t *swjdp,uint32_t ap_reg) return ERROR_OK; } -int dap_ap_write_reg(swjdp_common_t *swjdp, uint32_t reg_addr, uint8_t* out_value_buf) +int dap_ap_write_reg(struct swjdp_common *swjdp, uint32_t reg_addr, uint8_t* out_value_buf) { dap_dp_bankselect(swjdp, reg_addr); scan_inout_check(swjdp, DAP_IR_APACC, reg_addr, DPAP_WRITE, out_value_buf, NULL); @@ -336,14 +336,14 @@ int dap_ap_write_reg(swjdp_common_t *swjdp, uint32_t reg_addr, uint8_t* out_valu return ERROR_OK; } -int dap_ap_read_reg(swjdp_common_t *swjdp, uint32_t reg_addr, uint8_t *in_value_buf) +int dap_ap_read_reg(struct swjdp_common *swjdp, uint32_t reg_addr, uint8_t *in_value_buf) { dap_dp_bankselect(swjdp, reg_addr); scan_inout_check(swjdp, DAP_IR_APACC, reg_addr, DPAP_READ, 0, in_value_buf); return ERROR_OK; } -int dap_ap_write_reg_u32(swjdp_common_t *swjdp, uint32_t reg_addr, uint32_t value) +int dap_ap_write_reg_u32(struct swjdp_common *swjdp, uint32_t reg_addr, uint32_t value) { uint8_t out_value_buf[4]; @@ -354,7 +354,7 @@ int dap_ap_write_reg_u32(swjdp_common_t *swjdp, uint32_t reg_addr, uint32_t valu return ERROR_OK; } -int dap_ap_read_reg_u32(swjdp_common_t *swjdp, uint32_t reg_addr, uint32_t *value) +int dap_ap_read_reg_u32(struct swjdp_common *swjdp, uint32_t reg_addr, uint32_t *value) { dap_dp_bankselect(swjdp, reg_addr); scan_inout_check_u32(swjdp, DAP_IR_APACC, reg_addr, DPAP_READ, 0, value); @@ -368,19 +368,19 @@ int dap_ap_read_reg_u32(swjdp_common_t *swjdp, uint32_t reg_addr, uint32_t *valu * * ***************************************************************************/ -int dap_setup_accessport(swjdp_common_t *swjdp, uint32_t csw, uint32_t tar) +int dap_setup_accessport(struct swjdp_common *swjdp, uint32_t csw, uint32_t tar) { csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT; if (csw != swjdp->ap_csw_value) { /* LOG_DEBUG("swjdp : Set CSW %x",csw); */ - dap_ap_write_reg_u32(swjdp, AP_REG_CSW, csw ); + dap_ap_write_reg_u32(swjdp, AP_REG_CSW, csw); swjdp->ap_csw_value = csw; } if (tar != swjdp->ap_tar_value) { /* LOG_DEBUG("swjdp : Set TAR %x",tar); */ - dap_ap_write_reg_u32(swjdp, AP_REG_TAR, tar ); + dap_ap_write_reg_u32(swjdp, AP_REG_TAR, tar); swjdp->ap_tar_value = tar; } if (csw & CSW_ADDRINC_MASK) @@ -393,23 +393,23 @@ int dap_setup_accessport(swjdp_common_t *swjdp, uint32_t csw, uint32_t tar) /***************************************************************************** * * -* mem_ap_read_u32(swjdp_common_t *swjdp, uint32_t address, uint32_t *value) * +* mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value) * * * * Read a uint32_t value from memory or system register * * Functionally equivalent to target_read_u32(target, address, uint32_t *value), * * but with less overhead * *****************************************************************************/ -int mem_ap_read_u32(swjdp_common_t *swjdp, uint32_t address, uint32_t *value) +int mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value) { swjdp->trans_mode = TRANS_MODE_COMPOSITE; dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0); - dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value ); + dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value); return ERROR_OK; } -int mem_ap_read_atomic_u32(swjdp_common_t *swjdp, uint32_t address, uint32_t *value) +int mem_ap_read_atomic_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value) { mem_ap_read_u32(swjdp, address, value); @@ -418,22 +418,22 @@ int mem_ap_read_atomic_u32(swjdp_common_t *swjdp, uint32_t address, uint32_t *va /***************************************************************************** * * -* mem_ap_write_u32(swjdp_common_t *swjdp, uint32_t address, uint32_t value) * +* mem_ap_write_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value) * * * * Write a uint32_t value to memory or memory mapped register * * * *****************************************************************************/ -int mem_ap_write_u32(swjdp_common_t *swjdp, uint32_t address, uint32_t value) +int mem_ap_write_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value) { swjdp->trans_mode = TRANS_MODE_COMPOSITE; dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0); - dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value ); + dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value); return ERROR_OK; } -int mem_ap_write_atomic_u32(swjdp_common_t *swjdp, uint32_t address, uint32_t value) +int mem_ap_write_atomic_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value) { mem_ap_write_u32(swjdp, address, value); @@ -442,12 +442,12 @@ int mem_ap_write_atomic_u32(swjdp_common_t *swjdp, uint32_t address, uint32_t va /***************************************************************************** * * -* mem_ap_write_buf(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint32_t address) * +* mem_ap_write_buf(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) * * * * Write a buffer in target order (little endian) * * * *****************************************************************************/ -int mem_ap_write_buf_u32(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint32_t address) +int mem_ap_write_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) { int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK; uint32_t adr = address; @@ -467,7 +467,7 @@ int mem_ap_write_buf_u32(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint uint32_t outvalue; memcpy(&outvalue, pBuffer, sizeof(uint32_t)); - for (i = 0; i < 4; i++ ) + for (i = 0; i < 4; i++) { *((uint8_t*)pBuffer + (adr & 0x3)) = outvalue; outvalue >>= 8; @@ -492,7 +492,7 @@ int mem_ap_write_buf_u32(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint for (writecount = 0; writecount < blocksize; writecount++) { - dap_ap_write_reg(swjdp, AP_REG_DRW, buffer + 4 * writecount ); + dap_ap_write_reg(swjdp, AP_REG_DRW, buffer + 4 * writecount); } if (swjdp_transaction_endcheck(swjdp) == ERROR_OK) @@ -516,7 +516,7 @@ int mem_ap_write_buf_u32(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint return retval; } -int mem_ap_write_buf_packed_u16(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint32_t address) +int mem_ap_write_buf_packed_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) { int retval = ERROR_OK; int wcount, blocksize, writecount, i; @@ -546,7 +546,7 @@ int mem_ap_write_buf_packed_u16(swjdp_common_t *swjdp, uint8_t *buffer, int coun { nbytes = MIN((writecount << 1), 4); - if (nbytes < 4 ) + if (nbytes < 4) { if (mem_ap_write_buf_u16(swjdp, buffer, nbytes, address) != ERROR_OK) { @@ -561,7 +561,7 @@ int mem_ap_write_buf_packed_u16(swjdp_common_t *swjdp, uint8_t *buffer, int coun uint32_t outvalue; memcpy(&outvalue, buffer, sizeof(uint32_t)); - for (i = 0; i < nbytes; i++ ) + for (i = 0; i < nbytes; i++) { *((uint8_t*)buffer + (address & 0x3)) = outvalue; outvalue >>= 8; @@ -587,7 +587,7 @@ int mem_ap_write_buf_packed_u16(swjdp_common_t *swjdp, uint8_t *buffer, int coun return retval; } -int mem_ap_write_buf_u16(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint32_t address) +int mem_ap_write_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) { int retval = ERROR_OK; @@ -602,7 +602,7 @@ int mem_ap_write_buf_u16(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint uint16_t svalue; memcpy(&svalue, buffer, sizeof(uint16_t)); uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3); - dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue ); + dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue); retval = swjdp_transaction_endcheck(swjdp); count -= 2; address += 2; @@ -612,7 +612,7 @@ int mem_ap_write_buf_u16(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint return retval; } -int mem_ap_write_buf_packed_u8(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint32_t address) +int mem_ap_write_buf_packed_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) { int retval = ERROR_OK; int wcount, blocksize, writecount, i; @@ -638,7 +638,7 @@ int mem_ap_write_buf_packed_u8(swjdp_common_t *swjdp, uint8_t *buffer, int count { nbytes = MIN(writecount, 4); - if (nbytes < 4 ) + if (nbytes < 4) { if (mem_ap_write_buf_u8(swjdp, buffer, nbytes, address) != ERROR_OK) { @@ -653,7 +653,7 @@ int mem_ap_write_buf_packed_u8(swjdp_common_t *swjdp, uint8_t *buffer, int count uint32_t outvalue; memcpy(&outvalue, buffer, sizeof(uint32_t)); - for (i = 0; i < nbytes; i++ ) + for (i = 0; i < nbytes; i++) { *((uint8_t*)buffer + (address & 0x3)) = outvalue; outvalue >>= 8; @@ -679,7 +679,7 @@ int mem_ap_write_buf_packed_u8(swjdp_common_t *swjdp, uint8_t *buffer, int count return retval; } -int mem_ap_write_buf_u8(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint32_t address) +int mem_ap_write_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) { int retval = ERROR_OK; @@ -692,7 +692,7 @@ int mem_ap_write_buf_u8(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint3 { dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address); uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3); - dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue ); + dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue); retval = swjdp_transaction_endcheck(swjdp); count--; address++; @@ -704,12 +704,12 @@ int mem_ap_write_buf_u8(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint3 /********************************************************************************* * * -* mem_ap_read_buf_u32(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint32_t address) * +* mem_ap_read_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) * * * * Read block fast in target order (little endian) into a buffer * * * **********************************************************************************/ -int mem_ap_read_buf_u32(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint32_t address) +int mem_ap_read_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) { int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK; uint32_t adr = address; @@ -770,7 +770,7 @@ int mem_ap_read_buf_u32(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint3 uint32_t data; memcpy(&data, pBuffer, sizeof(uint32_t)); - for (i = 0; i < 4; i++ ) + for (i = 0; i < 4; i++) { *((uint8_t*)pBuffer) = (data >> 8 * (adr & 0x3)); pBuffer++; @@ -782,7 +782,7 @@ int mem_ap_read_buf_u32(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint3 return retval; } -int mem_ap_read_buf_packed_u16(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint32_t address) +int mem_ap_read_buf_packed_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) { uint32_t invalue; int retval = ERROR_OK; @@ -810,7 +810,7 @@ int mem_ap_read_buf_packed_u16(swjdp_common_t *swjdp, uint8_t *buffer, int count do { - dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue ); + dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue); if (swjdp_transaction_endcheck(swjdp) != ERROR_OK) { LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count); @@ -819,7 +819,7 @@ int mem_ap_read_buf_packed_u16(swjdp_common_t *swjdp, uint8_t *buffer, int count nbytes = MIN((readcount << 1), 4); - for (i = 0; i < nbytes; i++ ) + for (i = 0; i < nbytes; i++) { *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3)); buffer++; @@ -834,7 +834,7 @@ int mem_ap_read_buf_packed_u16(swjdp_common_t *swjdp, uint8_t *buffer, int count return retval; } -int mem_ap_read_buf_u16(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint32_t address) +int mem_ap_read_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) { uint32_t invalue, i; int retval = ERROR_OK; @@ -847,11 +847,11 @@ int mem_ap_read_buf_u16(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint3 while (count > 0) { dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address); - dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue ); + dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue); retval = swjdp_transaction_endcheck(swjdp); if (address & 0x1) { - for (i = 0; i < 2; i++ ) + for (i = 0; i < 2; i++) { *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3)); buffer++; @@ -877,7 +877,7 @@ int mem_ap_read_buf_u16(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint3 * The solution is to arrange for a large out/in scan in this loop and * and convert data afterwards. */ -int mem_ap_read_buf_packed_u8(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint32_t address) +int mem_ap_read_buf_packed_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) { uint32_t invalue; int retval = ERROR_OK; @@ -902,7 +902,7 @@ int mem_ap_read_buf_packed_u8(swjdp_common_t *swjdp, uint8_t *buffer, int count, do { - dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue ); + dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue); if (swjdp_transaction_endcheck(swjdp) != ERROR_OK) { LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count); @@ -911,7 +911,7 @@ int mem_ap_read_buf_packed_u8(swjdp_common_t *swjdp, uint8_t *buffer, int count, nbytes = MIN(readcount, 4); - for (i = 0; i < nbytes; i++ ) + for (i = 0; i < nbytes; i++) { *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3)); buffer++; @@ -926,7 +926,7 @@ int mem_ap_read_buf_packed_u8(swjdp_common_t *swjdp, uint8_t *buffer, int count, return retval; } -int mem_ap_read_buf_u8(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint32_t address) +int mem_ap_read_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) { uint32_t invalue; int retval = ERROR_OK; @@ -939,7 +939,7 @@ int mem_ap_read_buf_u8(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint32 while (count > 0) { dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address); - dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue ); + dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue); retval = swjdp_transaction_endcheck(swjdp); *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3)); count--; @@ -950,7 +950,7 @@ int mem_ap_read_buf_u8(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint32 return retval; } -int ahbap_debugport_init(swjdp_common_t *swjdp) +int ahbap_debugport_init(struct swjdp_common *swjdp) { uint32_t idreg, romaddr, dummy; uint32_t ctrlstat; @@ -971,7 +971,7 @@ int ahbap_debugport_init(swjdp_common_t *swjdp) dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT); dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT); - if ((retval=jtag_execute_queue()) != ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) return retval; /* Check that we have debug power domains activated */ @@ -979,7 +979,7 @@ int ahbap_debugport_init(swjdp_common_t *swjdp) { LOG_DEBUG("swjdp: wait CDBGPWRUPACK"); dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT); - if ((retval=jtag_execute_queue()) != ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) return retval; alive_sleep(10); } @@ -988,7 +988,7 @@ int ahbap_debugport_init(swjdp_common_t *swjdp) { LOG_DEBUG("swjdp: wait CSYSPWRUPACK"); dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT); - if ((retval=jtag_execute_queue()) != ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) return retval; alive_sleep(10); } @@ -1007,13 +1007,22 @@ int ahbap_debugport_init(swjdp_common_t *swjdp) return ERROR_OK; } +/* CID interpretation -- see ARM IHI 0029B section 3 */ +static const char *class_description[16] ={ + "Reserved", "ROM table", "Reserved", "Reserved", + "Reserved", "Reserved", "Reserved", "Reserved", + "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block", + "Reserved", "DESS", "Generic IP component", "PrimeCell or System component" +}; -char * class_description[16] ={ - "Reserved", - "ROM table","Reserved","Reserved","Reserved","Reserved","Reserved","Reserved","Reserved", - "CoreSight component","Reserved","Peripheral Test Block","Reserved","DESS","Generic IP component","Non standard layout"}; +static bool +is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0) +{ + return cid3 == 0xb1 && cid2 == 0x05 + && ((cid1 & 0x0f) == 0) && cid0 == 0x0d; +} -int dap_info_command(struct command_context_s *cmd_ctx, swjdp_common_t *swjdp, int apsel) +int dap_info_command(struct command_context *cmd_ctx, struct swjdp_common *swjdp, int apsel) { uint32_t dbgbase,apid; @@ -1058,57 +1067,283 @@ int dap_info_command(struct command_context_s *cmd_ctx, swjdp_common_t *swjdp, i { uint32_t cid0,cid1,cid2,cid3,memtype,romentry; uint16_t entry_offset; + /* bit 16 of apid indicates a memory access port */ - if (dbgbase&0x02) - { + if (dbgbase & 0x02) command_print(cmd_ctx, "\tValid ROM table present"); - } else - { - command_print(cmd_ctx, "\tROM table in legacy format" ); - } + command_print(cmd_ctx, "\tROM table in legacy format"); + /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */ - mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFF0, &cid0); - mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFF4, &cid1); - mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFF8, &cid2); - mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFFC, &cid3); - mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFCC, &memtype); + mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF0, &cid0); + mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF4, &cid1); + mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF8, &cid2); + mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFFC, &cid3); + mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFCC, &memtype); swjdp_transaction_endcheck(swjdp); - command_print(cmd_ctx, "\tCID3 0x%" PRIx32 ", CID2 0x%" PRIx32 ", CID1 0x%" PRIx32 " CID0, 0x%" PRIx32,cid3,cid2,cid1,cid0); - if (memtype&0x01) - { + if (!is_dap_cid_ok(cid3, cid2, cid1, cid0)) + command_print(cmd_ctx, "\tCID3 0x%2.2" PRIx32 + ", CID2 0x%2.2" PRIx32 + ", CID1 0x%2.2" PRIx32 + ", CID0 0x%2.2" PRIx32, + cid3, cid2, cid1, cid0); + if (memtype & 0x01) command_print(cmd_ctx, "\tMEMTYPE system memory present on bus"); - } else - { - command_print(cmd_ctx, "\tMEMTYPE system memory not present. Dedicated debug bus" ); - } + command_print(cmd_ctx, "\tMEMTYPE System memory not present. " + "Dedicated debug bus."); - /* Now we read ROM table entries from dbgbase&0xFFFFF000)|0x000 until we get 0x00000000 */ + /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */ entry_offset = 0; do { - mem_ap_read_atomic_u32(swjdp, (dbgbase&0xFFFFF000)|entry_offset, &romentry); + mem_ap_read_atomic_u32(swjdp, (dbgbase&0xFFFFF000) | entry_offset, &romentry); command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "",entry_offset,romentry); if (romentry&0x01) { - uint32_t c_cid0,c_cid1,c_cid2,c_cid3,c_pid0,c_pid1,c_pid2,c_pid3,c_pid4,component_start; - uint32_t component_base = (uint32_t)((dbgbase&0xFFFFF000)+(int)(romentry&0xFFFFF000)); - mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFE0, &c_pid0); - mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFE4, &c_pid1); - mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFE8, &c_pid2); - mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFEC, &c_pid3); - mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFD0, &c_pid4); - mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFF0, &c_cid0); - mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFF4, &c_cid1); - mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFF8, &c_cid2); - mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFFC, &c_cid3); + uint32_t c_cid0, c_cid1, c_cid2, c_cid3; + uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4; + uint32_t component_start, component_base; + unsigned part_num; + char *type, *full; + + component_base = (uint32_t)((dbgbase & 0xFFFFF000) + + (int)(romentry & 0xFFFFF000)); + mem_ap_read_atomic_u32(swjdp, + (component_base & 0xFFFFF000) | 0xFE0, &c_pid0); + mem_ap_read_atomic_u32(swjdp, + (component_base & 0xFFFFF000) | 0xFE4, &c_pid1); + mem_ap_read_atomic_u32(swjdp, + (component_base & 0xFFFFF000) | 0xFE8, &c_pid2); + mem_ap_read_atomic_u32(swjdp, + (component_base & 0xFFFFF000) | 0xFEC, &c_pid3); + mem_ap_read_atomic_u32(swjdp, + (component_base & 0xFFFFF000) | 0xFD0, &c_pid4); + mem_ap_read_atomic_u32(swjdp, + (component_base & 0xFFFFF000) | 0xFF0, &c_cid0); + mem_ap_read_atomic_u32(swjdp, + (component_base & 0xFFFFF000) | 0xFF4, &c_cid1); + mem_ap_read_atomic_u32(swjdp, + (component_base & 0xFFFFF000) | 0xFF8, &c_cid2); + mem_ap_read_atomic_u32(swjdp, + (component_base & 0xFFFFF000) | 0xFFC, &c_cid3); component_start = component_base - 0x1000*(c_pid4 >> 4); - command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32 ", pid4 0x%" PRIx32 ", start address 0x%" PRIx32 "",component_base,c_pid4,component_start); - command_print(cmd_ctx, "\t\tComponent cid1 0x%" PRIx32 ", class is %s",c_cid1,class_description[(c_cid1 >> 4)&0xF]); /* Se ARM DDI 0314 C Table 2.2 */ - command_print(cmd_ctx, "\t\tCID3 0x%" PRIx32 ", CID2 0x%" PRIx32 ", CID1 0x%" PRIx32 ", CID0, 0x%" PRIx32 "",c_cid3,c_cid2,c_cid1,c_cid0); - command_print(cmd_ctx, "\t\tPID3 0x%" PRIx32 ", PID2 0x%" PRIx32 ", PID1 0x%" PRIx32 ", PID0, 0x%" PRIx32 "",c_pid3,c_pid2,c_pid1,c_pid0); - /* For CoreSight components, (c_cid1 >> 4)&0xF==9 , we also read 0xFC8 DevId and 0xFCC DevType */ + + command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32 + ", start address 0x%" PRIx32, + component_base, component_start); + command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s", + (int) (c_cid1 >> 4) & 0xf, + /* See ARM IHI 0029B Table 3-3 */ + class_description[(c_cid1 >> 4) & 0xf]); + + /* CoreSight component? */ + if (((c_cid1 >> 4) & 0x0f) == 9) { + uint32_t devtype; + unsigned minor; + char *major = "Reserved", *subtype = "Reserved"; + + mem_ap_read_atomic_u32(swjdp, + (component_base & 0xfffff000) | 0xfcc, + &devtype); + minor = (devtype >> 4) & 0x0f; + switch (devtype & 0x0f) { + case 0: + major = "Miscellaneous"; + switch (minor) { + case 0: + subtype = "other"; + break; + case 4: + subtype = "Validation component"; + break; + } + break; + case 1: + major = "Trace Sink"; + switch (minor) { + case 0: + subtype = "other"; + break; + case 1: + subtype = "Port"; + break; + case 2: + subtype = "Buffer"; + break; + } + break; + case 2: + major = "Trace Link"; + switch (minor) { + case 0: + subtype = "other"; + break; + case 1: + subtype = "Funnel, router"; + break; + case 2: + subtype = "Filter"; + break; + case 3: + subtype = "FIFO, buffer"; + break; + } + break; + case 3: + major = "Trace Source"; + switch (minor) { + case 0: + subtype = "other"; + break; + case 1: + subtype = "Processor"; + break; + case 2: + subtype = "DSP"; + break; + case 3: + subtype = "Engine/Coprocessor"; + break; + case 4: + subtype = "Bus"; + break; + } + break; + case 4: + major = "Debug Control"; + switch (minor) { + case 0: + subtype = "other"; + break; + case 1: + subtype = "Trigger Matrix"; + break; + case 2: + subtype = "Debug Auth"; + break; + } + break; + case 5: + major = "Debug Logic"; + switch (minor) { + case 0: + subtype = "other"; + break; + case 1: + subtype = "Processor"; + break; + case 2: + subtype = "DSP"; + break; + case 3: + subtype = "Engine/Coprocessor"; + break; + } + break; + } + command_print(cmd_ctx, "\t\tType is 0x%2.2x, %s, %s", + (unsigned) (devtype & 0xff), + major, subtype); + /* REVISIT also show 0xfc8 DevId */ + } + + if (!is_dap_cid_ok(cid3, cid2, cid1, cid0)) + command_print(cmd_ctx, "\t\tCID3 0x%2.2" PRIx32 + ", CID2 0x%2.2" PRIx32 + ", CID1 0x%2.2" PRIx32 + ", CID0 0x%2.2" PRIx32, + c_cid3, c_cid2, c_cid1, c_cid0); + command_print(cmd_ctx, "\t\tPeripheral ID[4..0] = hex " + "%2.2x %2.2x %2.2x %2.2x %2.2x", + (int) c_pid4, + (int) c_pid3, (int) c_pid2, + (int) c_pid1, (int) c_pid0); + + /* Part number interpretations are from Cortex + * core specs, the CoreSight components TRM + * (ARM DDI 0314H), and ETM specs; also from + * chip observation (e.g. TI SDTI). + */ + part_num = c_pid0 & 0xff; + part_num |= (c_pid1 & 0x0f) << 8; + switch (part_num) { + case 0x000: + type = "Cortex-M3 NVIC"; + full = "(Interrupt Controller)"; + break; + case 0x001: + type = "Cortex-M3 ITM"; + full = "(Instrumentation Trace Module)"; + break; + case 0x002: + type = "Cortex-M3 DWT"; + full = "(Data Watchpoint and Trace)"; + break; + case 0x003: + type = "Cortex-M3 FBP"; + full = "(Flash Patch and Breakpoint)"; + break; + case 0x00d: + type = "CoreSight ETM11"; + full = "(Embedded Trace)"; + break; + // case 0x113: what? + case 0x120: /* from OMAP3 memmap */ + type = "TI SDTI"; + full = "(System Debug Trace Interface)"; + break; + case 0x343: /* from OMAP3 memmap */ + type = "TI DAPCTL"; + full = ""; + break; + case 0x4e0: + type = "Cortex-M3 ETM"; + full = "(Embedded Trace)"; + break; + case 0x906: + type = "Coresight CTI"; + full = "(Cross Trigger)"; + break; + case 0x907: + type = "Coresight ETB"; + full = "(Trace Buffer)"; + break; + case 0x908: + type = "Coresight CSTF"; + full = "(Trace Funnel)"; + break; + case 0x910: + type = "CoreSight ETM9"; + full = "(Embedded Trace)"; + break; + case 0x912: + type = "Coresight TPIU"; + full = "(Trace Port Interface Unit)"; + break; + case 0x921: + type = "Cortex-A8 ETM"; + full = "(Embedded Trace)"; + break; + case 0x922: + type = "Cortex-A8 CTI"; + full = "(Cross Trigger)"; + break; + case 0x923: + type = "Cortex-M3 TPIU"; + full = "(Trace Port Interface Unit)"; + break; + case 0xc08: + type = "Cortex-A8 Debug"; + full = "(Debug Unit)"; + break; + default: + type = "-*- unrecognized -*-"; + full = ""; + break; + } + command_print(cmd_ctx, "\t\tPart is %s %s", + type, full); } else { @@ -1118,7 +1353,7 @@ int dap_info_command(struct command_context_s *cmd_ctx, swjdp_common_t *swjdp, i command_print(cmd_ctx, "\t\tEnd of ROM table"); } entry_offset += 4; - } while (romentry>0); + } while (romentry > 0); } else { @@ -1129,3 +1364,108 @@ int dap_info_command(struct command_context_s *cmd_ctx, swjdp_common_t *swjdp, i return ERROR_OK; } +DAP_COMMAND_HANDLER(dap_baseaddr_command) +{ + uint32_t apsel, apselsave, baseaddr; + int retval; + + apselsave = swjdp->apsel; + switch (CMD_ARGC) { + case 0: + apsel = swjdp->apsel; + break; + case 1: + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel); + break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; + } + + if (apselsave != apsel) + dap_ap_select(swjdp, apsel); + + dap_ap_read_reg_u32(swjdp, 0xF8, &baseaddr); + retval = swjdp_transaction_endcheck(swjdp); + command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr); + + if (apselsave != apsel) + dap_ap_select(swjdp, apselsave); + + return retval; +} + +DAP_COMMAND_HANDLER(dap_memaccess_command) +{ + uint32_t memaccess_tck; + + switch (CMD_ARGC) { + case 0: + memaccess_tck = swjdp->memaccess_tck; + break; + case 1: + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck); + break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; + } + swjdp->memaccess_tck = memaccess_tck; + + command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck", + swjdp->memaccess_tck); + + return ERROR_OK; +} + +DAP_COMMAND_HANDLER(dap_apsel_command) +{ + uint32_t apsel, apid; + int retval; + + switch (CMD_ARGC) { + case 0: + apsel = 0; + break; + case 1: + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel); + break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; + } + + dap_ap_select(swjdp, apsel); + dap_ap_read_reg_u32(swjdp, 0xFC, &apid); + retval = swjdp_transaction_endcheck(swjdp); + command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32, + apsel, apid); + + return retval; +} + +DAP_COMMAND_HANDLER(dap_apid_command) +{ + uint32_t apsel, apselsave, apid; + int retval; + + apselsave = swjdp->apsel; + switch (CMD_ARGC) { + case 0: + apsel = swjdp->apsel; + break; + case 1: + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel); + break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; + } + + if (apselsave != apsel) + dap_ap_select(swjdp, apsel); + + dap_ap_read_reg_u32(swjdp, 0xFC, &apid); + retval = swjdp_transaction_endcheck(swjdp); + command_print(CMD_CTX, "0x%8.8" PRIx32, apid); + if (apselsave != apsel) + dap_ap_select(swjdp, apselsave); + + return retval; +}