X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm_adi_v5.c;h=34147967a7feda7fa526e670ba7b5c05a59f395e;hp=ba5db3b13c23bd1faca14cfd2c350524c51a6737;hb=559d08c19ed838f7bb2a77ce56a5a274641111f8;hpb=183765707fb4d819b790b9431b83a9bf637fadc5 diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c index ba5db3b13c..34147967a7 100644 --- a/src/target/arm_adi_v5.c +++ b/src/target/arm_adi_v5.c @@ -5,9 +5,11 @@ * Copyright (C) 2008 by Spencer Oliver * * spen@spen-soft.co.uk * * * - * Copyright (C) 2009 by Oyvind Harboe * + * Copyright (C) 2009-2010 by Oyvind Harboe * * oyvind.harboe@zylin.com * * * + * Copyright (C) 2009-2010 by David Brownell * + * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * * the Free Software Foundation; either version 2 of the License, or * @@ -40,6 +42,17 @@ * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP * is used to access memory mapped resources and is called a MEM-AP. Also a * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon. + * + * This programming interface allows DAP pipelined operations through a + * transaction queue. This primarily affects AP operations (such as using + * a MEM-AP to access memory or registers). If the current transaction has + * not finished by the time the next one must begin, and the ORUNDETECT bit + * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and + * further AP operations will fail. There are two basic methods to avoid + * such overrun errors. One involves polling for status instead of using + * transaction piplining. The other involves adding delays to ensure the + * AP has enough time to complete one operation before starting the next + * one. (For JTAG these delays are controlled by memaccess_tck.) */ /* @@ -56,20 +69,10 @@ #include "config.h" #endif +#include "arm.h" #include "arm_adi_v5.h" #include -/* - * Transaction Mode: - * swjdp->trans_mode = TRANS_MODE_COMPOSITE; - * Uses Overrun checking mode and does not do actual JTAG send/receive or transaction - * result checking until swjdp_end_transaction() - * This must be done before using or deallocating any return variables. - * swjdp->trans_mode == TRANS_MODE_ATOMIC - * All reads and writes to the AHB bus are checked for valid completion, and return values - * are immediatley available. -*/ - /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */ @@ -84,465 +87,195 @@ static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address /*************************************************************************** * * - * DPACC and APACC scanchain access through JTAG-DP * + * DP and MEM-AP register access through APACC and DPACC * * * ***************************************************************************/ /** - * Scan DPACC or APACC using target ordered uint8_t buffers. No endianness - * conversions are performed. See section 4.4.3 of the ADIv5 spec, which - * discusses operations which access these registers. + * Select one of the APs connected to the specified DAP. The + * selection is implicitly used with future AP transactions. + * This is a NOP if the specified AP is already selected. * - * Note that only one scan is performed. If RnW is set, a separate scan - * will be needed to collect the data which was read; the "invalue" collects - * the posted result of a preceding operation, not the current one. - * - * @param swjdp the DAP - * @param instr JTAG_DP_APACC (AP access) or JTAG_DP_DPACC (DP access) - * @param reg_addr two significant bits; A[3:2]; for APACC access, the - * SELECT register has more addressing bits. - * @param RnW false iff outvalue will be written to the DP or AP - * @param outvalue points to a 32-bit (little-endian) integer - * @param invalue NULL, or points to a 32-bit (little-endian) integer - * @param ack points to where the three bit JTAG_ACK_* code will be stored + * @param dap The DAP + * @param apsel Number of the AP to (implicitly) use with further + * transactions. This normally identifies a MEM-AP. */ -static int adi_jtag_dp_scan(struct swjdp_common *swjdp, - uint8_t instr, uint8_t reg_addr, uint8_t RnW, - uint8_t *outvalue, uint8_t *invalue, uint8_t *ack) -{ - struct arm_jtag *jtag_info = swjdp->jtag_info; - struct scan_field fields[2]; - uint8_t out_addr_buf; - - jtag_set_end_state(TAP_IDLE); - arm_jtag_set_instr(jtag_info, instr, NULL); - - /* Add specified number of tck clocks before accessing memory bus */ - - /* REVISIT these TCK cycles should be *AFTER* updating APACC, since - * they provide more time for the (MEM) AP to complete the read ... - * See "Minimum Response Time" for JTAG-DP, in the ADIv5 spec. - */ - if ((instr == JTAG_DP_APACC) - && ((reg_addr == AP_REG_DRW) - || ((reg_addr & 0xF0) == AP_REG_BD0)) - && (swjdp->memaccess_tck != 0)) - jtag_add_runtest(swjdp->memaccess_tck, jtag_set_end_state(TAP_IDLE)); - - /* Scan out a read or write operation using some DP or AP register. - * For APACC access with any sticky error flag set, this is discarded. - */ - fields[0].tap = jtag_info->tap; - fields[0].num_bits = 3; - buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1)); - fields[0].out_value = &out_addr_buf; - fields[0].in_value = ack; - - /* NOTE: if we receive JTAG_ACK_WAIT, the previous operation did not - * complete; data we write is discarded, data we read is unpredictable. - * When overrun detect is active, STICKYORUN is set. - */ - - fields[1].tap = jtag_info->tap; - fields[1].num_bits = 32; - fields[1].out_value = outvalue; - fields[1].in_value = invalue; - - jtag_add_dr_scan(2, fields, jtag_get_end_state()); - - return ERROR_OK; -} - -/* Scan out and in from host ordered uint32_t variables */ -static int adi_jtag_dp_scan_u32(struct swjdp_common *swjdp, - uint8_t instr, uint8_t reg_addr, uint8_t RnW, - uint32_t outvalue, uint32_t *invalue, uint8_t *ack) +void dap_ap_select(struct adiv5_dap *dap,uint8_t apsel) { - struct arm_jtag *jtag_info = swjdp->jtag_info; - struct scan_field fields[2]; - uint8_t out_value_buf[4]; - uint8_t out_addr_buf; + uint32_t select_apsel = (apsel << 24) & 0xFF000000; - jtag_set_end_state(TAP_IDLE); - arm_jtag_set_instr(jtag_info, instr, NULL); - - /* Add specified number of tck clocks before accessing memory bus */ - - /* REVISIT these TCK cycles should be *AFTER* updating APACC, since - * they provide more time for the (MEM) AP to complete the read ... - */ - if ((instr == JTAG_DP_APACC) - && ((reg_addr == AP_REG_DRW) - || ((reg_addr & 0xF0) == AP_REG_BD0)) - && (swjdp->memaccess_tck != 0)) - jtag_add_runtest(swjdp->memaccess_tck, jtag_set_end_state(TAP_IDLE)); - - fields[0].tap = jtag_info->tap; - fields[0].num_bits = 3; - buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1)); - fields[0].out_value = &out_addr_buf; - fields[0].in_value = ack; - - fields[1].tap = jtag_info->tap; - fields[1].num_bits = 32; - buf_set_u32(out_value_buf, 0, 32, outvalue); - fields[1].out_value = out_value_buf; - fields[1].in_value = NULL; - - if (invalue) + if (select_apsel != dap->apsel) { - fields[1].in_value = (uint8_t *)invalue; - jtag_add_dr_scan(2, fields, jtag_get_end_state()); - - jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t) invalue); - } else - { - - jtag_add_dr_scan(2, fields, jtag_get_end_state()); + dap->apsel = select_apsel; + /* Switching AP invalidates cached values. + * Values MUST BE UPDATED BEFORE AP ACCESS. + */ + dap->ap_bank_value = -1; + dap->ap_csw_value = -1; + dap->ap_tar_value = -1; } - - return ERROR_OK; } -/* scan_inout_check adds one extra inscan for DPAP_READ commands to read variables */ -static int scan_inout_check(struct swjdp_common *swjdp, - uint8_t instr, uint8_t reg_addr, uint8_t RnW, - uint8_t *outvalue, uint8_t *invalue) -{ - adi_jtag_dp_scan(swjdp, instr, reg_addr, RnW, outvalue, NULL, NULL); - - if ((RnW == DPAP_READ) && (invalue != NULL)) - adi_jtag_dp_scan(swjdp, JTAG_DP_DPACC, - DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack); - - /* In TRANS_MODE_ATOMIC all JTAG_DP_APACC transactions wait for - * ack = OK/FAULT and the check CTRL_STAT - */ - if ((instr == JTAG_DP_APACC) - && (swjdp->trans_mode == TRANS_MODE_ATOMIC)) - return swjdp_transaction_endcheck(swjdp); - - return ERROR_OK; -} - -static int scan_inout_check_u32(struct swjdp_common *swjdp, - uint8_t instr, uint8_t reg_addr, uint8_t RnW, - uint32_t outvalue, uint32_t *invalue) -{ - /* Issue the read or write */ - adi_jtag_dp_scan_u32(swjdp, instr, reg_addr, RnW, outvalue, NULL, NULL); - - /* For reads, collect posted value; RDBUFF has no other effect. - * Assumes read gets acked with OK/FAULT, and CTRL_STAT says "OK". - */ - if ((RnW == DPAP_READ) && (invalue != NULL)) - adi_jtag_dp_scan_u32(swjdp, JTAG_DP_DPACC, - DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack); - - /* In TRANS_MODE_ATOMIC all JTAG_DP_APACC transactions wait for - * ack = OK/FAULT and then check CTRL_STAT - */ - if ((instr == JTAG_DP_APACC) - && (swjdp->trans_mode == TRANS_MODE_ATOMIC)) - return swjdp_transaction_endcheck(swjdp); - - return ERROR_OK; -} - -int swjdp_transaction_endcheck(struct swjdp_common *swjdp) +/** + * Queue transactions setting up transfer parameters for the + * currently selected MEM-AP. + * + * Subsequent transfers using registers like AP_REG_DRW or AP_REG_BD2 + * initiate data reads or writes using memory or peripheral addresses. + * If the CSW is configured for it, the TAR may be automatically + * incremented after each transfer. + * + * @todo Rename to reflect it being specifically a MEM-AP function. + * + * @param dap The DAP connected to the MEM-AP. + * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this + * matches the cached value, the register is not changed. + * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this + * matches the cached address, the register is not changed. + * + * @return ERROR_OK if the transaction was properly queued, else a fault code. + */ +int dap_setup_accessport(struct adiv5_dap *dap, uint32_t csw, uint32_t tar) { int retval; - uint32_t ctrlstat; - - /* too expensive to call keep_alive() here */ - -#if 0 - /* Danger!!!! BROKEN!!!! */ - scan_inout_check_u32(swjdp, JTAG_DP_DPACC, - DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat); - /* Danger!!!! BROKEN!!!! Why will jtag_execute_queue() fail here???? - R956 introduced the check on return value here and now Michael Schwingen reports - that this code no longer works.... - - https://lists.berlios.de/pipermail/openocd-development/2008-September/003107.html - */ - if ((retval = jtag_execute_queue()) != ERROR_OK) - { - LOG_ERROR("BUG: Why does this fail the first time????"); - } - /* Why??? second time it works??? */ -#endif - - /* Post CTRL/STAT read; discard any previous posted read value - * but collect its ACK status. - */ - scan_inout_check_u32(swjdp, JTAG_DP_DPACC, - DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat); - if ((retval = jtag_execute_queue()) != ERROR_OK) - return retval; - - swjdp->ack = swjdp->ack & 0x7; - /* common code path avoids calling timeval_ms() */ - if (swjdp->ack != JTAG_ACK_OK_FAULT) - { - long long then = timeval_ms(); - - while (swjdp->ack != JTAG_ACK_OK_FAULT) - { - if (swjdp->ack == JTAG_ACK_WAIT) - { - if ((timeval_ms()-then) > 1000) - { - /* NOTE: this would be a good spot - * to use JTAG_DP_ABORT. - */ - LOG_WARNING("Timeout (1000ms) waiting " - "for ACK=OK/FAULT " - "in JTAG-DP transaction"); - return ERROR_JTAG_DEVICE_ERROR; - } - } - else - { - LOG_WARNING("Invalid ACK %#x" - "in JTAG-DP transaction", - swjdp->ack); - return ERROR_JTAG_DEVICE_ERROR; - } - - scan_inout_check_u32(swjdp, JTAG_DP_DPACC, - DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat); - if ((retval = jtag_execute_queue()) != ERROR_OK) - return retval; - swjdp->ack = swjdp->ack & 0x7; - } - } - - /* Check for STICKYERR and STICKYORUN */ - if (ctrlstat & (SSTICKYORUN | SSTICKYERR)) + csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT; + if (csw != dap->ap_csw_value) { - LOG_DEBUG("swjdp: CTRL/STAT error 0x%" PRIx32 "", ctrlstat); - /* Check power to debug regions */ - if ((ctrlstat & 0xf0000000) != 0xf0000000) - { - ahbap_debugport_init(swjdp); - } - else - { - uint32_t mem_ap_csw, mem_ap_tar; - - /* Print information about last AHBAP access */ - LOG_ERROR("AHBAP Cached values: dp_select 0x%" PRIx32 ", ap_csw 0x%" PRIx32 ", ap_tar 0x%" PRIx32 "", swjdp->dp_select_value, swjdp->ap_csw_value, swjdp->ap_tar_value); - if (ctrlstat & SSTICKYORUN) - LOG_ERROR("JTAG-DP OVERRUN - " - "check clock or reduce jtag speed"); - - if (ctrlstat & SSTICKYERR) - LOG_ERROR("JTAG-DP STICKY ERROR"); - - /* Clear Sticky Error Bits */ - scan_inout_check_u32(swjdp, JTAG_DP_DPACC, - DP_CTRL_STAT, DPAP_WRITE, - swjdp->dp_ctrl_stat | SSTICKYORUN - | SSTICKYERR, NULL); - scan_inout_check_u32(swjdp, JTAG_DP_DPACC, - DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat); - if ((retval = jtag_execute_queue()) != ERROR_OK) - return retval; - - LOG_DEBUG("swjdp: status 0x%" PRIx32 "", ctrlstat); - - dap_ap_read_reg_u32(swjdp, AP_REG_CSW, &mem_ap_csw); - dap_ap_read_reg_u32(swjdp, AP_REG_TAR, &mem_ap_tar); - if ((retval = jtag_execute_queue()) != ERROR_OK) - return retval; - LOG_ERROR("Read MEM_AP_CSW 0x%" PRIx32 ", MEM_AP_TAR 0x%" PRIx32 "", mem_ap_csw, mem_ap_tar); - - } - if ((retval = jtag_execute_queue()) != ERROR_OK) + /* LOG_DEBUG("DAP: Set CSW %x",csw); */ + retval = dap_queue_ap_write(dap, AP_REG_CSW, csw); + if (retval != ERROR_OK) return retval; - return ERROR_JTAG_DEVICE_ERROR; + dap->ap_csw_value = csw; } - - return ERROR_OK; -} - -/*************************************************************************** - * * - * DP and MEM-AP register access through APACC and DPACC * - * * -***************************************************************************/ - -static int dap_dp_write_reg(struct swjdp_common *swjdp, - uint32_t value, uint8_t reg_addr) -{ - return scan_inout_check_u32(swjdp, JTAG_DP_DPACC, - reg_addr, DPAP_WRITE, value, NULL); -} - -static int dap_dp_read_reg(struct swjdp_common *swjdp, - uint32_t *value, uint8_t reg_addr) -{ - return scan_inout_check_u32(swjdp, JTAG_DP_DPACC, - reg_addr, DPAP_READ, 0, value); -} - -int dap_ap_select(struct swjdp_common *swjdp,uint8_t apsel) -{ - uint32_t select; - select = (apsel << 24) & 0xFF000000; - - if (select != swjdp->apsel) + if (tar != dap->ap_tar_value) { - swjdp->apsel = select; - /* Switching AP invalidates cached values */ - swjdp->dp_select_value = -1; - swjdp->ap_csw_value = -1; - swjdp->ap_tar_value = -1; - } - - return ERROR_OK; -} - -static int dap_dp_bankselect(struct swjdp_common *swjdp, uint32_t ap_reg) -{ - uint32_t select; - select = (ap_reg & 0x000000F0); - - if (select != swjdp->dp_select_value) - { - dap_dp_write_reg(swjdp, select | swjdp->apsel, DP_SELECT); - swjdp->dp_select_value = select; + /* LOG_DEBUG("DAP: Set TAR %x",tar); */ + retval = dap_queue_ap_write(dap, AP_REG_TAR, tar); + if (retval != ERROR_OK) + return retval; + dap->ap_tar_value = tar; } - - return ERROR_OK; -} - -static int dap_ap_write_reg(struct swjdp_common *swjdp, - uint32_t reg_addr, uint8_t *out_value_buf) -{ - dap_dp_bankselect(swjdp, reg_addr); - scan_inout_check(swjdp, JTAG_DP_APACC, reg_addr, - DPAP_WRITE, out_value_buf, NULL); - + /* Disable TAR cache when autoincrementing */ + if (csw & CSW_ADDRINC_MASK) + dap->ap_tar_value = -1; return ERROR_OK; } -int dap_ap_write_reg_u32(struct swjdp_common *swjdp, uint32_t reg_addr, uint32_t value) +/** + * Asynchronous (queued) read of a word from memory or a system register. + * + * @param dap The DAP connected to the MEM-AP performing the read. + * @param address Address of the 32-bit word to read; it must be + * readable by the currently selected MEM-AP. + * @param value points to where the word will be stored when the + * transaction queue is flushed (assuming no errors). + * + * @return ERROR_OK for success. Otherwise a fault code. + */ +int mem_ap_read_u32(struct adiv5_dap *dap, uint32_t address, + uint32_t *value) { - uint8_t out_value_buf[4]; + int retval; - buf_set_u32(out_value_buf, 0, 32, value); - dap_dp_bankselect(swjdp, reg_addr); - scan_inout_check(swjdp, JTAG_DP_APACC, reg_addr, - DPAP_WRITE, out_value_buf, NULL); + /* Use banked addressing (REG_BDx) to avoid some link traffic + * (updating TAR) when reading several consecutive addresses. + */ + retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF, + address & 0xFFFFFFF0); + if (retval != ERROR_OK) + return retval; - return ERROR_OK; + return dap_queue_ap_read(dap, AP_REG_BD0 | (address & 0xC), value); } -int dap_ap_read_reg_u32(struct swjdp_common *swjdp, uint32_t reg_addr, uint32_t *value) +/** + * Synchronous read of a word from memory or a system register. + * As a side effect, this flushes any queued transactions. + * + * @param dap The DAP connected to the MEM-AP performing the read. + * @param address Address of the 32-bit word to read; it must be + * readable by the currently selected MEM-AP. + * @param value points to where the result will be stored. + * + * @return ERROR_OK for success; *value holds the result. + * Otherwise a fault code. + */ +int mem_ap_read_atomic_u32(struct adiv5_dap *dap, uint32_t address, + uint32_t *value) { - dap_dp_bankselect(swjdp, reg_addr); - scan_inout_check_u32(swjdp, JTAG_DP_APACC, reg_addr, - DPAP_READ, 0, value); - - return ERROR_OK; -} + int retval; -/*************************************************************************** - * * - * AHB-AP access to memory and system registers on AHB bus * - * * -***************************************************************************/ + retval = mem_ap_read_u32(dap, address, value); + if (retval != ERROR_OK) + return retval; -int dap_setup_accessport(struct swjdp_common *swjdp, uint32_t csw, uint32_t tar) -{ - csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT; - if (csw != swjdp->ap_csw_value) - { - /* LOG_DEBUG("swjdp : Set CSW %x",csw); */ - dap_ap_write_reg_u32(swjdp, AP_REG_CSW, csw); - swjdp->ap_csw_value = csw; - } - if (tar != swjdp->ap_tar_value) - { - /* LOG_DEBUG("swjdp : Set TAR %x",tar); */ - dap_ap_write_reg_u32(swjdp, AP_REG_TAR, tar); - swjdp->ap_tar_value = tar; - } - if (csw & CSW_ADDRINC_MASK) - { - /* Do not cache TAR value when autoincrementing */ - swjdp->ap_tar_value = -1; - } - return ERROR_OK; + return dap_run(dap); } -/***************************************************************************** -* * -* mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value) * -* * -* Read a uint32_t value from memory or system register * -* Functionally equivalent to target_read_u32(target, address, uint32_t *value), * -* but with less overhead * -*****************************************************************************/ -int mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value) +/** + * Asynchronous (queued) write of a word to memory or a system register. + * + * @param dap The DAP connected to the MEM-AP. + * @param address Address to be written; it must be writable by + * the currently selected MEM-AP. + * @param value Word that will be written to the address when transaction + * queue is flushed (assuming no errors). + * + * @return ERROR_OK for success. Otherwise a fault code. + */ +int mem_ap_write_u32(struct adiv5_dap *dap, uint32_t address, + uint32_t value) { - swjdp->trans_mode = TRANS_MODE_COMPOSITE; - - dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0); - dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value); - - return ERROR_OK; -} + int retval; -int mem_ap_read_atomic_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value) -{ - mem_ap_read_u32(swjdp, address, value); + /* Use banked addressing (REG_BDx) to avoid some link traffic + * (updating TAR) when writing several consecutive addresses. + */ + retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF, + address & 0xFFFFFFF0); + if (retval != ERROR_OK) + return retval; - return swjdp_transaction_endcheck(swjdp); + return dap_queue_ap_write(dap, AP_REG_BD0 | (address & 0xC), + value); } -/***************************************************************************** -* * -* mem_ap_write_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value) * -* * -* Write a uint32_t value to memory or memory mapped register * -* * -*****************************************************************************/ -int mem_ap_write_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value) +/** + * Synchronous write of a word to memory or a system register. + * As a side effect, this flushes any queued transactions. + * + * @param dap The DAP connected to the MEM-AP. + * @param address Address to be written; it must be writable by + * the currently selected MEM-AP. + * @param value Word that will be written. + * + * @return ERROR_OK for success; the data was written. Otherwise a fault code. + */ +int mem_ap_write_atomic_u32(struct adiv5_dap *dap, uint32_t address, + uint32_t value) { - swjdp->trans_mode = TRANS_MODE_COMPOSITE; - - dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0); - dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value); - - return ERROR_OK; -} + int retval = mem_ap_write_u32(dap, address, value); -int mem_ap_write_atomic_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value) -{ - mem_ap_write_u32(swjdp, address, value); + if (retval != ERROR_OK) + return retval; - return swjdp_transaction_endcheck(swjdp); + return dap_run(dap); } /***************************************************************************** * * -* mem_ap_write_buf(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) * +* mem_ap_write_buf(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address) * * * * Write a buffer in target order (little endian) * * * *****************************************************************************/ -int mem_ap_write_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) +int mem_ap_write_buf_u32(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address) { int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK; uint32_t adr = address; uint8_t* pBuffer = buffer; - swjdp->trans_mode = TRANS_MODE_COMPOSITE; - count >>= 2; wcount = count; @@ -568,7 +301,7 @@ int mem_ap_write_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, while (wcount > 0) { /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/ - blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address); + blocksize = max_tar_block_size(dap->tar_autoincr_block, address); if (wcount < blocksize) blocksize = wcount; @@ -576,14 +309,19 @@ int mem_ap_write_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, if (blocksize == 0) blocksize = 1; - dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address); + retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_SINGLE, address); + if (retval != ERROR_OK) + return retval; for (writecount = 0; writecount < blocksize; writecount++) { - dap_ap_write_reg(swjdp, AP_REG_DRW, buffer + 4 * writecount); + retval = dap_queue_ap_write(dap, AP_REG_DRW, + *(uint32_t *) ((void *) (buffer + 4 * writecount))); + if (retval != ERROR_OK) + break; } - if (swjdp_transaction_endcheck(swjdp) == ERROR_OK) + if ((retval = dap_run(dap)) == ERROR_OK) { wcount = wcount - blocksize; address = address + 4 * blocksize; @@ -597,21 +335,19 @@ int mem_ap_write_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, if (errorcount > 1) { LOG_WARNING("Block write error address 0x%" PRIx32 ", wcount 0x%x", address, wcount); - return ERROR_JTAG_DEVICE_ERROR; + return retval; } } return retval; } -static int mem_ap_write_buf_packed_u16(struct swjdp_common *swjdp, +static int mem_ap_write_buf_packed_u16(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address) { int retval = ERROR_OK; int wcount, blocksize, writecount, i; - swjdp->trans_mode = TRANS_MODE_COMPOSITE; - wcount = count >> 1; while (wcount > 0) @@ -619,7 +355,7 @@ static int mem_ap_write_buf_packed_u16(struct swjdp_common *swjdp, int nbytes; /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/ - blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address); + blocksize = max_tar_block_size(dap->tar_autoincr_block, address); if (wcount < blocksize) blocksize = wcount; @@ -628,7 +364,9 @@ static int mem_ap_write_buf_packed_u16(struct swjdp_common *swjdp, if (blocksize == 0) blocksize = 1; - dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address); + retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_PACKED, address); + if (retval != ERROR_OK) + return retval; writecount = blocksize; do @@ -637,10 +375,14 @@ static int mem_ap_write_buf_packed_u16(struct swjdp_common *swjdp, if (nbytes < 4) { - if (mem_ap_write_buf_u16(swjdp, buffer, nbytes, address) != ERROR_OK) + retval = mem_ap_write_buf_u16(dap, buffer, + nbytes, address); + if (retval != ERROR_OK) { - LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count); - return ERROR_JTAG_DEVICE_ERROR; + LOG_WARNING("Block write error address " + "0x%" PRIx32 ", count 0x%x", + address, count); + return retval; } address += nbytes >> 1; @@ -658,11 +400,17 @@ static int mem_ap_write_buf_packed_u16(struct swjdp_common *swjdp, } memcpy(&outvalue, buffer, sizeof(uint32_t)); - dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue); - if (swjdp_transaction_endcheck(swjdp) != ERROR_OK) + retval = dap_queue_ap_write(dap, + AP_REG_DRW, outvalue); + if (retval != ERROR_OK) + break; + + if ((retval = dap_run(dap)) != ERROR_OK) { - LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count); - return ERROR_JTAG_DEVICE_ERROR; + LOG_WARNING("Block write error address " + "0x%" PRIx32 ", count 0x%x", + address, count); + return retval; } } @@ -676,23 +424,29 @@ static int mem_ap_write_buf_packed_u16(struct swjdp_common *swjdp, return retval; } -int mem_ap_write_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) +int mem_ap_write_buf_u16(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address) { int retval = ERROR_OK; if (count >= 4) - return mem_ap_write_buf_packed_u16(swjdp, buffer, count, address); - - swjdp->trans_mode = TRANS_MODE_COMPOSITE; + return mem_ap_write_buf_packed_u16(dap, buffer, count, address); while (count > 0) { - dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address); + retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address); + if (retval != ERROR_OK) + return retval; uint16_t svalue; memcpy(&svalue, buffer, sizeof(uint16_t)); uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3); - dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue); - retval = swjdp_transaction_endcheck(swjdp); + retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue); + if (retval != ERROR_OK) + break; + + retval = dap_run(dap); + if (retval != ERROR_OK) + break; + count -= 2; address += 2; buffer += 2; @@ -701,14 +455,12 @@ int mem_ap_write_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, return retval; } -static int mem_ap_write_buf_packed_u8(struct swjdp_common *swjdp, +static int mem_ap_write_buf_packed_u8(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address) { int retval = ERROR_OK; int wcount, blocksize, writecount, i; - swjdp->trans_mode = TRANS_MODE_COMPOSITE; - wcount = count; while (wcount > 0) @@ -716,12 +468,14 @@ static int mem_ap_write_buf_packed_u8(struct swjdp_common *swjdp, int nbytes; /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/ - blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address); + blocksize = max_tar_block_size(dap->tar_autoincr_block, address); if (wcount < blocksize) blocksize = wcount; - dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address); + retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, address); + if (retval != ERROR_OK) + return retval; writecount = blocksize; do @@ -730,10 +484,13 @@ static int mem_ap_write_buf_packed_u8(struct swjdp_common *swjdp, if (nbytes < 4) { - if (mem_ap_write_buf_u8(swjdp, buffer, nbytes, address) != ERROR_OK) + retval = mem_ap_write_buf_u8(dap, buffer, nbytes, address); + if (retval != ERROR_OK) { - LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count); - return ERROR_JTAG_DEVICE_ERROR; + LOG_WARNING("Block write error address " + "0x%" PRIx32 ", count 0x%x", + address, count); + return retval; } address += nbytes; @@ -751,11 +508,17 @@ static int mem_ap_write_buf_packed_u8(struct swjdp_common *swjdp, } memcpy(&outvalue, buffer, sizeof(uint32_t)); - dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue); - if (swjdp_transaction_endcheck(swjdp) != ERROR_OK) + retval = dap_queue_ap_write(dap, + AP_REG_DRW, outvalue); + if (retval != ERROR_OK) + break; + + if ((retval = dap_run(dap)) != ERROR_OK) { - LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count); - return ERROR_JTAG_DEVICE_ERROR; + LOG_WARNING("Block write error address " + "0x%" PRIx32 ", count 0x%x", + address, count); + return retval; } } @@ -769,21 +532,27 @@ static int mem_ap_write_buf_packed_u8(struct swjdp_common *swjdp, return retval; } -int mem_ap_write_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) +int mem_ap_write_buf_u8(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address) { int retval = ERROR_OK; if (count >= 4) - return mem_ap_write_buf_packed_u8(swjdp, buffer, count, address); - - swjdp->trans_mode = TRANS_MODE_COMPOSITE; + return mem_ap_write_buf_packed_u8(dap, buffer, count, address); while (count > 0) { - dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address); + retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address); + if (retval != ERROR_OK) + return retval; uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3); - dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue); - retval = swjdp_transaction_endcheck(swjdp); + retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue); + if (retval != ERROR_OK) + break; + + retval = dap_run(dap); + if (retval != ERROR_OK) + break; + count--; address++; buffer++; @@ -792,28 +561,39 @@ int mem_ap_write_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, return retval; } -/********************************************************************************* -* * -* mem_ap_read_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) * -* * -* Read block fast in target order (little endian) into a buffer * -* * -**********************************************************************************/ -int mem_ap_read_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) +/* FIXME don't import ... this is a temporary workaround for the + * mem_ap_read_buf_u32() mess, until it's no longer JTAG-specific. + */ +extern int adi_jtag_dp_scan(struct adiv5_dap *dap, + uint8_t instr, uint8_t reg_addr, uint8_t RnW, + uint8_t *outvalue, uint8_t *invalue, uint8_t *ack); + +/** + * Synchronously read a block of 32-bit words into a buffer + * @param dap The DAP connected to the MEM-AP. + * @param buffer where the words will be stored (in host byte order). + * @param count How many words to read. + * @param address Memory address from which to read words; all the + * words must be readable by the currently selected MEM-AP. + */ +int mem_ap_read_buf_u32(struct adiv5_dap *dap, uint8_t *buffer, + int count, uint32_t address) { int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK; uint32_t adr = address; uint8_t* pBuffer = buffer; - swjdp->trans_mode = TRANS_MODE_COMPOSITE; - count >>= 2; wcount = count; while (wcount > 0) { - /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/ - blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address); + /* Adjust to read blocks within boundaries aligned to the + * TAR autoincrement size (at least 2^10). Autoincrement + * mode avoids an extra per-word roundtrip to update TAR. + */ + blocksize = max_tar_block_size(dap->tar_autoincr_block, + address); if (wcount < blocksize) blocksize = wcount; @@ -821,44 +601,60 @@ int mem_ap_read_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, if (blocksize == 0) blocksize = 1; - dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address); + retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_SINGLE, + address); + if (retval != ERROR_OK) + return retval; + + /* FIXME remove these three calls to adi_jtag_dp_scan(), + * so this routine becomes transport-neutral. Be careful + * not to cause performance problems with JTAG; would it + * suffice to loop over dap_queue_ap_read(), or would that + * be slower when JTAG is the chosen transport? + */ /* Scan out first read */ - adi_jtag_dp_scan(swjdp, JTAG_DP_APACC, AP_REG_DRW, + retval = adi_jtag_dp_scan(dap, JTAG_DP_APACC, AP_REG_DRW, DPAP_READ, 0, NULL, NULL); + if (retval != ERROR_OK) + return retval; for (readcount = 0; readcount < blocksize - 1; readcount++) { /* Scan out next read; scan in posted value for the * previous one. Assumes read is acked "OK/FAULT", * and CTRL_STAT says that meant "OK". */ - adi_jtag_dp_scan(swjdp, JTAG_DP_APACC, AP_REG_DRW, + retval = adi_jtag_dp_scan(dap, JTAG_DP_APACC, AP_REG_DRW, DPAP_READ, 0, buffer + 4 * readcount, - &swjdp->ack); + &dap->ack); + if (retval != ERROR_OK) + return retval; } /* Scan in last posted value; RDBUFF has no other effect, * assuming ack is OK/FAULT and CTRL_STAT says "OK". */ - adi_jtag_dp_scan(swjdp, JTAG_DP_DPACC, DP_RDBUFF, + retval = adi_jtag_dp_scan(dap, JTAG_DP_DPACC, DP_RDBUFF, DPAP_READ, 0, buffer + 4 * readcount, - &swjdp->ack); - if (swjdp_transaction_endcheck(swjdp) == ERROR_OK) - { - wcount = wcount - blocksize; - address += 4 * blocksize; - buffer += 4 * blocksize; - } - else - { - errorcount++; - } + &dap->ack); + if (retval != ERROR_OK) + return retval; - if (errorcount > 1) + retval = dap_run(dap); + if (retval != ERROR_OK) { - LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count); - return ERROR_JTAG_DEVICE_ERROR; + errorcount++; + if (errorcount <= 1) + { + /* try again */ + continue; + } + LOG_WARNING("Block read error address 0x%" PRIx32, address); + return retval; } + wcount = wcount - blocksize; + address += 4 * blocksize; + buffer += 4 * blocksize; } /* if we have an unaligned access - reorder data */ @@ -872,7 +668,8 @@ int mem_ap_read_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, for (i = 0; i < 4; i++) { - *((uint8_t*)pBuffer) = (data >> 8 * (adr & 0x3)); + *((uint8_t*)pBuffer) = + (data >> 8 * (adr & 0x3)); pBuffer++; adr++; } @@ -882,15 +679,13 @@ int mem_ap_read_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, return retval; } -static int mem_ap_read_buf_packed_u16(struct swjdp_common *swjdp, +static int mem_ap_read_buf_packed_u16(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address) { uint32_t invalue; int retval = ERROR_OK; int wcount, blocksize, readcount, i; - swjdp->trans_mode = TRANS_MODE_COMPOSITE; - wcount = count >> 1; while (wcount > 0) @@ -898,11 +693,13 @@ static int mem_ap_read_buf_packed_u16(struct swjdp_common *swjdp, int nbytes; /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/ - blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address); + blocksize = max_tar_block_size(dap->tar_autoincr_block, address); if (wcount < blocksize) blocksize = wcount; - dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address); + retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_PACKED, address); + if (retval != ERROR_OK) + return retval; /* handle unaligned data at 4k boundary */ if (blocksize == 0) @@ -911,11 +708,13 @@ static int mem_ap_read_buf_packed_u16(struct swjdp_common *swjdp, do { - dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue); - if (swjdp_transaction_endcheck(swjdp) != ERROR_OK) + retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue); + if (retval != ERROR_OK) + return retval; + if ((retval = dap_run(dap)) != ERROR_OK) { LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count); - return ERROR_JTAG_DEVICE_ERROR; + return retval; } nbytes = MIN((readcount << 1), 4); @@ -935,21 +734,36 @@ static int mem_ap_read_buf_packed_u16(struct swjdp_common *swjdp, return retval; } -int mem_ap_read_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) +/** + * Synchronously read a block of 16-bit halfwords into a buffer + * @param dap The DAP connected to the MEM-AP. + * @param buffer where the halfwords will be stored (in host byte order). + * @param count How many halfwords to read. + * @param address Memory address from which to read words; all the + * words must be readable by the currently selected MEM-AP. + */ +int mem_ap_read_buf_u16(struct adiv5_dap *dap, uint8_t *buffer, + int count, uint32_t address) { uint32_t invalue, i; int retval = ERROR_OK; if (count >= 4) - return mem_ap_read_buf_packed_u16(swjdp, buffer, count, address); - - swjdp->trans_mode = TRANS_MODE_COMPOSITE; + return mem_ap_read_buf_packed_u16(dap, buffer, count, address); while (count > 0) { - dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address); - dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue); - retval = swjdp_transaction_endcheck(swjdp); + retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address); + if (retval != ERROR_OK) + return retval; + retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue); + if (retval != ERROR_OK) + break; + + retval = dap_run(dap); + if (retval != ERROR_OK) + break; + if (address & 0x1) { for (i = 0; i < 2; i++) @@ -978,15 +792,13 @@ int mem_ap_read_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, * The solution is to arrange for a large out/in scan in this loop and * and convert data afterwards. */ -static int mem_ap_read_buf_packed_u8(struct swjdp_common *swjdp, +static int mem_ap_read_buf_packed_u8(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address) { uint32_t invalue; int retval = ERROR_OK; int wcount, blocksize, readcount, i; - swjdp->trans_mode = TRANS_MODE_COMPOSITE; - wcount = count; while (wcount > 0) @@ -994,21 +806,25 @@ static int mem_ap_read_buf_packed_u8(struct swjdp_common *swjdp, int nbytes; /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/ - blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address); + blocksize = max_tar_block_size(dap->tar_autoincr_block, address); if (wcount < blocksize) blocksize = wcount; - dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address); + retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, address); + if (retval != ERROR_OK) + return retval; readcount = blocksize; do { - dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue); - if (swjdp_transaction_endcheck(swjdp) != ERROR_OK) + retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue); + if (retval != ERROR_OK) + return retval; + if ((retval = dap_run(dap)) != ERROR_OK) { LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count); - return ERROR_JTAG_DEVICE_ERROR; + return retval; } nbytes = MIN(readcount, 4); @@ -1028,21 +844,35 @@ static int mem_ap_read_buf_packed_u8(struct swjdp_common *swjdp, return retval; } -int mem_ap_read_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) +/** + * Synchronously read a block of bytes into a buffer + * @param dap The DAP connected to the MEM-AP. + * @param buffer where the bytes will be stored. + * @param count How many bytes to read. + * @param address Memory address from which to read data; all the + * data must be readable by the currently selected MEM-AP. + */ +int mem_ap_read_buf_u8(struct adiv5_dap *dap, uint8_t *buffer, + int count, uint32_t address) { uint32_t invalue; int retval = ERROR_OK; if (count >= 4) - return mem_ap_read_buf_packed_u8(swjdp, buffer, count, address); - - swjdp->trans_mode = TRANS_MODE_COMPOSITE; + return mem_ap_read_buf_packed_u8(dap, buffer, count, address); while (count > 0) { - dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address); - dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue); - retval = swjdp_transaction_endcheck(swjdp); + retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address); + if (retval != ERROR_OK) + return retval; + retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue); + if (retval != ERROR_OK) + return retval; + retval = dap_run(dap); + if (retval != ERROR_OK) + break; + *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3)); count--; address++; @@ -1052,14 +882,29 @@ int mem_ap_read_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, u return retval; } +/*--------------------------------------------------------------------------*/ + + +/* FIXME don't import ... just initialize as + * part of DAP transport setup +*/ +extern const struct dap_ops jtag_dp_ops; + +/*--------------------------------------------------------------------------*/ + /** - * Initialize a DAP. + * Initialize a DAP. This sets up the power domains, prepares the DP + * for further use, and arranges to use AP #0 for all AP operations + * until dap_ap-select() changes that policy. + * + * @param dap The DAP being initialized. * * @todo Rename this. We also need an initialization scheme which account * for SWD transports not just JTAG; that will need to address differences * in layering. (JTAG is useful without any debug target; but not SWD.) + * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP. */ -int ahbap_debugport_init(struct swjdp_common *swjdp) +int ahbap_debugport_init(struct adiv5_dap *dap) { uint32_t idreg, romaddr, dummy; uint32_t ctrlstat; @@ -1068,53 +913,77 @@ int ahbap_debugport_init(struct swjdp_common *swjdp) LOG_DEBUG(" "); + /* JTAG-DP or SWJ-DP, in JTAG mode */ + dap->ops = &jtag_dp_ops; + /* Default MEM-AP setup. * * REVISIT AP #0 may be an inappropriate default for this. - * Should we probe, or receve a hint from the caller? + * Should we probe, or take a hint from the caller? * Presumably we can ignore the possibility of multiple APs. */ - swjdp->apsel = 0; - swjdp->ap_csw_value = -1; - swjdp->ap_tar_value = -1; + dap->apsel = !0; + dap_ap_select(dap, 0); /* DP initialization */ - swjdp->trans_mode = TRANS_MODE_ATOMIC; - dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT); - dap_dp_write_reg(swjdp, SSTICKYERR, DP_CTRL_STAT); - dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT); - swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ; + retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &dummy); + if (retval != ERROR_OK) + return retval; + + retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR); + if (retval != ERROR_OK) + return retval; + + retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &dummy); + if (retval != ERROR_OK) + return retval; + + dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ; + retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat); + if (retval != ERROR_OK) + return retval; - dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT); - dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT); - if ((retval = jtag_execute_queue()) != ERROR_OK) + retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat); + if (retval != ERROR_OK) + return retval; + if ((retval = dap_run(dap)) != ERROR_OK) return retval; /* Check that we have debug power domains activated */ while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10)) { - LOG_DEBUG("swjdp: wait CDBGPWRUPACK"); - dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT); - if ((retval = jtag_execute_queue()) != ERROR_OK) + LOG_DEBUG("DAP: wait CDBGPWRUPACK"); + retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat); + if (retval != ERROR_OK) + return retval; + if ((retval = dap_run(dap)) != ERROR_OK) return retval; alive_sleep(10); } while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10)) { - LOG_DEBUG("swjdp: wait CSYSPWRUPACK"); - dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT); - if ((retval = jtag_execute_queue()) != ERROR_OK) + LOG_DEBUG("DAP: wait CSYSPWRUPACK"); + retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat); + if (retval != ERROR_OK) + return retval; + if ((retval = dap_run(dap)) != ERROR_OK) return retval; alive_sleep(10); } - dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT); + retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &dummy); + if (retval != ERROR_OK) + return retval; /* With debug power on we can activate OVERRUN checking */ - swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT; - dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT); - dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT); + dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT; + retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat); + if (retval != ERROR_OK) + return retval; + retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &dummy); + if (retval != ERROR_OK) + return retval; /* * REVISIT this isn't actually *initializing* anything in an AP, @@ -1122,10 +991,19 @@ int ahbap_debugport_init(struct swjdp_common *swjdp) * Should it? If the ROM address is valid, is this the right * place to scan the table and do any topology detection? */ - dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &idreg); - dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &romaddr); + retval = dap_queue_ap_read(dap, AP_REG_IDR, &idreg); + if (retval != ERROR_OK) + return retval; + retval = dap_queue_ap_read(dap, AP_REG_BASE, &romaddr); + if (retval != ERROR_OK) + return retval; - LOG_DEBUG("AHB-AP ID Register 0x%" PRIx32 ", Debug ROM Address 0x%" PRIx32 "", idreg, romaddr); + if ((retval = dap_run(dap)) != ERROR_OK) + return retval; + + LOG_DEBUG("MEM-AP #%" PRId32 " ID Register 0x%" PRIx32 + ", Debug ROM Address 0x%" PRIx32, + dap->apsel, idreg, romaddr); return ERROR_OK; } @@ -1148,19 +1026,31 @@ is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0) && ((cid1 & 0x0f) == 0) && cid0 == 0x0d; } -int dap_info_command(struct command_context *cmd_ctx, struct swjdp_common *swjdp, int apsel) +static int dap_info_command(struct command_context *cmd_ctx, + struct adiv5_dap *dap, int apsel) { - + int retval; uint32_t dbgbase, apid; int romtable_present = 0; uint8_t mem_ap; uint32_t apselold; - apselold = swjdp->apsel; - dap_ap_select(swjdp, apsel); - dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &dbgbase); - dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid); - swjdp_transaction_endcheck(swjdp); + /* AP address is in bits 31:24 of DP_SELECT */ + if (apsel >= 256) + return ERROR_INVALID_ARGUMENTS; + + apselold = dap->apsel; + dap_ap_select(dap, apsel); + retval = dap_queue_ap_read(dap, AP_REG_BASE, &dbgbase); + if (retval != ERROR_OK) + return retval; + retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid); + if (retval != ERROR_OK) + return retval; + retval = dap_run(dap); + if (retval != ERROR_OK) + return retval; + /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */ mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0)); command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid); @@ -1207,18 +1097,32 @@ int dap_info_command(struct command_context *cmd_ctx, struct swjdp_common *swjdp command_print(cmd_ctx, "\tROM table in legacy format"); /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */ - mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF0, &cid0); - mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF4, &cid1); - mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF8, &cid2); - mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFFC, &cid3); - mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFCC, &memtype); - swjdp_transaction_endcheck(swjdp); + retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF0, &cid0); + if (retval != ERROR_OK) + return retval; + retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF4, &cid1); + if (retval != ERROR_OK) + return retval; + retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF8, &cid2); + if (retval != ERROR_OK) + return retval; + retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFFC, &cid3); + if (retval != ERROR_OK) + return retval; + retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFCC, &memtype); + if (retval != ERROR_OK) + return retval; + retval = dap_run(dap); + if (retval != ERROR_OK) + return retval; + if (!is_dap_cid_ok(cid3, cid2, cid1, cid0)) - command_print(cmd_ctx, "\tCID3 0x%2.2" PRIx32 - ", CID2 0x%2.2" PRIx32 - ", CID1 0x%2.2" PRIx32 - ", CID0 0x%2.2" PRIx32, - cid3, cid2, cid1, cid0); + command_print(cmd_ctx, "\tCID3 0x%2.2x" + ", CID2 0x%2.2x" + ", CID1 0x%2.2x" + ", CID0 0x%2.2x", + (unsigned) cid3, (unsigned)cid2, + (unsigned) cid1, (unsigned) cid0); if (memtype & 0x01) command_print(cmd_ctx, "\tMEMTYPE system memory present on bus"); else @@ -1229,41 +1133,78 @@ int dap_info_command(struct command_context *cmd_ctx, struct swjdp_common *swjdp entry_offset = 0; do { - mem_ap_read_atomic_u32(swjdp, (dbgbase&0xFFFFF000) | entry_offset, &romentry); + retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) | entry_offset, &romentry); + if (retval != ERROR_OK) + return retval; command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "",entry_offset,romentry); if (romentry&0x01) { uint32_t c_cid0, c_cid1, c_cid2, c_cid3; uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4; - uint32_t component_start, component_base; + uint32_t component_base; unsigned part_num; char *type, *full; - component_base = (uint32_t)((dbgbase & 0xFFFFF000) - + (int)(romentry & 0xFFFFF000)); - mem_ap_read_atomic_u32(swjdp, - (component_base & 0xFFFFF000) | 0xFE0, &c_pid0); - mem_ap_read_atomic_u32(swjdp, - (component_base & 0xFFFFF000) | 0xFE4, &c_pid1); - mem_ap_read_atomic_u32(swjdp, - (component_base & 0xFFFFF000) | 0xFE8, &c_pid2); - mem_ap_read_atomic_u32(swjdp, - (component_base & 0xFFFFF000) | 0xFEC, &c_pid3); - mem_ap_read_atomic_u32(swjdp, - (component_base & 0xFFFFF000) | 0xFD0, &c_pid4); - mem_ap_read_atomic_u32(swjdp, - (component_base & 0xFFFFF000) | 0xFF0, &c_cid0); - mem_ap_read_atomic_u32(swjdp, - (component_base & 0xFFFFF000) | 0xFF4, &c_cid1); - mem_ap_read_atomic_u32(swjdp, - (component_base & 0xFFFFF000) | 0xFF8, &c_cid2); - mem_ap_read_atomic_u32(swjdp, - (component_base & 0xFFFFF000) | 0xFFC, &c_cid3); - component_start = component_base - 0x1000*(c_pid4 >> 4); - - command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32 - ", start address 0x%" PRIx32, - component_base, component_start); + component_base = (dbgbase & 0xFFFFF000) + + (romentry & 0xFFFFF000); + + /* IDs are in last 4K section */ + + + retval = mem_ap_read_atomic_u32(dap, + component_base + 0xFE0, &c_pid0); + if (retval != ERROR_OK) + return retval; + c_pid0 &= 0xff; + retval = mem_ap_read_atomic_u32(dap, + component_base + 0xFE4, &c_pid1); + if (retval != ERROR_OK) + return retval; + c_pid1 &= 0xff; + retval = mem_ap_read_atomic_u32(dap, + component_base + 0xFE8, &c_pid2); + if (retval != ERROR_OK) + return retval; + c_pid2 &= 0xff; + retval = mem_ap_read_atomic_u32(dap, + component_base + 0xFEC, &c_pid3); + if (retval != ERROR_OK) + return retval; + c_pid3 &= 0xff; + retval = mem_ap_read_atomic_u32(dap, + component_base + 0xFD0, &c_pid4); + if (retval != ERROR_OK) + return retval; + c_pid4 &= 0xff; + + retval = mem_ap_read_atomic_u32(dap, + component_base + 0xFF0, &c_cid0); + if (retval != ERROR_OK) + return retval; + c_cid0 &= 0xff; + retval = mem_ap_read_atomic_u32(dap, + component_base + 0xFF4, &c_cid1); + if (retval != ERROR_OK) + return retval; + c_cid1 &= 0xff; + retval = mem_ap_read_atomic_u32(dap, + component_base + 0xFF8, &c_cid2); + if (retval != ERROR_OK) + return retval; + c_cid2 &= 0xff; + retval = mem_ap_read_atomic_u32(dap, + component_base + 0xFFC, &c_cid3); + if (retval != ERROR_OK) + return retval; + c_cid3 &= 0xff; + + + command_print(cmd_ctx, + "\t\tComponent base address 0x%" PRIx32 + ", start address 0x%" PRIx32, + component_base, + /* component may take multiple 4K pages */ + component_base - 0x1000*(c_pid4 >> 4)); command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s", (int) (c_cid1 >> 4) & 0xf, /* See ARM IHI 0029B Table 3-3 */ @@ -1275,9 +1216,11 @@ int dap_info_command(struct command_context *cmd_ctx, struct swjdp_common *swjdp unsigned minor; char *major = "Reserved", *subtype = "Reserved"; - mem_ap_read_atomic_u32(swjdp, + retval = mem_ap_read_atomic_u32(dap, (component_base & 0xfffff000) | 0xfcc, &devtype); + if (retval != ERROR_OK) + return retval; minor = (devtype >> 4) & 0x0f; switch (devtype & 0x0f) { case 0: @@ -1381,23 +1324,27 @@ int dap_info_command(struct command_context *cmd_ctx, struct swjdp_common *swjdp } if (!is_dap_cid_ok(cid3, cid2, cid1, cid0)) - command_print(cmd_ctx, "\t\tCID3 0x%2.2" PRIx32 - ", CID2 0x%2.2" PRIx32 - ", CID1 0x%2.2" PRIx32 - ", CID0 0x%2.2" PRIx32, - c_cid3, c_cid2, c_cid1, c_cid0); - command_print(cmd_ctx, "\t\tPeripheral ID[4..0] = hex " - "%2.2x %2.2x %2.2x %2.2x %2.2x", - (int) c_pid4, - (int) c_pid3, (int) c_pid2, - (int) c_pid1, (int) c_pid0); + command_print(cmd_ctx, + "\t\tCID3 0%2.2x" + ", CID2 0%2.2x" + ", CID1 0%2.2x" + ", CID0 0%2.2x", + (int) c_cid3, + (int) c_cid2, + (int)c_cid1, + (int)c_cid0); + command_print(cmd_ctx, + "\t\tPeripheral ID[4..0] = hex " + "%2.2x %2.2x %2.2x %2.2x %2.2x", + (int) c_pid4, (int) c_pid3, (int) c_pid2, + (int) c_pid1, (int) c_pid0); /* Part number interpretations are from Cortex * core specs, the CoreSight components TRM * (ARM DDI 0314H), and ETM specs; also from * chip observation (e.g. TI SDTI). */ - part_num = c_pid0 & 0xff; + part_num = (c_pid0 & 0xff); part_num |= (c_pid1 & 0x0f) << 8; switch (part_num) { case 0x000: @@ -1429,10 +1376,6 @@ int dap_info_command(struct command_context *cmd_ctx, struct swjdp_common *swjdp type = "TI DAPCTL"; full = ""; break; - case 0x4e0: - type = "Cortex-M3 ETM"; - full = "(Embedded Trace)"; - break; case 0x906: type = "Coresight CTI"; full = "(Cross Trigger)"; @@ -1465,6 +1408,10 @@ int dap_info_command(struct command_context *cmd_ctx, struct swjdp_common *swjdp type = "Cortex-M3 TPIU"; full = "(Trace Port Interface Unit)"; break; + case 0x924: + type = "Cortex-M3 ETM"; + full = "(Embedded Trace)"; + break; case 0xc08: type = "Cortex-A8 Debug"; full = "(Debug Unit)"; @@ -1491,48 +1438,90 @@ int dap_info_command(struct command_context *cmd_ctx, struct swjdp_common *swjdp { command_print(cmd_ctx, "\tNo ROM table present"); } - dap_ap_select(swjdp, apselold); + dap_ap_select(dap, apselold); return ERROR_OK; } -DAP_COMMAND_HANDLER(dap_baseaddr_command) +COMMAND_HANDLER(handle_dap_info_command) { + struct target *target = get_current_target(CMD_CTX); + struct arm *arm = target_to_arm(target); + struct adiv5_dap *dap = arm->dap; + uint32_t apsel; + + switch (CMD_ARGC) { + case 0: + apsel = dap->apsel; + break; + case 1: + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel); + break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; + } + + return dap_info_command(CMD_CTX, dap, apsel); +} + +COMMAND_HANDLER(dap_baseaddr_command) +{ + struct target *target = get_current_target(CMD_CTX); + struct arm *arm = target_to_arm(target); + struct adiv5_dap *dap = arm->dap; + uint32_t apsel, apselsave, baseaddr; int retval; - apselsave = swjdp->apsel; + apselsave = dap->apsel; switch (CMD_ARGC) { case 0: - apsel = swjdp->apsel; + apsel = dap->apsel; break; case 1: COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel); + /* AP address is in bits 31:24 of DP_SELECT */ + if (apsel >= 256) + return ERROR_INVALID_ARGUMENTS; break; default: return ERROR_COMMAND_SYNTAX_ERROR; } if (apselsave != apsel) - dap_ap_select(swjdp, apsel); + dap_ap_select(dap, apsel); + + /* NOTE: assumes we're talking to a MEM-AP, which + * has a base address. There are other kinds of AP, + * though they're not common for now. This should + * use the ID register to verify it's a MEM-AP. + */ + retval = dap_queue_ap_read(dap, AP_REG_BASE, &baseaddr); + if (retval != ERROR_OK) + return retval; + retval = dap_run(dap); + if (retval != ERROR_OK) + return retval; - dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &baseaddr); - retval = swjdp_transaction_endcheck(swjdp); command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr); if (apselsave != apsel) - dap_ap_select(swjdp, apselsave); + dap_ap_select(dap, apselsave); return retval; } -DAP_COMMAND_HANDLER(dap_memaccess_command) +COMMAND_HANDLER(dap_memaccess_command) { + struct target *target = get_current_target(CMD_CTX); + struct arm *arm = target_to_arm(target); + struct adiv5_dap *dap = arm->dap; + uint32_t memaccess_tck; switch (CMD_ARGC) { case 0: - memaccess_tck = swjdp->memaccess_tck; + memaccess_tck = dap->memaccess_tck; break; case 1: COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck); @@ -1540,16 +1529,20 @@ DAP_COMMAND_HANDLER(dap_memaccess_command) default: return ERROR_COMMAND_SYNTAX_ERROR; } - swjdp->memaccess_tck = memaccess_tck; + dap->memaccess_tck = memaccess_tck; command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck", - swjdp->memaccess_tck); + dap->memaccess_tck); return ERROR_OK; } -DAP_COMMAND_HANDLER(dap_apsel_command) +COMMAND_HANDLER(dap_apsel_command) { + struct target *target = get_current_target(CMD_CTX); + struct arm *arm = target_to_arm(target); + struct adiv5_dap *dap = arm->dap; + uint32_t apsel, apid; int retval; @@ -1559,45 +1552,121 @@ DAP_COMMAND_HANDLER(dap_apsel_command) break; case 1: COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel); + /* AP address is in bits 31:24 of DP_SELECT */ + if (apsel >= 256) + return ERROR_INVALID_ARGUMENTS; break; default: return ERROR_COMMAND_SYNTAX_ERROR; } - dap_ap_select(swjdp, apsel); - dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid); - retval = swjdp_transaction_endcheck(swjdp); + dap_ap_select(dap, apsel); + retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid); + if (retval != ERROR_OK) + return retval; + retval = dap_run(dap); + if (retval != ERROR_OK) + return retval; + command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32, apsel, apid); return retval; } -DAP_COMMAND_HANDLER(dap_apid_command) +COMMAND_HANDLER(dap_apid_command) { + struct target *target = get_current_target(CMD_CTX); + struct arm *arm = target_to_arm(target); + struct adiv5_dap *dap = arm->dap; + uint32_t apsel, apselsave, apid; int retval; - apselsave = swjdp->apsel; + apselsave = dap->apsel; switch (CMD_ARGC) { case 0: - apsel = swjdp->apsel; + apsel = dap->apsel; break; case 1: COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel); + /* AP address is in bits 31:24 of DP_SELECT */ + if (apsel >= 256) + return ERROR_INVALID_ARGUMENTS; break; default: return ERROR_COMMAND_SYNTAX_ERROR; } if (apselsave != apsel) - dap_ap_select(swjdp, apsel); + dap_ap_select(dap, apsel); + + retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid); + if (retval != ERROR_OK) + return retval; + retval = dap_run(dap); + if (retval != ERROR_OK) + return retval; - dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid); - retval = swjdp_transaction_endcheck(swjdp); command_print(CMD_CTX, "0x%8.8" PRIx32, apid); if (apselsave != apsel) - dap_ap_select(swjdp, apselsave); + dap_ap_select(dap, apselsave); return retval; } + +static const struct command_registration dap_commands[] = { + { + .name = "info", + .handler = handle_dap_info_command, + .mode = COMMAND_EXEC, + .help = "display ROM table for MEM-AP " + "(default currently selected AP)", + .usage = "[ap_num]", + }, + { + .name = "apsel", + .handler = dap_apsel_command, + .mode = COMMAND_EXEC, + .help = "Set the currently selected AP (default 0) " + "and display the result", + .usage = "[ap_num]", + }, + { + .name = "apid", + .handler = dap_apid_command, + .mode = COMMAND_EXEC, + .help = "return ID register from AP " + "(default currently selected AP)", + .usage = "[ap_num]", + }, + { + .name = "baseaddr", + .handler = dap_baseaddr_command, + .mode = COMMAND_EXEC, + .help = "return debug base address from MEM-AP " + "(default currently selected AP)", + .usage = "[ap_num]", + }, + { + .name = "memaccess", + .handler = dap_memaccess_command, + .mode = COMMAND_EXEC, + .help = "set/get number of extra tck for MEM-AP memory " + "bus access [0-255]", + .usage = "[cycles]", + }, + COMMAND_REGISTRATION_DONE +}; + +const struct command_registration dap_command_handlers[] = { + { + .name = "dap", + .mode = COMMAND_EXEC, + .help = "DAP command group", + .chain = dap_commands, + }, + COMMAND_REGISTRATION_DONE +}; + +