X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm_adi_v5.c;h=146f89f4a3fc6591d8501eea1dc5e073afefdf12;hp=2584dbc6f24537d976dc447e45f0b42e606050ab;hb=0e2c2fe1d1eec5482078147d551215a58604cc3a;hpb=53d605e12c3765aeedabf2bfe0c5cc338dc95d5a diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c index 2584dbc6f2..146f89f4a3 100644 --- a/src/target/arm_adi_v5.c +++ b/src/target/arm_adi_v5.c @@ -1027,7 +1027,7 @@ int dap_info_command(struct command_context_s *cmd_ctx, swjdp_common_t *swjdp, i dap_ap_read_reg_u32(swjdp, 0xFC, &apid); swjdp_transaction_endcheck(swjdp); /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */ - mem_ap = ((apid&0x10000)&&((apid&0x0F) != 0)); + mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0)); command_print(cmd_ctx, "ap identification register 0x%8.8" PRIx32 "", apid); if (apid) { @@ -1053,7 +1053,7 @@ int dap_info_command(struct command_context_s *cmd_ctx, swjdp_common_t *swjdp, i command_print(cmd_ctx, "No AP found at this apsel 0x%x", apsel); } - romtable_present = ((mem_ap)&&(dbgbase != 0xFFFFFFFF)); + romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF)); if (romtable_present) { uint32_t cid0,cid1,cid2,cid3,memtype,romentry; @@ -1103,12 +1103,12 @@ int dap_info_command(struct command_context_s *cmd_ctx, swjdp_common_t *swjdp, i mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFF4, &c_cid1); mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFF8, &c_cid2); mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFFC, &c_cid3); - component_start = component_base - 0x1000*(c_pid4>>4); + component_start = component_base - 0x1000*(c_pid4 >> 4); command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32 ", pid4 0x%" PRIx32 ", start address 0x%" PRIx32 "",component_base,c_pid4,component_start); - command_print(cmd_ctx, "\t\tComponent cid1 0x%" PRIx32 ", class is %s",c_cid1,class_description[(c_cid1>>4)&0xF]); /* Se ARM DDI 0314 C Table 2.2 */ + command_print(cmd_ctx, "\t\tComponent cid1 0x%" PRIx32 ", class is %s",c_cid1,class_description[(c_cid1 >> 4)&0xF]); /* Se ARM DDI 0314 C Table 2.2 */ command_print(cmd_ctx, "\t\tCID3 0x%" PRIx32 ", CID2 0x%" PRIx32 ", CID1 0x%" PRIx32 ", CID0, 0x%" PRIx32 "",c_cid3,c_cid2,c_cid1,c_cid0); command_print(cmd_ctx, "\t\tPID3 0x%" PRIx32 ", PID2 0x%" PRIx32 ", PID1 0x%" PRIx32 ", PID0, 0x%" PRIx32 "",c_pid3,c_pid2,c_pid1,c_pid0); - /* For CoreSight components, (c_cid1>>4)&0xF==9 , we also read 0xFC8 DevId and 0xFCC DevType */ + /* For CoreSight components, (c_cid1 >> 4)&0xF==9 , we also read 0xFC8 DevId and 0xFCC DevType */ } else {