X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm9tdmi.c;h=c468282bc8e9503c5935dc8830fa48b3ec07f0c1;hp=b582eae3319ea3cff8efe2d4a29a1965c64d623b;hb=refs%2Fchanges%2F26%2F1426%2F4;hpb=7bf1a86e473a12882bf6f71cb4d0d416394b69d4 diff --git a/src/target/arm9tdmi.c b/src/target/arm9tdmi.c index b582eae331..c468282bc8 100644 --- a/src/target/arm9tdmi.c +++ b/src/target/arm9tdmi.c @@ -21,8 +21,9 @@ * You should have received a copy of the GNU General Public License * * along with this program; if not, write to the * * Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * ***************************************************************************/ + #ifdef HAVE_CONFIG_H #include "config.h" #endif @@ -30,7 +31,7 @@ #include "arm9tdmi.h" #include "target_type.h" #include "register.h" - +#include "arm_opcodes.h" /* * NOTE: this holds code that's used with multiple ARM9 processors: @@ -46,8 +47,7 @@ #define _DEBUG_INSTRUCTION_EXECUTION_ #endif -enum arm9tdmi_vector_bit -{ +enum arm9tdmi_vector_bit { ARM9TDMI_RESET_VECTOR = 0x01, ARM9TDMI_UNDEF_VECTOR = 0x02, ARM9TDMI_SWI_VECTOR = 0x04, @@ -59,7 +59,7 @@ enum arm9tdmi_vector_bit }; static const struct arm9tdmi_vector { - char *name; + const char *name; uint32_t value; } arm9tdmi_vectors[] = { {"reset", ARM9TDMI_RESET_VECTOR}, @@ -79,41 +79,35 @@ int arm9tdmi_examine_debug_reason(struct target *target) /* only check the debug reason if we don't know it already */ if ((target->debug_reason != DBG_REASON_DBGRQ) - && (target->debug_reason != DBG_REASON_SINGLESTEP)) - { + && (target->debug_reason != DBG_REASON_SINGLESTEP)) { struct scan_field fields[3]; uint8_t databus[4]; uint8_t instructionbus[4]; uint8_t debug_reason; - jtag_set_end_state(TAP_DRPAUSE); - - fields[0].tap = arm7_9->jtag_info.tap; fields[0].num_bits = 32; fields[0].out_value = NULL; fields[0].in_value = databus; - fields[1].tap = arm7_9->jtag_info.tap; fields[1].num_bits = 3; fields[1].out_value = NULL; fields[1].in_value = &debug_reason; - fields[2].tap = arm7_9->jtag_info.tap; fields[2].num_bits = 32; fields[2].out_value = NULL; fields[2].in_value = instructionbus; - if ((retval = arm_jtag_scann(&arm7_9->jtag_info, 0x1)) != ERROR_OK) - { + retval = arm_jtag_scann(&arm7_9->jtag_info, 0x1, TAP_DRPAUSE); + if (retval != ERROR_OK) + return retval; + retval = arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL, TAP_DRPAUSE); + if (retval != ERROR_OK) return retval; - } - arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL); - jtag_add_dr_scan(3, fields, jtag_set_end_state(TAP_DRPAUSE)); - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + jtag_add_dr_scan(arm7_9->jtag_info.tap, 3, fields, TAP_DRPAUSE); + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; - } fields[0].in_value = NULL; fields[0].out_value = databus; @@ -122,7 +116,7 @@ int arm9tdmi_examine_debug_reason(struct target *target) fields[2].in_value = NULL; fields[2].out_value = instructionbus; - jtag_add_dr_scan(3, fields, jtag_set_end_state(TAP_DRPAUSE)); + jtag_add_dr_scan(arm7_9->jtag_info.tap, 3, fields, TAP_DRPAUSE); if (debug_reason & 0x4) if (debug_reason & 0x2) @@ -156,54 +150,44 @@ int arm9tdmi_clock_out(struct arm_jtag *jtag_info, uint32_t instr, if (sysspeed) buf_set_u32(&sysspeed_buf, 2, 1, 1); - jtag_set_end_state(TAP_DRPAUSE); - if ((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK) - { + retval = arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE); + if (retval != ERROR_OK) return retval; - } - arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); + retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE); + if (retval != ERROR_OK) + return retval; - fields[0].tap = jtag_info->tap; fields[0].num_bits = 32; fields[0].out_value = out_buf; fields[0].in_value = NULL; - fields[1].tap = jtag_info->tap; fields[1].num_bits = 3; fields[1].out_value = &sysspeed_buf; fields[1].in_value = NULL; - fields[2].tap = jtag_info->tap; fields[2].num_bits = 32; fields[2].out_value = instr_buf; fields[2].in_value = NULL; - if (in) - { + if (in) { fields[0].in_value = (uint8_t *)in; - jtag_add_dr_scan(3, fields, jtag_get_end_state()); + jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_DRPAUSE); jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)in); - } - else - { - jtag_add_dr_scan(3, fields, jtag_get_end_state()); - } + } else + jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_DRPAUSE); - jtag_add_runtest(0, jtag_get_end_state()); + jtag_add_runtest(0, TAP_DRPAUSE); #ifdef _DEBUG_INSTRUCTION_EXECUTION_ { - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; - } if (in) - { LOG_DEBUG("instr: 0x%8.8x, out: 0x%8.8x, in: 0x%8.8x", instr, out, *in); - } else LOG_DEBUG("instr: 0x%8.8x, out: 0x%8.8x", instr, out); } @@ -215,71 +199,51 @@ int arm9tdmi_clock_out(struct arm_jtag *jtag_info, uint32_t instr, /* just read data (instruction and data-out = don't care) */ int arm9tdmi_clock_data_in(struct arm_jtag *jtag_info, uint32_t *in) { - int retval = ERROR_OK;; + int retval = ERROR_OK; struct scan_field fields[3]; - jtag_set_end_state(TAP_DRPAUSE); - if ((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK) - { + retval = arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE); + if (retval != ERROR_OK) return retval; - } - arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); + retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE); + if (retval != ERROR_OK) + return retval; - fields[0].tap = jtag_info->tap; fields[0].num_bits = 32; fields[0].out_value = NULL; fields[0].in_value = (uint8_t *)in; - fields[1].tap = jtag_info->tap; fields[1].num_bits = 3; fields[1].out_value = NULL; fields[1].in_value = NULL; - fields[2].tap = jtag_info->tap; fields[2].num_bits = 32; fields[2].out_value = NULL; fields[2].in_value = NULL; - jtag_add_dr_scan(3, fields, jtag_get_end_state()); + jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_DRPAUSE); jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)in); - jtag_add_runtest(0, jtag_get_end_state()); + jtag_add_runtest(0, TAP_DRPAUSE); #ifdef _DEBUG_INSTRUCTION_EXECUTION_ { - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; - } if (in) - { LOG_DEBUG("in: 0x%8.8x", *in); - } else - { LOG_ERROR("BUG: called with in == NULL"); - } } #endif return ERROR_OK; } -extern void arm_endianness(uint8_t *tmp, void *in, int size, int be, int flip); - -static int arm9endianness(jtag_callback_data_t arg, - jtag_callback_data_t size, jtag_callback_data_t be, - jtag_callback_data_t captured) -{ - uint8_t *in = (uint8_t *)arg; - - arm_endianness((uint8_t *)captured, in, (int)size, (int)be, 0); - return ERROR_OK; -} - /* clock the target, and read the databus * the *in pointer points to a buffer where elements of 'size' bytes * are stored in big (be == 1) or little (be == 0) endianness @@ -288,52 +252,56 @@ int arm9tdmi_clock_data_in_endianness(struct arm_jtag *jtag_info, void *in, int size, int be) { int retval = ERROR_OK; - struct scan_field fields[3]; + struct scan_field fields[2]; - jtag_set_end_state(TAP_DRPAUSE); - if ((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK) - { + retval = arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE); + if (retval != ERROR_OK) return retval; - } - arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); + retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE); + if (retval != ERROR_OK) + return retval; - fields[0].tap = jtag_info->tap; - fields[0].num_bits = 32; - fields[0].out_value = NULL; - jtag_alloc_in_value32(&fields[0]); + if (size == 4) { + fields[0].num_bits = 32; + fields[0].out_value = NULL; + fields[0].in_value = in; - fields[1].tap = jtag_info->tap; - fields[1].num_bits = 3; - fields[1].out_value = NULL; - fields[1].in_value = NULL; + fields[1].num_bits = 3 + 32; + fields[1].out_value = NULL; + fields[1].in_value = NULL; + } else { + /* Discard irrelevant bits of the scan, making sure we don't write more + * than size bytes to in */ + fields[0].num_bits = size * 8; + fields[0].out_value = NULL; + fields[0].in_value = in; - fields[2].tap = jtag_info->tap; - fields[2].num_bits = 32; - fields[2].out_value = NULL; - fields[2].in_value = NULL; + fields[1].num_bits = 3 + 32 + 32 - size * 8; + fields[1].out_value = NULL; + fields[1].in_value = NULL; + } - jtag_add_dr_scan(3, fields, jtag_get_end_state()); + jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_DRPAUSE); - jtag_add_callback4(arm9endianness, (jtag_callback_data_t)in, (jtag_callback_data_t)size, (jtag_callback_data_t)be, (jtag_callback_data_t)fields[0].in_value); + jtag_add_callback4(arm7_9_endianness_callback, + (jtag_callback_data_t)in, + (jtag_callback_data_t)size, + (jtag_callback_data_t)be, + (jtag_callback_data_t)0); - jtag_add_runtest(0, jtag_get_end_state()); + jtag_add_runtest(0, TAP_DRPAUSE); #ifdef _DEBUG_INSTRUCTION_EXECUTION_ { - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; - } if (in) - { - LOG_DEBUG("in: 0x%8.8x", *(uint32_t*)in); - } + LOG_DEBUG("in: 0x%8.8x", *(uint32_t *)in); else - { LOG_ERROR("BUG: called with in == NULL"); - } } #endif @@ -382,10 +350,9 @@ static void arm9tdmi_change_to_arm(struct target *target, /* NOP fetched, BX in Execute (1) */ arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0); - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return; - } /* fix program counter: * MOV r0, r15 was the 5th instruction (+8) @@ -395,7 +362,7 @@ static void arm9tdmi_change_to_arm(struct target *target, } void arm9tdmi_read_core_regs(struct target *target, - uint32_t mask, uint32_t* core_regs[16]) + uint32_t mask, uint32_t *core_regs[16]) { int i; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); @@ -411,8 +378,7 @@ void arm9tdmi_read_core_regs(struct target *target, /* fetch NOP, STM in EXECUTE stage (1st cycle) */ arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); - for (i = 0; i <= 15; i++) - { + for (i = 0; i <= 15; i++) { if (mask & (1 << i)) /* nothing fetched, STM in MEMORY (i'th cycle) */ arm9tdmi_clock_data_in(jtag_info, core_regs[i]); @@ -420,7 +386,7 @@ void arm9tdmi_read_core_regs(struct target *target, } static void arm9tdmi_read_core_regs_target_buffer(struct target *target, - uint32_t mask, void* buffer, int size) + uint32_t mask, void *buffer, int size) { int i; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); @@ -440,12 +406,10 @@ static void arm9tdmi_read_core_regs_target_buffer(struct target *target, /* fetch NOP, STM in EXECUTE stage (1st cycle) */ arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); - for (i = 0; i <= 15; i++) - { + for (i = 0; i <= 15; i++) { if (mask & (1 << i)) /* nothing fetched, STM in MEMORY (i'th cycle) */ - switch (size) - { + switch (size) { case 4: arm9tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be); break; @@ -531,8 +495,7 @@ static void arm9tdmi_write_xpsr_im8(struct target *target, arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); /* rot == 4 writes flags, which takes only one cycle */ - if (rot != 4) - { + if (rot != 4) { /* nothing fetched, MSR in EXECUTE (2) */ arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); /* nothing fetched, MSR in EXECUTE (3) */ @@ -557,8 +520,7 @@ void arm9tdmi_write_core_regs(struct target *target, /* fetch NOP, LDM in EXECUTE stage (1st cycle) */ arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); - for (i = 0; i <= 15; i++) - { + for (i = 0; i <= 15; i++) { if (mask & (1 << i)) /* nothing fetched, LDM still in EXECUTE (1 + i cycle) */ arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, core_regs[i], NULL, 0); @@ -664,7 +626,7 @@ static void arm9tdmi_branch_resume_thumb(struct target *target) LOG_DEBUG("-"); struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; + struct arm *arm = &arm7_9->arm; struct arm_jtag *jtag_info = &arm7_9->jtag_info; struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; @@ -678,7 +640,8 @@ static void arm9tdmi_branch_resume_thumb(struct target *target) /* fetch NOP, LDM in EXECUTE stage (1st cycle) */ arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); /* nothing fetched, LDM in EXECUTE stage (2nd cycle) */ - arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32) | 1, NULL, 0); + arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, + buf_get_u32(arm->pc->value, 0, 32) | 1, NULL, 0); /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */ arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); @@ -705,7 +668,8 @@ static void arm9tdmi_branch_resume_thumb(struct target *target) /* fetch NOP, LDR in Execute */ arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0); /* nothing fetched, LDR in EXECUTE stage (2nd cycle) */ - arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32), NULL, 0); + arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, + buf_get_u32(arm->core_cache->reg_list[0].value, 0, 32), NULL, 0); /* nothing fetched, LDR in EXECUTE stage (3rd cycle) */ arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0); @@ -722,39 +686,30 @@ void arm9tdmi_enable_single_step(struct target *target, uint32_t next_pc) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - if (arm7_9->has_single_step) - { + if (arm7_9->has_single_step) { buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 1); embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]); - } - else - { + } else arm7_9_enable_eice_step(target, next_pc); - } } void arm9tdmi_disable_single_step(struct target *target) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - if (arm7_9->has_single_step) - { + if (arm7_9->has_single_step) { buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 0); embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]); - } - else - { + } else arm7_9_disable_eice_step(target); - } } static void arm9tdmi_build_reg_cache(struct target *target) { struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache); - struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); + struct arm *arm = target_to_arm(target); - (*cache_p) = armv4_5_build_reg_cache(target, armv4_5); - armv4_5->core_cache = (*cache_p); + (*cache_p) = arm_build_reg_cache(target, arm); } int arm9tdmi_init_target(struct command_context *cmd_ctx, @@ -800,7 +755,6 @@ int arm9tdmi_init_arch_info(struct target *target, arm7_9->post_debug_entry = NULL; arm7_9->pre_restore_context = NULL; - arm7_9->post_restore_context = NULL; /* initialize arch-specific breakpoint handling */ arm7_9->arm_bkpt = 0xdeeedeee; @@ -821,25 +775,30 @@ int arm9tdmi_init_arch_info(struct target *target, static int arm9tdmi_target_create(struct target *target, Jim_Interp *interp) { - struct arm7_9_common *arm7_9 = calloc(1,sizeof(struct arm7_9_common)); + struct arm7_9_common *arm7_9 = calloc(1, sizeof(struct arm7_9_common)); arm9tdmi_init_arch_info(target, arm7_9, target->tap); - arm7_9->armv4_5_common.is_armv4 = true; + arm7_9->arm.is_armv4 = true; return ERROR_OK; } COMMAND_HANDLER(handle_arm9tdmi_catch_vectors_command) { - struct target *target = get_current_target(cmd_ctx); + struct target *target = get_current_target(CMD_CTX); struct arm7_9_common *arm7_9 = target_to_arm7_9(target); struct reg *vector_catch; uint32_t vector_catch_value; + if (!target_was_examined(target)) { + LOG_ERROR("Target not examined yet"); + return ERROR_FAIL; + } + /* it's uncommon, but some ARM7 chips can support this */ if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC || !arm7_9->has_vector_catch) { - command_print(cmd_ctx, "target doesn't have EmbeddedICE " + command_print(CMD_CTX, "target doesn't have EmbeddedICE " "with vector_catch"); return ERROR_TARGET_INVALID; } @@ -853,42 +812,31 @@ COMMAND_HANDLER(handle_arm9tdmi_catch_vectors_command) /* get the current setting */ vector_catch_value = buf_get_u32(vector_catch->value, 0, 8); - if (CMD_ARGC > 0) - { + if (CMD_ARGC > 0) { vector_catch_value = 0x0; - if (strcmp(args[0], "all") == 0) - { + if (strcmp(CMD_ARGV[0], "all") == 0) vector_catch_value = 0xdf; - } - else if (strcmp(args[0], "none") == 0) - { + else if (strcmp(CMD_ARGV[0], "none") == 0) { /* do nothing */ - } - else - { - for (unsigned i = 0; i < CMD_ARGC; i++) - { + } else { + for (unsigned i = 0; i < CMD_ARGC; i++) { /* go through list of vectors */ unsigned j; - for (j = 0; arm9tdmi_vectors[j].name; j++) - { - if (strcmp(args[i], arm9tdmi_vectors[j].name) == 0) - { + for (j = 0; arm9tdmi_vectors[j].name; j++) { + if (strcmp(CMD_ARGV[i], arm9tdmi_vectors[j].name) == 0) { vector_catch_value |= arm9tdmi_vectors[j].value; break; } } /* complain if vector wasn't found */ - if (!arm9tdmi_vectors[j].name) - { - command_print(cmd_ctx, "vector '%s' not found, leaving current setting unchanged", args[i]); + if (!arm9tdmi_vectors[j].name) { + command_print(CMD_CTX, "vector '%s' not found, leaving current setting unchanged", CMD_ARGV[i]); /* reread current setting */ vector_catch_value = buf_get_u32( vector_catch->value, 0, 8); - break; } } @@ -901,7 +849,7 @@ COMMAND_HANDLER(handle_arm9tdmi_catch_vectors_command) /* output current settings */ for (unsigned i = 0; arm9tdmi_vectors[i].name; i++) { - command_print(cmd_ctx, "%s: %s", arm9tdmi_vectors[i].name, + command_print(CMD_CTX, "%s: %s", arm9tdmi_vectors[i].name, (vector_catch_value & arm9tdmi_vectors[i].value) ? "catch" : "don't catch"); } @@ -909,29 +857,37 @@ COMMAND_HANDLER(handle_arm9tdmi_catch_vectors_command) return ERROR_OK; } -int arm9tdmi_register_commands(struct command_context *cmd_ctx) -{ - int retval; - struct command *arm9tdmi_cmd; - - retval = arm7_9_register_commands(cmd_ctx); - arm9tdmi_cmd = register_command(cmd_ctx, NULL, "arm9", - NULL, COMMAND_ANY, - "arm9 specific commands"); - register_command(cmd_ctx, arm9tdmi_cmd, "vector_catch", - handle_arm9tdmi_catch_vectors_command, COMMAND_EXEC, - "arm9 vector_catch [all|none|reset|undef|swi|pabt|dabt|irq|fiq] ..."); - - return retval; -} +static const struct command_registration arm9tdmi_exec_command_handlers[] = { + { + .name = "vector_catch", + .handler = handle_arm9tdmi_catch_vectors_command, + .mode = COMMAND_EXEC, + .help = "Display, after optionally updating, configuration " + "of vector catch unit.", + .usage = "[all|none|(reset|undef|swi|pabt|dabt|irq|fiq)*]", + }, + COMMAND_REGISTRATION_DONE +}; +const struct command_registration arm9tdmi_command_handlers[] = { + { + .chain = arm7_9_command_handlers, + }, + { + .name = "arm9", + .mode = COMMAND_ANY, + .help = "arm9 command group", + .usage = "", + .chain = arm9tdmi_exec_command_handlers, + }, + COMMAND_REGISTRATION_DONE +}; /** Holds methods for ARM9TDMI targets. */ -struct target_type arm9tdmi_target = -{ +struct target_type arm9tdmi_target = { .name = "arm9tdmi", .poll = arm7_9_poll, - .arch_state = armv4_5_arch_state, + .arch_state = arm_arch_state, .target_request_data = arm7_9_target_request_data, @@ -943,7 +899,7 @@ struct target_type arm9tdmi_target = .deassert_reset = arm7_9_deassert_reset, .soft_reset_halt = arm7_9_soft_reset_halt, - .get_gdb_reg_list = armv4_5_get_gdb_reg_list, + .get_gdb_reg_list = arm_get_gdb_reg_list, .read_memory = arm7_9_read_memory, .write_memory = arm7_9_write_memory, @@ -959,8 +915,9 @@ struct target_type arm9tdmi_target = .add_watchpoint = arm7_9_add_watchpoint, .remove_watchpoint = arm7_9_remove_watchpoint, - .register_commands = arm9tdmi_register_commands, + .commands = arm9tdmi_command_handlers, .target_create = arm9tdmi_target_create, .init_target = arm9tdmi_init_target, .examine = arm7_9_examine, + .check_reset = arm7_9_check_reset, };