X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm9tdmi.c;h=3179a6137e669a3f6518cd56fe1ea877ead7bc98;hp=15ce8dcb1235ecac244b874ea9ee3fcf636828db;hb=8959de9f679cfd0436d731fd91b88a68b9a75fa6;hpb=0bba832713cca8e5931d5d21f37f526d0a3979cf diff --git a/src/target/arm9tdmi.c b/src/target/arm9tdmi.c index 15ce8dcb12..3179a6137e 100644 --- a/src/target/arm9tdmi.c +++ b/src/target/arm9tdmi.c @@ -28,33 +28,19 @@ #endif #include "arm9tdmi.h" +#include "target_type.h" -#include "arm7_9_common.h" -#include "register.h" -#include "target.h" -#include "armv4_5.h" -#include "embeddedice.h" -#include "etm.h" -#include "etb.h" -#include "log.h" -#include "jtag.h" -#include "arm_jtag.h" - -#include -#include #if 0 #define _DEBUG_INSTRUCTION_EXECUTION_ #endif /* cli handling */ -int arm9tdmi_register_commands(struct command_context_s *cmd_ctx); int handle_arm9tdmi_catch_vectors_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); /* forward declarations */ int arm9tdmi_target_create( struct target_s *target, Jim_Interp *interp ); -int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target); int arm9tdmi_quit(void); target_type_t arm9tdmi_target = @@ -121,50 +107,35 @@ int arm9tdmi_examine_debug_reason(target_t *target) && (target->debug_reason != DBG_REASON_SINGLESTEP)) { scan_field_t fields[3]; - u8 databus[4]; - u8 instructionbus[4]; - u8 debug_reason; + uint8_t databus[4]; + uint8_t instructionbus[4]; + uint8_t debug_reason; - jtag_add_end_state(TAP_DRPAUSE); + jtag_set_end_state(TAP_DRPAUSE); fields[0].tap = arm7_9->jtag_info.tap; fields[0].num_bits = 32; fields[0].out_value = NULL; - fields[0].out_mask = NULL; fields[0].in_value = databus; - fields[0].in_check_value = NULL; - fields[0].in_check_mask = NULL; - fields[0].in_handler = NULL; - fields[0].in_handler_priv = NULL; fields[1].tap = arm7_9->jtag_info.tap; fields[1].num_bits = 3; fields[1].out_value = NULL; - fields[1].out_mask = NULL; fields[1].in_value = &debug_reason; - fields[1].in_check_value = NULL; - fields[1].in_check_mask = NULL; - fields[1].in_handler = NULL; - fields[1].in_handler_priv = NULL; fields[2].tap = arm7_9->jtag_info.tap; fields[2].num_bits = 32; fields[2].out_value = NULL; - fields[2].out_mask = NULL; fields[2].in_value = instructionbus; - fields[2].in_check_value = NULL; - fields[2].in_check_mask = NULL; - fields[2].in_handler = NULL; - fields[2].in_handler_priv = NULL; - if((retval = arm_jtag_scann(&arm7_9->jtag_info, 0x1)) != ERROR_OK) + if ((retval = arm_jtag_scann(&arm7_9->jtag_info, 0x1)) != ERROR_OK) { return retval; } arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL); - jtag_add_dr_scan(3, fields, TAP_DRPAUSE); - if((retval = jtag_execute_queue()) != ERROR_OK) + jtag_add_dr_scan(3, fields, jtag_set_end_state(TAP_DRPAUSE)); + if ((retval = jtag_execute_queue()) != ERROR_OK) { return retval; } @@ -176,7 +147,7 @@ int arm9tdmi_examine_debug_reason(target_t *target) fields[2].in_value = NULL; fields[2].out_value = instructionbus; - jtag_add_dr_scan(3, fields, TAP_DRPAUSE); + jtag_add_dr_scan(3, fields, jtag_set_end_state(TAP_DRPAUSE)); if (debug_reason & 0x4) if (debug_reason & 0x2) @@ -191,13 +162,13 @@ int arm9tdmi_examine_debug_reason(target_t *target) } /* put an instruction in the ARM9TDMI pipeline or write the data bus, and optionally read data */ -int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int sysspeed) +int arm9tdmi_clock_out(arm_jtag_t *jtag_info, uint32_t instr, uint32_t out, uint32_t *in, int sysspeed) { int retval = ERROR_OK; scan_field_t fields[3]; - u8 out_buf[4]; - u8 instr_buf[4]; - u8 sysspeed_buf = 0x0; + uint8_t out_buf[4]; + uint8_t instr_buf[4]; + uint8_t sysspeed_buf = 0x0; /* prepare buffer */ buf_set_u32(out_buf, 0, 32, out); @@ -207,8 +178,8 @@ int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int s if (sysspeed) buf_set_u32(&sysspeed_buf, 2, 1, 1); - jtag_add_end_state(TAP_DRPAUSE); - if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK) + jtag_set_end_state(TAP_DRPAUSE); + if ((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK) { return retval; } @@ -218,48 +189,35 @@ int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int s fields[0].tap = jtag_info->tap; fields[0].num_bits = 32; fields[0].out_value = out_buf; - fields[0].out_mask = NULL; fields[0].in_value = NULL; - if (in) - { - fields[0].in_handler = arm_jtag_buf_to_u32; - fields[0].in_handler_priv = in; - } - else - { - fields[0].in_handler = NULL; - fields[0].in_handler_priv = NULL; - } - fields[0].in_check_value = NULL; - fields[0].in_check_mask = NULL; fields[1].tap = jtag_info->tap; fields[1].num_bits = 3; fields[1].out_value = &sysspeed_buf; - fields[1].out_mask = NULL; fields[1].in_value = NULL; - fields[1].in_check_value = NULL; - fields[1].in_check_mask = NULL; - fields[1].in_handler = NULL; - fields[1].in_handler_priv = NULL; fields[2].tap = jtag_info->tap; fields[2].num_bits = 32; fields[2].out_value = instr_buf; - fields[2].out_mask = NULL; fields[2].in_value = NULL; - fields[2].in_check_value = NULL; - fields[2].in_check_mask = NULL; - fields[2].in_handler = NULL; - fields[2].in_handler_priv = NULL; - jtag_add_dr_scan(3, fields, TAP_INVALID); + if (in) + { + fields[0].in_value = (uint8_t *)in; + jtag_add_dr_scan(3, fields, jtag_get_end_state()); + + jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)in); + } + else + { + jtag_add_dr_scan(3, fields, jtag_get_end_state()); + } - jtag_add_runtest(0, TAP_INVALID); + jtag_add_runtest(0, jtag_get_end_state()); #ifdef _DEBUG_INSTRUCTION_EXECUTION_ { - if((retval = jtag_execute_queue()) != ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) { return retval; } @@ -277,13 +235,13 @@ int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int s } /* just read data (instruction and data-out = don't care) */ -int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in) +int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, uint32_t *in) { int retval = ERROR_OK;; scan_field_t fields[3]; - jtag_add_end_state(TAP_DRPAUSE); - if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK) + jtag_set_end_state(TAP_DRPAUSE); + if ((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK) { return retval; } @@ -293,40 +251,27 @@ int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in) fields[0].tap = jtag_info->tap; fields[0].num_bits = 32; fields[0].out_value = NULL; - fields[0].out_mask = NULL; - fields[0].in_value = NULL; - fields[0].in_handler = arm_jtag_buf_to_u32; - fields[0].in_handler_priv = in; - fields[0].in_check_value = NULL; - fields[0].in_check_mask = NULL; + fields[0].in_value = (uint8_t *)in; fields[1].tap = jtag_info->tap; fields[1].num_bits = 3; fields[1].out_value = NULL; - fields[1].out_mask = NULL; fields[1].in_value = NULL; - fields[1].in_handler = NULL; - fields[1].in_handler_priv = NULL; - fields[1].in_check_value = NULL; - fields[1].in_check_mask = NULL; fields[2].tap = jtag_info->tap; fields[2].num_bits = 32; fields[2].out_value = NULL; - fields[2].out_mask = NULL; fields[2].in_value = NULL; - fields[2].in_check_value = NULL; - fields[2].in_check_mask = NULL; - fields[2].in_handler = NULL; - fields[2].in_handler_priv = NULL; - jtag_add_dr_scan(3, fields, TAP_INVALID); + jtag_add_dr_scan(3, fields, jtag_get_end_state()); + + jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)in); - jtag_add_runtest(0, TAP_INVALID); + jtag_add_runtest(0, jtag_get_end_state()); #ifdef _DEBUG_INSTRUCTION_EXECUTION_ { - if((retval = jtag_execute_queue()) != ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) { return retval; } @@ -345,17 +290,26 @@ int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in) return ERROR_OK; } +extern void arm_endianness(uint8_t *tmp, void *in, int size, int be, int flip); + +static int arm9endianness(jtag_callback_data_t arg, jtag_callback_data_t size, jtag_callback_data_t be, jtag_callback_data_t captured) +{ + uint8_t *in = (uint8_t *)arg; + arm_endianness((uint8_t *)captured, in, (int)size, (int)be, 0); + return ERROR_OK; +} + /* clock the target, and read the databus * the *in pointer points to a buffer where elements of 'size' bytes - * are stored in big (be==1) or little (be==0) endianness + * are stored in big (be == 1) or little (be == 0) endianness */ int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, int be) { int retval = ERROR_OK; scan_field_t fields[3]; - jtag_add_end_state(TAP_DRPAUSE); - if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK) + jtag_set_end_state(TAP_DRPAUSE); + if ((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK) { return retval; } @@ -365,58 +319,34 @@ int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, fields[0].tap = jtag_info->tap; fields[0].num_bits = 32; fields[0].out_value = NULL; - fields[0].out_mask = NULL; - fields[0].in_value = NULL; - switch (size) - { - case 4: - fields[0].in_handler = (be) ? arm_jtag_buf_to_be32 : arm_jtag_buf_to_le32; - break; - case 2: - fields[0].in_handler = (be) ? arm_jtag_buf_to_be16 : arm_jtag_buf_to_le16; - break; - case 1: - fields[0].in_handler = arm_jtag_buf_to_8; - break; - } - fields[0].in_handler_priv = in; - fields[0].in_check_value = NULL; - fields[0].in_check_mask = NULL; + jtag_alloc_in_value32(&fields[0]); fields[1].tap = jtag_info->tap; fields[1].num_bits = 3; fields[1].out_value = NULL; - fields[1].out_mask = NULL; fields[1].in_value = NULL; - fields[1].in_handler = NULL; - fields[1].in_handler_priv = NULL; - fields[1].in_check_value = NULL; - fields[1].in_check_mask = NULL; fields[2].tap = jtag_info->tap; fields[2].num_bits = 32; fields[2].out_value = NULL; - fields[2].out_mask = NULL; fields[2].in_value = NULL; - fields[2].in_check_value = NULL; - fields[2].in_check_mask = NULL; - fields[2].in_handler = NULL; - fields[2].in_handler_priv = NULL; - jtag_add_dr_scan(3, fields, TAP_INVALID); + jtag_add_dr_scan(3, fields, jtag_get_end_state()); - jtag_add_runtest(0, TAP_INVALID); + jtag_add_callback4(arm9endianness, (jtag_callback_data_t)in, (jtag_callback_data_t)size, (jtag_callback_data_t)be, (jtag_callback_data_t)fields[0].in_value); + + jtag_add_runtest(0, jtag_get_end_state()); #ifdef _DEBUG_INSTRUCTION_EXECUTION_ { - if((retval = jtag_execute_queue()) != ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) { return retval; } if (in) { - LOG_DEBUG("in: 0x%8.8x", *(u32*)in); + LOG_DEBUG("in: 0x%8.8x", *(uint32_t*)in); } else { @@ -428,7 +358,7 @@ int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, return ERROR_OK; } -void arm9tdmi_change_to_arm(target_t *target, u32 *r0, u32 *pc) +void arm9tdmi_change_to_arm(target_t *target, uint32_t *r0, uint32_t *pc) { int retval = ERROR_OK; /* get pointers to arch-specific information */ @@ -471,7 +401,7 @@ void arm9tdmi_change_to_arm(target_t *target, u32 *r0, u32 *pc) /* NOP fetched, BX in Execute (1) */ arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0); - if((retval = jtag_execute_queue()) != ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) { return; } @@ -483,7 +413,7 @@ void arm9tdmi_change_to_arm(target_t *target, u32 *r0, u32 *pc) *pc -= 0xc; } -void arm9tdmi_read_core_regs(target_t *target, u32 mask, u32* core_regs[16]) +void arm9tdmi_read_core_regs(target_t *target, uint32_t mask, uint32_t* core_regs[16]) { int i; /* get pointers to arch-specific information */ @@ -509,7 +439,7 @@ void arm9tdmi_read_core_regs(target_t *target, u32 mask, u32* core_regs[16]) } } -void arm9tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buffer, int size) +void arm9tdmi_read_core_regs_target_buffer(target_t *target, uint32_t mask, void* buffer, int size) { int i; /* get pointers to arch-specific information */ @@ -517,9 +447,9 @@ void arm9tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buf arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info; int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0; - u32 *buf_u32 = buffer; - u16 *buf_u16 = buffer; - u8 *buf_u8 = buffer; + uint32_t *buf_u32 = buffer; + uint16_t *buf_u16 = buffer; + uint8_t *buf_u8 = buffer; /* STMIA r0-15, [r0] at debug speed * register values will start to appear on 4th DCLK @@ -550,7 +480,7 @@ void arm9tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buf } } -void arm9tdmi_read_xpsr(target_t *target, u32 *xpsr, int spsr) +void arm9tdmi_read_xpsr(target_t *target, uint32_t *xpsr, int spsr) { /* get pointers to arch-specific information */ armv4_5_common_t *armv4_5 = target->arch_info; @@ -574,14 +504,14 @@ void arm9tdmi_read_xpsr(target_t *target, u32 *xpsr, int spsr) arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, xpsr, 0); } -void arm9tdmi_write_xpsr(target_t *target, u32 xpsr, int spsr) +void arm9tdmi_write_xpsr(target_t *target, uint32_t xpsr, int spsr) { /* get pointers to arch-specific information */ armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info; - LOG_DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr); + LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr); /* MSR1 fetched */ arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), 0, NULL, 0); @@ -610,7 +540,7 @@ void arm9tdmi_write_xpsr(target_t *target, u32 xpsr, int spsr) arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); } -void arm9tdmi_write_xpsr_im8(target_t *target, u8 xpsr_im, int rot, int spsr) +void arm9tdmi_write_xpsr_im8(target_t *target, uint8_t xpsr_im, int rot, int spsr) { /* get pointers to arch-specific information */ armv4_5_common_t *armv4_5 = target->arch_info; @@ -636,7 +566,7 @@ void arm9tdmi_write_xpsr_im8(target_t *target, u8 xpsr_im, int rot, int spsr) } } -void arm9tdmi_write_core_regs(target_t *target, u32 mask, u32 core_regs[16]) +void arm9tdmi_write_core_regs(target_t *target, uint32_t mask, uint32_t core_regs[16]) { int i; /* get pointers to arch-specific information */ @@ -657,13 +587,13 @@ void arm9tdmi_write_core_regs(target_t *target, u32 mask, u32 core_regs[16]) for (i = 0; i <= 15; i++) { if (mask & (1 << i)) - /* nothing fetched, LDM still in EXECUTE (1+i cycle) */ + /* nothing fetched, LDM still in EXECUTE (1 + i cycle) */ arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, core_regs[i], NULL, 0); } arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); } -void arm9tdmi_load_word_regs(target_t *target, u32 mask) +void arm9tdmi_load_word_regs(target_t *target, uint32_t mask) { /* get pointers to arch-specific information */ armv4_5_common_t *armv4_5 = target->arch_info; @@ -699,7 +629,7 @@ void arm9tdmi_load_byte_reg(target_t *target, int num) arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1); } -void arm9tdmi_store_word_regs(target_t *target, u32 mask) +void arm9tdmi_store_word_regs(target_t *target, uint32_t mask) { /* get pointers to arch-specific information */ armv4_5_common_t *armv4_5 = target->arch_info; @@ -735,7 +665,7 @@ void arm9tdmi_store_byte_reg(target_t *target, int num) arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1); } -void arm9tdmi_write_pc(target_t *target, u32 pc) +void arm9tdmi_write_pc(target_t *target, uint32_t pc) { /* get pointers to arch-specific information */ armv4_5_common_t *armv4_5 = target->arch_info; @@ -832,7 +762,7 @@ void arm9tdmi_branch_resume_thumb(target_t *target) arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0); } -void arm9tdmi_enable_single_step(target_t *target, u32 next_pc) +void arm9tdmi_enable_single_step(target_t *target, uint32_t next_pc) { /* get pointers to arch-specific information */ armv4_5_common_t *armv4_5 = target->arch_info; @@ -882,13 +812,13 @@ int arm9tdmi_examine(struct target_s *target) int retval; armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; - if (!target->type->examined) + if (!target_was_examined(target)) { reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache); reg_cache_t *t; /* one extra register (vector catch) */ - t=embeddedice_build_reg_cache(target, arm7_9); - if (t==NULL) + t = embeddedice_build_reg_cache(target, arm7_9); + if (t == NULL) return ERROR_FAIL; (*cache_p) = t; arm7_9->eice_cache = (*cache_p); @@ -899,15 +829,15 @@ int arm9tdmi_examine(struct target_s *target) (*cache_p)->next = etm_build_reg_cache(target, jtag_info, arm7_9->etm_ctx); arm7_9->etm_ctx->reg_cache = (*cache_p)->next; } - target->type->examined = 1; + target_set_examined(target); } - if ((retval=embeddedice_setup(target))!=ERROR_OK) + if ((retval = embeddedice_setup(target)) != ERROR_OK) return retval; - if ((retval=arm7_9_setup(target))!=ERROR_OK) + if ((retval = arm7_9_setup(target)) != ERROR_OK) return retval; if (arm7_9->etm_ctx) { - if ((retval=etm_setup(target))!=ERROR_OK) + if ((retval = etm_setup(target)) != ERROR_OK) return retval; } return ERROR_OK; @@ -1034,11 +964,11 @@ int arm9tdmi_register_commands(struct command_context_s *cmd_ctx) { int retval; command_t *arm9tdmi_cmd; - + retval = arm7_9_register_commands(cmd_ctx); arm9tdmi_cmd = register_command(cmd_ctx, NULL, "arm9tdmi", NULL, COMMAND_ANY, "arm9tdmi specific commands"); register_command(cmd_ctx, arm9tdmi_cmd, "vector_catch", handle_arm9tdmi_catch_vectors_command, COMMAND_EXEC, "catch arm920t vectors ['all'|'none'|'']"); - + return retval; } @@ -1049,7 +979,7 @@ int handle_arm9tdmi_catch_vectors_command(struct command_context_s *cmd_ctx, cha arm7_9_common_t *arm7_9; arm9tdmi_common_t *arm9tdmi; reg_t *vector_catch; - u32 vector_catch_value; + uint32_t vector_catch_value; int i, j; if (arm9tdmi_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi) != ERROR_OK) @@ -1083,7 +1013,7 @@ int handle_arm9tdmi_catch_vectors_command(struct command_context_s *cmd_ctx, cha for (i = 0; i < argc; i++) { /* go through list of vectors */ - for(j = 0; arm9tdmi_vectors[j].name; j++) + for (j = 0; arm9tdmi_vectors[j].name; j++) { if (strcmp(args[i], arm9tdmi_vectors[j].name) == 0) {