X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm966e.c;h=4ba5d8526334f887e23abb4d11207bb2e49dc511;hp=f5f4a209f2b012fd36f8d628243acf3d44657bde;hb=3d6bcf07921753141a3905ee5619724573460cb3;hpb=a582e9a8d183c56d1aa8ae18afc1c11e2cbd6d2d diff --git a/src/target/arm966e.c b/src/target/arm966e.c index f5f4a209f2..4ba5d85263 100644 --- a/src/target/arm966e.c +++ b/src/target/arm966e.c @@ -43,8 +43,6 @@ int arm966e_register_commands(struct command_context_s *cmd_ctx); /* forward declarations */ -int arm966e_deassert_reset(target_t *target); -int arm966e_assert_reset(target_t *target); int arm966e_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target); int arm966e_init_target(struct command_context_s *cmd_ctx, struct target_s *target); int arm966e_quit(void); @@ -56,20 +54,24 @@ target_type_t arm966e_target = .poll = arm7_9_poll, .arch_state = armv4_5_arch_state, + .target_request_data = arm7_9_target_request_data, + .halt = arm7_9_halt, .resume = arm7_9_resume, .step = arm7_9_step, - .assert_reset = arm966e_assert_reset, - .deassert_reset = arm966e_deassert_reset, + .assert_reset = arm7_9_assert_reset, + .deassert_reset = arm7_9_deassert_reset, .soft_reset_halt = arm7_9_soft_reset_halt, + .prepare_reset_halt = arm7_9_prepare_reset_halt, .get_gdb_reg_list = armv4_5_get_gdb_reg_list, .read_memory = arm7_9_read_memory, .write_memory = arm7_9_write_memory, .bulk_write_memory = arm7_9_bulk_write_memory, - + .checksum_memory = arm7_9_checksum_memory, + .run_algorithm = armv4_5_run_algorithm, .add_breakpoint = arm7_9_add_breakpoint, @@ -83,127 +85,6 @@ target_type_t arm966e_target = .quit = arm966e_quit, }; -int arm966e_assert_reset(target_t *target) -{ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info; - arm966e_common_t *arm966e = arm9tdmi->arch_info; - reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; - int retval; - int trst_asserted_with_srt = 0; - - arm966e->monitor_mode_set = 1; - - DEBUG("target->state: %s", target_state_strings[target->state]); - - if (target->state == TARGET_HALTED || target->state == TARGET_UNKNOWN) - { - /* assert SRST and TRST */ - /* system would get ouf sync if we didn't reset test-logic, too */ - if ((retval = jtag_add_reset(1, 1)) != ERROR_OK) - { - if (retval == ERROR_JTAG_RESET_CANT_SRST) - { - WARNING("can't assert srst"); - return retval; - } - else - { - ERROR("unknown error"); - exit(-1); - } - } - jtag_add_sleep(5000); - if ((retval = jtag_add_reset(0, 1)) != ERROR_OK) - { - if (retval == ERROR_JTAG_RESET_WOULD_ASSERT_TRST) - { - WARNING("srst resets test logic, too"); - retval = jtag_add_reset(1, 1); - trst_asserted_with_srt = 1; - } - } - } - else - { - if ((retval = jtag_add_reset(0, 1)) != ERROR_OK) - { - if (retval == ERROR_JTAG_RESET_WOULD_ASSERT_TRST) - { - WARNING("srst resets test logic, too"); - retval = jtag_add_reset(1, 1); - trst_asserted_with_srt = 1; - } - - if (retval == ERROR_JTAG_RESET_CANT_SRST) - { - WARNING("can't assert srst"); - return retval; - } - else if (retval != ERROR_OK) - { - ERROR("unknown error"); - exit(-1); - } - } - } - - target->state = TARGET_RESET; - jtag_add_sleep(50000); - - armv4_5_invalidate_core_regs(target); - - if( trst_asserted_with_srt == 0 ) - { - DEBUG("monitor mode needs clearing"); - - /* arm9e monitor mode enabled at reset */ - embeddedice_read_reg(dbg_ctrl); - jtag_execute_queue(); - - if(buf_get_u32(dbg_ctrl->value, EICE_DBG_CONTROL_MONEN, 1)) - { - buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_MONEN, 1, 0); - embeddedice_store_reg(dbg_ctrl); - DEBUG("monitor mode disabled"); - } - arm966e->monitor_mode_set = 0; - } - - return ERROR_OK; -} - -int arm966e_deassert_reset(target_t *target) -{ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info; - arm966e_common_t *arm966e = arm9tdmi->arch_info; - reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; - - arm7_9_deassert_reset( target ); - - if( arm966e->monitor_mode_set == 1 ) - { - DEBUG("monitor mode needs clearing"); - - /* arm9e monitor mode enabled at reset */ - embeddedice_read_reg(dbg_ctrl); - jtag_execute_queue(); - - if(buf_get_u32(dbg_ctrl->value, EICE_DBG_CONTROL_MONEN, 1)) - { - buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_MONEN, 1, 0); - embeddedice_store_reg(dbg_ctrl); - arm966e->monitor_mode_set = 0; - DEBUG("monitor mode disabled"); - } - } - - return ERROR_OK; -} - int arm966e_init_target(struct command_context_s *cmd_ctx, struct target_s *target) { arm9tdmi_init_target(cmd_ctx, target); @@ -220,14 +101,21 @@ int arm966e_quit(void) int arm966e_init_arch_info(target_t *target, arm966e_common_t *arm966e, int chain_pos, char *variant) { arm9tdmi_common_t *arm9tdmi = &arm966e->arm9tdmi_common; + arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common; arm9tdmi_init_arch_info(target, arm9tdmi, chain_pos, variant); arm9tdmi->arch_info = arm966e; arm966e->common_magic = ARM966E_COMMON_MAGIC; - arm9tdmi->has_single_step = 0; - arm9tdmi->has_monitor_mode = 1; + /* The ARM966E-S implements the ARMv5TE architecture which + * has the BKPT instruction, so we don't have to use a watchpoint comparator + */ + arm7_9->arm_bkpt = ARMV5_BKPT(0x0); + arm7_9->thumb_bkpt = ARMV5_T_BKPT(0x0) & 0xffff; + + arm7_9->sw_bkpts_use_wp = 0; + arm7_9->sw_bkpts_enabled = 1; return ERROR_OK; } @@ -305,7 +193,7 @@ int arm966e_read_cp15(target_t *target, int reg_addr, u32 *value) jtag_add_end_state(TAP_RTI); arm_jtag_scann(jtag_info, 0xf); - arm_jtag_set_instr(jtag_info, jtag_info->intest_instr); + arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); fields[0].device = jtag_info->chain_pos; fields[0].num_bits = 32; @@ -339,10 +227,16 @@ int arm966e_read_cp15(target_t *target, int reg_addr, u32 *value) jtag_add_dr_scan(3, fields, -1); - fields[0].in_value = (u8*)value; + fields[0].in_handler_priv = value; + fields[0].in_handler = arm_jtag_buf_to_u32; jtag_add_dr_scan(3, fields, -1); +#ifdef _DEBUG_INSTRUCTION_EXECUTION_ + jtag_execute_queue(); + DEBUG("addr: 0x%x value: %8.8x", reg_addr, *value); +#endif + return ERROR_OK; } @@ -354,14 +248,17 @@ int arm966e_write_cp15(target_t *target, int reg_addr, u32 value) scan_field_t fields[3]; u8 reg_addr_buf = reg_addr & 0x3f; u8 nr_w_buf = 1; + u8 value_buf[4]; + + buf_set_u32(value_buf, 0, 32, value); jtag_add_end_state(TAP_RTI); arm_jtag_scann(jtag_info, 0xf); - arm_jtag_set_instr(jtag_info, jtag_info->intest_instr); + arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); fields[0].device = jtag_info->chain_pos; fields[0].num_bits = 32; - fields[0].out_value = (u8*)&value; + fields[0].out_value = value_buf; fields[0].out_mask = NULL; fields[0].in_value = NULL; fields[0].in_check_value = NULL; @@ -391,6 +288,10 @@ int arm966e_write_cp15(target_t *target, int reg_addr, u32 value) jtag_add_dr_scan(3, fields, -1); +#ifdef _DEBUG_INSTRUCTION_EXECUTION_ + DEBUG("addr: 0x%x value: %8.8x", reg_addr, value); +#endif + return ERROR_OK; } @@ -455,7 +356,7 @@ int arm966e_register_commands(struct command_context_s *cmd_ctx) int retval; command_t *arm966e_cmd; - retval = arm7_9_register_commands(cmd_ctx); + retval = arm9tdmi_register_commands(cmd_ctx); arm966e_cmd = register_command(cmd_ctx, NULL, "arm966e", NULL, COMMAND_ANY, "arm966e specific commands"); register_command(cmd_ctx, arm966e_cmd, "cp15", arm966e_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register [value]");