X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm946e.c;h=fb50d694cca6c0ff8cdb568e3e6c10883d128c86;hp=2a71f2d3501d6011190cb316acbe04c120008ea4;hb=13f6c889ab9b6e5b1c4f48fca9807fdc1fb83f42;hpb=63687807ccad246754e2fc32518bf27d1ab02d6b

diff --git a/src/target/arm946e.c b/src/target/arm946e.c
index 2a71f2d350..fb50d694cc 100644
--- a/src/target/arm946e.c
+++ b/src/target/arm946e.c
@@ -21,7 +21,7 @@
  *   You should have received a copy of the GNU General Public License     *
  *   along with this program; if not, write to the                         *
  *   Free Software Foundation, Inc.,                                       *
- *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
+ *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  ***************************************************************************/
 
 #ifdef HAVE_CONFIG_H
@@ -111,6 +111,16 @@ static int arm946e_verify_pointer(struct command_context *cmd_ctx,
 	return ERROR_OK;
 }
 
+/*
+ * Update cp15_control_reg, saved on debug_entry.
+ */
+static void arm946e_update_cp15_caches(struct target *target, uint32_t value)
+{
+	struct arm946e_common *arm946e = target_to_arm946(target);
+	arm946e->cp15_control_reg = (arm946e->cp15_control_reg & ~(CP15_CTL_DCACHE|CP15_CTL_ICACHE))
+		| (value & (CP15_CTL_DCACHE|CP15_CTL_ICACHE));
+}
+
 /*
  * REVISIT:  The "read_cp15" and "write_cp15" commands could hook up
  * to eventual mrc() and mcr() routines ... the reg_addr values being
@@ -494,7 +504,7 @@ int arm946e_write_memory(struct target *target, uint32_t address,
 	/**
 	 * Write memory
 	 */
-	retval = arm7_9_write_memory(target, address, size, count, buffer);
+	retval = arm7_9_write_memory_opt(target, address, size, count, buffer);
 	if (retval != ERROR_OK)
 		return retval;
 
@@ -541,9 +551,77 @@ int arm946e_read_memory(struct target *target, uint32_t address,
 	return ERROR_OK;
 }
 
+static int jim_arm946e_cp15(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
+{
+	/* one or two arguments, access a single register (write if second argument is given) */
+	if (argc < 2 || argc > 3) {
+		Jim_WrongNumArgs(interp, 1, argv, "addr [value]");
+		return JIM_ERR;
+	}
+
+	struct command_context *cmd_ctx = current_command_context(interp);
+	assert(cmd_ctx != NULL);
+
+	struct target *target = get_current_target(cmd_ctx);
+	if (target == NULL) {
+		LOG_ERROR("arm946e: no current target");
+		return JIM_ERR;
+	}
+
+	struct arm946e_common *arm946e = target_to_arm946(target);
+	int retval = arm946e_verify_pointer(cmd_ctx, arm946e);
+	if (retval != ERROR_OK)
+		return JIM_ERR;
 
-COMMAND_HANDLER(arm946e_handle_cp15_command)
+	if (target->state != TARGET_HALTED) {
+		command_print(cmd_ctx, "target %s must be stopped for \"cp15\" command", target_name(target));
+		return JIM_ERR;
+	}
+
+	long l;
+	uint32_t address;
+	retval = Jim_GetLong(interp, argv[1], &l);
+	address = l;
+	if (JIM_OK != retval)
+		return retval;
+
+	if (argc == 2) {
+		uint32_t value;
+		retval = arm946e_read_cp15(target, address, &value);
+		if (retval != ERROR_OK) {
+			command_print(cmd_ctx, "%s cp15 reg %" PRIi32 " access failed", target_name(target), address);
+			return JIM_ERR;
+		}
+		retval = jtag_execute_queue();
+		if (retval != ERROR_OK)
+			return JIM_ERR;
+		char buf[20];
+		sprintf(buf, "0x%08" PRIx32, value);
+		/* Return value in hex format */
+		Jim_SetResultString(interp, buf, -1);
+	} else if (argc == 3) {
+		uint32_t value;
+		retval = Jim_GetLong(interp, argv[2], &l);
+		value = l;
+		if (JIM_OK != retval)
+			return retval;
+		retval = arm946e_write_cp15(target, address, value);
+		if (retval != ERROR_OK) {
+			command_print(cmd_ctx, "%s cp15 reg %" PRIi32 " access failed", target_name(target), address);
+			return JIM_ERR;
+		}
+		if (address == CP15_CTL)
+			arm946e_update_cp15_caches(target, value);
+	}
+
+	return JIM_OK;
+}
+
+COMMAND_HANDLER(arm946e_handle_idcache)
 {
+	if (CMD_ARGC > 1)
+		return ERROR_COMMAND_SYNTAX_ERROR;
+
 	int retval;
 	struct target *target = get_current_target(CMD_CTX);
 	struct arm946e_common *arm946e = target_to_arm946(target);
@@ -554,48 +632,97 @@ COMMAND_HANDLER(arm946e_handle_cp15_command)
 
 	if (target->state != TARGET_HALTED) {
 		command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
+		return ERROR_TARGET_NOT_HALTED;
+	}
+
+	bool icache = (strcmp(CMD_NAME, "icache") == 0);
+	uint32_t csize = arm946e_cp15_get_csize(target, icache ? GET_ICACHE_SIZE : GET_DCACHE_SIZE) / 1024;
+	if (CMD_ARGC == 0) {
+		bool  bena = ((arm946e->cp15_control_reg & (icache ? CP15_CTL_ICACHE : CP15_CTL_DCACHE)) != 0)
+			  && (arm946e->cp15_control_reg & 0x1);
+		if (csize == 0)
+			command_print(CMD_CTX, "%s-cache absent", icache ? "I" : "D");
+		else
+			command_print(CMD_CTX, "%s-cache size: %" PRIu32 "K, %s",
+				      icache ? "I" : "D", csize, bena ? "enabled" : "disabled");
 		return ERROR_OK;
 	}
 
-	/* one or more argument, access a single register (write if second argument is given */
-	if (CMD_ARGC >= 1) {
-		uint32_t address;
-		COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
+	bool flush = false;
+	bool enable = false;
+	retval = command_parse_bool_arg(CMD_ARGV[0], &enable);
+	if (retval == ERROR_COMMAND_SYNTAX_ERROR) {
+		if (strcmp(CMD_ARGV[0], "flush") == 0) {
+			flush = true;
+			retval = ERROR_OK;
+		} else
+			return retval;
+	}
 
-		if (CMD_ARGC == 1) {
-			uint32_t value;
-			retval = arm946e_read_cp15(target, address, &value);
-			if (retval != ERROR_OK) {
-				command_print(CMD_CTX, "couldn't access reg %" PRIi32, address);
-				return ERROR_OK;
-			}
-			retval = jtag_execute_queue();
-			if (retval != ERROR_OK)
-				return retval;
+	/* Do not invalidate or change state, if cache is absent */
+	if (csize == 0) {
+		command_print(CMD_CTX, "%s-cache absent, '%s' operation undefined", icache ? "I" : "D", CMD_ARGV[0]);
+		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+	}
 
-			command_print(CMD_CTX, "%" PRIi32 ": %8.8" PRIx32, address, value);
-		} else if (CMD_ARGC == 2) {
-			uint32_t value;
-			COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
-			retval = arm946e_write_cp15(target, address, value);
-			if (retval != ERROR_OK) {
-				command_print(CMD_CTX, "couldn't access reg %" PRIi32, address);
-				return ERROR_OK;
-			}
-			command_print(CMD_CTX, "%" PRIi32 ": %8.8" PRIx32, address, value);
-		}
+	/* NOTE: flushing entire cache will not preserve lock-down cache regions */
+	if (icache) {
+		if ((arm946e->cp15_control_reg & CP15_CTL_ICACHE) && !enable)
+			retval = arm946e_invalidate_whole_icache(target);
+	} else {
+		if ((arm946e->cp15_control_reg & CP15_CTL_DCACHE) && !enable)
+			retval = arm946e_invalidate_whole_dcache(target);
 	}
 
+	if (retval != ERROR_OK || flush)
+		return retval;
+
+	uint32_t value;
+	retval = arm946e_read_cp15(target, CP15_CTL, &value);
+	if (retval != ERROR_OK)
+		return retval;
+
+	uint32_t vnew = value;
+	uint32_t cmask = icache ? CP15_CTL_ICACHE : CP15_CTL_DCACHE;
+	if (enable) {
+		if ((value & 0x1) == 0)
+			LOG_WARNING("arm946e: MPU must be enabled for cache to operate");
+		vnew |= cmask;
+	} else
+		vnew &= ~cmask;
+
+	if (vnew == value)
+		return ERROR_OK;
+
+	retval = arm946e_write_cp15(target, CP15_CTL, vnew);
+	if (retval != ERROR_OK)
+		return retval;
+
+	arm946e_update_cp15_caches(target, vnew);
 	return ERROR_OK;
 }
 
 static const struct command_registration arm946e_exec_command_handlers[] = {
 	{
 		.name = "cp15",
-		.handler = arm946e_handle_cp15_command,
+		.jim_handler = jim_arm946e_cp15,
 		.mode = COMMAND_EXEC,
 		.usage = "regnum [value]",
-		.help = "display/modify cp15 register",
+		.help = "read/modify cp15 register",
+	},
+	{
+		.name = "icache",
+		.handler = arm946e_handle_idcache,
+		.mode = COMMAND_EXEC,
+		.usage = "['enable'|'disable'|'flush']",
+		.help = "I-cache info and operations",
+	},
+	{
+		.name = "dcache",
+		.handler = arm946e_handle_idcache,
+		.mode = COMMAND_EXEC,
+		.usage = "['enable'|'disable'|'flush']",
+		.help = "D-cache info and operations",
 	},
 	COMMAND_REGISTRATION_DONE
 };
@@ -638,8 +765,6 @@ struct target_type arm946e_target = {
 	.read_memory = arm946e_read_memory,
 	.write_memory = arm946e_write_memory,
 
-	.bulk_write_memory = arm7_9_bulk_write_memory,
-
 	.checksum_memory = arm_checksum_memory,
 	.blank_check_memory = arm_blank_check_memory,