X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm946e.c;h=5ee31cc2f6520f31309856713e53d37089bc63a7;hp=a7a57b743fb76ac3a120f1838a6ed4c993de2c3f;hb=f19ac83152b54a204b8148815a538d868973e1e1;hpb=f1e9cef4101a6c9aba2eb65ec99404b44a5a00fc diff --git a/src/target/arm946e.c b/src/target/arm946e.c index a7a57b743f..5ee31cc2f6 100644 --- a/src/target/arm946e.c +++ b/src/target/arm946e.c @@ -19,9 +19,7 @@ * GNU General Public License for more details. * * * * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * + * along with this program. If not, see . * ***************************************************************************/ #ifdef HAVE_CONFIG_H @@ -139,7 +137,7 @@ static int arm946e_read_cp15(struct target *target, int reg_addr, uint32_t *valu retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE); if (retval != ERROR_OK) return retval; - retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE); + retval = arm_jtag_set_instr(jtag_info->tap, jtag_info->intest_instr, NULL, TAP_IDLE); if (retval != ERROR_OK) return retval; @@ -191,7 +189,7 @@ int arm946e_write_cp15(struct target *target, int reg_addr, uint32_t value) retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE); if (retval != ERROR_OK) return retval; - retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE); + retval = arm_jtag_set_instr(jtag_info->tap, jtag_info->intest_instr, NULL, TAP_IDLE); if (retval != ERROR_OK) return retval; @@ -504,7 +502,7 @@ int arm946e_write_memory(struct target *target, uint32_t address, /** * Write memory */ - retval = arm7_9_write_memory(target, address, size, count, buffer); + retval = arm7_9_write_memory_opt(target, address, size, count, buffer); if (retval != ERROR_OK) return retval; @@ -596,7 +594,7 @@ static int jim_arm946e_cp15(Jim_Interp *interp, int argc, Jim_Obj * const *argv) if (retval != ERROR_OK) return JIM_ERR; char buf[20]; - sprintf(buf, "0x%08x", value); + sprintf(buf, "0x%08" PRIx32, value); /* Return value in hex format */ Jim_SetResultString(interp, buf, -1); } else if (argc == 3) { @@ -617,6 +615,91 @@ static int jim_arm946e_cp15(Jim_Interp *interp, int argc, Jim_Obj * const *argv) return JIM_OK; } +COMMAND_HANDLER(arm946e_handle_idcache) +{ + if (CMD_ARGC > 1) + return ERROR_COMMAND_SYNTAX_ERROR; + + int retval; + struct target *target = get_current_target(CMD_CTX); + struct arm946e_common *arm946e = target_to_arm946(target); + + retval = arm946e_verify_pointer(CMD_CTX, arm946e); + if (retval != ERROR_OK) + return retval; + + if (target->state != TARGET_HALTED) { + command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME); + return ERROR_TARGET_NOT_HALTED; + } + + bool icache = (strcmp(CMD_NAME, "icache") == 0); + uint32_t csize = arm946e_cp15_get_csize(target, icache ? GET_ICACHE_SIZE : GET_DCACHE_SIZE) / 1024; + if (CMD_ARGC == 0) { + bool bena = ((arm946e->cp15_control_reg & (icache ? CP15_CTL_ICACHE : CP15_CTL_DCACHE)) != 0) + && (arm946e->cp15_control_reg & 0x1); + if (csize == 0) + command_print(CMD_CTX, "%s-cache absent", icache ? "I" : "D"); + else + command_print(CMD_CTX, "%s-cache size: %" PRIu32 "K, %s", + icache ? "I" : "D", csize, bena ? "enabled" : "disabled"); + return ERROR_OK; + } + + bool flush = false; + bool enable = false; + retval = command_parse_bool_arg(CMD_ARGV[0], &enable); + if (retval == ERROR_COMMAND_SYNTAX_ERROR) { + if (strcmp(CMD_ARGV[0], "flush") == 0) { + flush = true; + retval = ERROR_OK; + } else + return retval; + } + + /* Do not invalidate or change state, if cache is absent */ + if (csize == 0) { + command_print(CMD_CTX, "%s-cache absent, '%s' operation undefined", icache ? "I" : "D", CMD_ARGV[0]); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + } + + /* NOTE: flushing entire cache will not preserve lock-down cache regions */ + if (icache) { + if ((arm946e->cp15_control_reg & CP15_CTL_ICACHE) && !enable) + retval = arm946e_invalidate_whole_icache(target); + } else { + if ((arm946e->cp15_control_reg & CP15_CTL_DCACHE) && !enable) + retval = arm946e_invalidate_whole_dcache(target); + } + + if (retval != ERROR_OK || flush) + return retval; + + uint32_t value; + retval = arm946e_read_cp15(target, CP15_CTL, &value); + if (retval != ERROR_OK) + return retval; + + uint32_t vnew = value; + uint32_t cmask = icache ? CP15_CTL_ICACHE : CP15_CTL_DCACHE; + if (enable) { + if ((value & 0x1) == 0) + LOG_WARNING("arm946e: MPU must be enabled for cache to operate"); + vnew |= cmask; + } else + vnew &= ~cmask; + + if (vnew == value) + return ERROR_OK; + + retval = arm946e_write_cp15(target, CP15_CTL, vnew); + if (retval != ERROR_OK) + return retval; + + arm946e_update_cp15_caches(target, vnew); + return ERROR_OK; +} + static const struct command_registration arm946e_exec_command_handlers[] = { { .name = "cp15", @@ -625,6 +708,20 @@ static const struct command_registration arm946e_exec_command_handlers[] = { .usage = "regnum [value]", .help = "read/modify cp15 register", }, + { + .name = "icache", + .handler = arm946e_handle_idcache, + .mode = COMMAND_EXEC, + .usage = "['enable'|'disable'|'flush']", + .help = "I-cache info and operations", + }, + { + .name = "dcache", + .handler = arm946e_handle_idcache, + .mode = COMMAND_EXEC, + .usage = "['enable'|'disable'|'flush']", + .help = "D-cache info and operations", + }, COMMAND_REGISTRATION_DONE }; @@ -666,8 +763,6 @@ struct target_type arm946e_target = { .read_memory = arm946e_read_memory, .write_memory = arm946e_write_memory, - .bulk_write_memory = arm7_9_bulk_write_memory, - .checksum_memory = arm_checksum_memory, .blank_check_memory = arm_blank_check_memory,