X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm926ejs.c;h=f4c47748cd282e39f5c5e608053a2d27e44f48fd;hp=4ac92a249c6357173c79e5ca10572c3fb842d083;hb=57d7743639d5092770d79f7c4b12ae694c482750;hpb=19ad7f828ba36f398f52749c2f33e25a3ea78ac2

diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index 4ac92a249c..f4c47748cd 100644
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -70,28 +70,23 @@ static int arm926ejs_cp15_read(struct target *target, uint32_t op1, uint32_t op2
 	}
 	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 
-	fields[0].tap = jtag_info->tap;
 	fields[0].num_bits = 32;
 	fields[0].out_value = NULL;
 	fields[0].in_value = (uint8_t *)value;
 
-
-	fields[1].tap = jtag_info->tap;
 	fields[1].num_bits = 1;
 	fields[1].out_value = &access;
 	fields[1].in_value = &access;
 
-	fields[2].tap = jtag_info->tap;
 	fields[2].num_bits = 14;
 	fields[2].out_value = address_buf;
 	fields[2].in_value = NULL;
 
-	fields[3].tap = jtag_info->tap;
 	fields[3].num_bits = 1;
 	fields[3].out_value = &nr_w_buf;
 	fields[3].in_value = NULL;
 
-	jtag_add_dr_scan(4, fields, jtag_get_end_state());
+	jtag_add_dr_scan(jtag_info->tap, 4, fields, jtag_get_end_state());
 
 	long long then = timeval_ms();
 
@@ -100,7 +95,7 @@ static int arm926ejs_cp15_read(struct target *target, uint32_t op1, uint32_t op2
 		/* rescan with NOP, to wait for the access to complete */
 		access = 0;
 		nr_w_buf = 0;
-		jtag_add_dr_scan(4, fields, jtag_get_end_state());
+		jtag_add_dr_scan(jtag_info->tap, 4, fields, jtag_get_end_state());
 
 		jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)value);
 
@@ -164,27 +159,23 @@ static int arm926ejs_cp15_write(struct target *target, uint32_t op1, uint32_t op
 	}
 	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 
-	fields[0].tap = jtag_info->tap;
 	fields[0].num_bits = 32;
 	fields[0].out_value = value_buf;
 	fields[0].in_value = NULL;
 
-	fields[1].tap = jtag_info->tap;
 	fields[1].num_bits = 1;
 	fields[1].out_value = &access;
 	fields[1].in_value = &access;
 
-	fields[2].tap = jtag_info->tap;
 	fields[2].num_bits = 14;
 	fields[2].out_value = address_buf;
 	fields[2].in_value = NULL;
 
-	fields[3].tap = jtag_info->tap;
 	fields[3].num_bits = 1;
 	fields[3].out_value = &nr_w_buf;
 	fields[3].in_value = NULL;
 
-	jtag_add_dr_scan(4, fields, jtag_get_end_state());
+	jtag_add_dr_scan(jtag_info->tap, 4, fields, jtag_get_end_state());
 
 	long long then = timeval_ms();
 
@@ -193,7 +184,7 @@ static int arm926ejs_cp15_write(struct target *target, uint32_t op1, uint32_t op
 		/* rescan with NOP, to wait for the access to complete */
 		access = 0;
 		nr_w_buf = 0;
-		jtag_add_dr_scan(4, fields, jtag_get_end_state());
+		jtag_add_dr_scan(jtag_info->tap, 4, fields, jtag_get_end_state());
 		if ((retval = jtag_execute_queue()) != ERROR_OK)
 		{
 			return retval;
@@ -569,9 +560,9 @@ int arm926ejs_soft_reset_halt(struct target *target)
 	armv4_5->cpsr->dirty = 1;
 
 	/* start fetching from 0x0 */
-	buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
-	armv4_5->core_cache->reg_list[15].dirty = 1;
-	armv4_5->core_cache->reg_list[15].valid = 1;
+	buf_set_u32(armv4_5->pc->value, 0, 32, 0x0);
+	armv4_5->pc->dirty = 1;
+	armv4_5->pc->valid = 1;
 
 	arm926ejs_disable_mmu_caches(target, 1, 1, 1);
 	arm926ejs->armv4_5_mmu.mmu_enabled = 0;
@@ -757,7 +748,7 @@ static int arm926ejs_mmu(struct target *target, int *enabled)
 static const struct command_registration arm926ejs_exec_command_handlers[] = {
 	{
 		.name = "cache_info",
-		.handler = &arm926ejs_handle_cache_info_command,
+		.handler = arm926ejs_handle_cache_info_command,
 		.mode = COMMAND_EXEC,
 		.help = "display information about target caches",
 
@@ -815,6 +806,7 @@ struct target_type arm926ejs_target =
 	.target_create = arm926ejs_target_create,
 	.init_target = arm9tdmi_init_target,
 	.examine = arm7_9_examine,
+	.check_reset = arm7_9_check_reset,
 	.virt2phys = arm926ejs_virt2phys,
 	.mmu = arm926ejs_mmu,