X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm926ejs.c;h=ba156d485e1555c3d7ee8eaaf544002bee041e34;hp=a6dbcfe73644acab1840b8ce156be3f3ec700528;hb=0bba832713cca8e5931d5d21f37f526d0a3979cf;hpb=9f558dfac3314943e9c12b7905039dc6c17e3c11 diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c index a6dbcfe736..ba156d485e 100644 --- a/src/target/arm926ejs.c +++ b/src/target/arm926ejs.c @@ -98,7 +98,6 @@ target_type_t arm926ejs_target = .mmu = arm926ejs_mmu }; - int arm926ejs_catch_broken_irscan(u8 *captured, void *priv, scan_field_t *field) { /* The ARM926EJ-S' instruction register is 4 bits wide */ @@ -132,14 +131,14 @@ int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u3 buf_set_u32(address_buf, 0, 14, address); - jtag_add_end_state(TAP_RTI); + jtag_add_end_state(TAP_IDLE); if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK) { return retval; } arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); - fields[0].device = jtag_info->chain_pos; + fields[0].tap = jtag_info->tap; fields[0].num_bits = 32; fields[0].out_value = NULL; fields[0].out_mask = NULL; @@ -149,7 +148,7 @@ int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u3 fields[0].in_handler = NULL; fields[0].in_handler_priv = NULL; - fields[1].device = jtag_info->chain_pos; + fields[1].tap = jtag_info->tap; fields[1].num_bits = 1; fields[1].out_value = &access; fields[1].out_mask = NULL; @@ -159,7 +158,7 @@ int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u3 fields[1].in_handler = NULL; fields[1].in_handler_priv = NULL; - fields[2].device = jtag_info->chain_pos; + fields[2].tap = jtag_info->tap; fields[2].num_bits = 14; fields[2].out_value = address_buf; fields[2].out_mask = NULL; @@ -169,7 +168,7 @@ int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u3 fields[2].in_handler = NULL; fields[2].in_handler_priv = NULL; - fields[3].device = jtag_info->chain_pos; + fields[3].tap = jtag_info->tap; fields[3].num_bits = 1; fields[3].out_value = &nr_w_buf; fields[3].out_mask = NULL; @@ -179,7 +178,7 @@ int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u3 fields[3].in_handler = NULL; fields[3].in_handler_priv = NULL; - jtag_add_dr_scan(4, fields, -1); + jtag_add_dr_scan(4, fields, TAP_INVALID); fields[0].in_handler_priv = value; fields[0].in_handler = arm_jtag_buf_to_u32; @@ -190,7 +189,7 @@ int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u3 /* rescan with NOP, to wait for the access to complete */ access = 0; nr_w_buf = 0; - jtag_add_dr_scan(4, fields, -1); + jtag_add_dr_scan(4, fields, TAP_INVALID); if((retval = jtag_execute_queue()) != ERROR_OK) { return retval; @@ -222,14 +221,14 @@ int arm926ejs_cp15_write(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u buf_set_u32(address_buf, 0, 14, address); buf_set_u32(value_buf, 0, 32, value); - jtag_add_end_state(TAP_RTI); + jtag_add_end_state(TAP_IDLE); if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK) { return retval; } arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); - fields[0].device = jtag_info->chain_pos; + fields[0].tap = jtag_info->tap; fields[0].num_bits = 32; fields[0].out_value = value_buf; fields[0].out_mask = NULL; @@ -239,7 +238,7 @@ int arm926ejs_cp15_write(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u fields[0].in_handler = NULL; fields[0].in_handler_priv = NULL; - fields[1].device = jtag_info->chain_pos; + fields[1].tap = jtag_info->tap; fields[1].num_bits = 1; fields[1].out_value = &access; fields[1].out_mask = NULL; @@ -249,7 +248,7 @@ int arm926ejs_cp15_write(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u fields[1].in_handler = NULL; fields[1].in_handler_priv = NULL; - fields[2].device = jtag_info->chain_pos; + fields[2].tap = jtag_info->tap; fields[2].num_bits = 14; fields[2].out_value = address_buf; fields[2].out_mask = NULL; @@ -259,7 +258,7 @@ int arm926ejs_cp15_write(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u fields[2].in_handler = NULL; fields[2].in_handler_priv = NULL; - fields[3].device = jtag_info->chain_pos; + fields[3].tap = jtag_info->tap; fields[3].num_bits = 1; fields[3].out_value = &nr_w_buf; fields[3].out_mask = NULL; @@ -269,14 +268,14 @@ int arm926ejs_cp15_write(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u fields[3].in_handler = NULL; fields[3].in_handler_priv = NULL; - jtag_add_dr_scan(4, fields, -1); + jtag_add_dr_scan(4, fields, TAP_INVALID); /*TODO: add timeout*/ do { /* rescan with NOP, to wait for the access to complete */ access = 0; nr_w_buf = 0; - jtag_add_dr_scan(4, fields, -1); + jtag_add_dr_scan(4, fields, TAP_INVALID); if((retval = jtag_execute_queue()) != ERROR_OK) { return retval; @@ -351,9 +350,23 @@ int arm926ejs_examine_debug_reason(target_t *target) case 11: LOG_ERROR("BUG: debug re-entry from system speed access shouldn't be handled here"); break; + case 12: + /* FIX!!!! here be dragons!!! We need to fail here so + * the target will interpreted as halted but we won't + * try to talk to it right now... a resume + halt seems + * to sync things up again. Please send an email to + * openocd development mailing list if you have hardware + * to donate to look into this problem.... + */ + LOG_ERROR("mystery debug reason MOE=0xc. Try issuing a resume + halt."); + target->debug_reason = DBG_REASON_DBGRQ; + retval = ERROR_TARGET_FAILURE; + break; default: LOG_ERROR("BUG: unknown debug reason: 0x%x", debug_reason); target->debug_reason = DBG_REASON_DBGRQ; + /* if we fail here, we won't talk to the target and it will + * be reported to be in the halted state */ retval = ERROR_TARGET_FAILURE; break; } @@ -484,7 +497,6 @@ void arm926ejs_post_debug_entry(target_t *target) LOG_DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x", arm926ejs->d_fsr, arm926ejs->d_far, arm926ejs->i_fsr); - u32 cache_dbg_ctrl; /* read-modify-write CP15 cache debug control register @@ -652,7 +664,6 @@ int arm926ejs_soft_reset_halt(struct target_s *target) arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0; return target_call_event_callbacks(target, TARGET_EVENT_HALTED); - } int arm926ejs_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer) @@ -691,23 +702,21 @@ int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *ta arm9tdmi_init_target(cmd_ctx, target); return ERROR_OK; - } int arm926ejs_quit(void) { - return ERROR_OK; } -int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, int chain_pos, const char *variant) +int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, jtag_tap_t *tap) { arm9tdmi_common_t *arm9tdmi = &arm926ejs->arm9tdmi_common; arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common; /* initialize arm9tdmi specific info (including arm7_9 and armv4_5) */ - arm9tdmi_init_arch_info(target, arm9tdmi, chain_pos, variant); + arm9tdmi_init_arch_info(target, arm9tdmi, tap); arm9tdmi->arch_info = arm926ejs; arm926ejs->common_magic = ARM926EJS_COMMON_MAGIC; @@ -741,7 +750,7 @@ int arm926ejs_target_create(struct target_s *target, Jim_Interp *interp) { arm926ejs_common_t *arm926ejs = calloc(1,sizeof(arm926ejs_common_t)); - arm926ejs_init_arch_info(target, arm926ejs, target->chain_position, target->variant); + arm926ejs_init_arch_info(target, arm926ejs, target->tap); return ERROR_OK; } @@ -931,6 +940,7 @@ int arm926ejs_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu); } + static int arm926ejs_virt2phys(struct target_s *target, u32 virtual, u32 *physical) { int retval;