X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm926ejs.c;h=4dec23da79872a9926e5d8ee3e00d3d76d33a5f1;hp=51b241a597b381bd5a9e3261d271bef0f32739cf;hb=6512e5e36b067ae458cb7f6a9fdfb08d38da3583;hpb=aafb916bea1153b8d2f4706e4a62628f49741133 diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c index 51b241a597..4dec23da79 100644 --- a/src/target/arm926ejs.c +++ b/src/target/arm926ejs.c @@ -25,8 +25,9 @@ #endif #include "arm926ejs.h" -#include "time_support.h" +#include #include "target_type.h" +#include "register.h" /* @@ -55,7 +56,7 @@ static int arm926ejs_cp15_read(struct target *target, uint32_t op1, uint32_t op2 struct arm_jtag *jtag_info = &arm7_9->jtag_info; uint32_t address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm); struct scan_field fields[4]; - uint8_t address_buf[2]; + uint8_t address_buf[2] = {0, 0}; uint8_t nr_w_buf = 0; uint8_t access = 1; @@ -148,7 +149,7 @@ static int arm926ejs_cp15_write(struct target *target, uint32_t op1, uint32_t op uint32_t address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm); struct scan_field fields[4]; uint8_t value_buf[4]; - uint8_t address_buf[2]; + uint8_t address_buf[2] = {0, 0}; uint8_t nr_w_buf = 1; uint8_t access = 1; @@ -493,7 +494,7 @@ int arm926ejs_arch_state(struct target *target) }; struct arm926ejs_common *arm926ejs = target_to_arm926(target); - struct armv4_5_common_s *armv4_5; + struct arm *armv4_5; if (arm926ejs->common_magic != ARM926EJS_COMMON_MAGIC) { @@ -501,15 +502,15 @@ int arm926ejs_arch_state(struct target *target) return ERROR_TARGET_INVALID; } - armv4_5 = &arm926ejs->arm9tdmi_common.arm7_9_common.armv4_5_common; + armv4_5 = &arm926ejs->arm7_9_common.armv4_5_common; LOG_USER("target halted in %s state due to %s, current mode: %s\n" "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n" "MMU: %s, D-Cache: %s, I-Cache: %s", armv4_5_state_strings[armv4_5->core_state], Jim_Nvp_value2name_simple(nvp_target_debug_reason,target->debug_reason)->name, - armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)], - buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32), + arm_mode_name(armv4_5->core_mode), + buf_get_u32(armv4_5->cpsr->value, 0, 32), buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32), state[arm926ejs->armv4_5_mmu.mmu_enabled], state[arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled], @@ -523,7 +524,7 @@ int arm926ejs_soft_reset_halt(struct target *target) int retval = ERROR_OK; struct arm926ejs_common *arm926ejs = target_to_arm926(target); struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; + struct arm *armv4_5 = &arm7_9->armv4_5_common; struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; if ((retval = target_halt(target)) != ERROR_OK) @@ -564,18 +565,19 @@ int arm926ejs_soft_reset_halt(struct target *target) target->state = TARGET_HALTED; /* SVC, ARM state, IRQ and FIQ disabled */ - buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3); - armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1; - armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1; + uint32_t cpsr; + + cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32); + cpsr &= ~0xff; + cpsr |= 0xd3; + arm_set_cpsr(armv4_5, cpsr); + armv4_5->cpsr->dirty = 1; /* start fetching from 0x0 */ buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0); armv4_5->core_cache->reg_list[15].dirty = 1; armv4_5->core_cache->reg_list[15].valid = 1; - armv4_5->core_mode = ARMV4_5_MODE_SVC; - armv4_5->core_state = ARMV4_5_STATE_ARM; - arm926ejs_disable_mmu_caches(target, 1, 1, 1); arm926ejs->armv4_5_mmu.mmu_enabled = 0; arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0; @@ -669,12 +671,13 @@ static int arm926ejs_read_phys_memory(struct target *target, int arm926ejs_init_arch_info(struct target *target, struct arm926ejs_common *arm926ejs, struct jtag_tap *tap) { - struct arm9tdmi_common *arm9tdmi = &arm926ejs->arm9tdmi_common; - struct arm7_9_common *arm7_9 = &arm9tdmi->arm7_9_common; + struct arm7_9_common *arm7_9 = &arm926ejs->arm7_9_common; - /* initialize arm9tdmi specific info (including arm7_9 and armv4_5) - */ - arm9tdmi_init_arch_info(target, arm9tdmi, tap); + arm7_9->armv4_5_common.mrc = arm926ejs_mrc; + arm7_9->armv4_5_common.mcr = arm926ejs_mcr; + + /* initialize arm7/arm9 specific info (including armv4_5) */ + arm9tdmi_init_arch_info(target, arm7_9, tap); arm926ejs->common_magic = ARM926EJS_COMMON_MAGIC; @@ -713,78 +716,17 @@ static int arm926ejs_target_create(struct target *target, Jim_Interp *interp) return arm926ejs_init_arch_info(target, arm926ejs, target->tap); } -COMMAND_HANDLER(arm926ejs_handle_cp15_command) -{ - int retval; - struct target *target = get_current_target(cmd_ctx); - struct arm926ejs_common *arm926ejs = target_to_arm926(target); - int opcode_1; - int opcode_2; - int CRn; - int CRm; - - if ((argc < 4) || (argc > 5)) - { - command_print(cmd_ctx, "usage: arm926ejs cp15 [value]"); - return ERROR_OK; - } - - COMMAND_PARSE_NUMBER(int, args[0], opcode_1); - COMMAND_PARSE_NUMBER(int, args[1], opcode_2); - COMMAND_PARSE_NUMBER(int, args[2], CRn); - COMMAND_PARSE_NUMBER(int, args[3], CRm); - - retval = arm926ejs_verify_pointer(cmd_ctx, arm926ejs); - if (retval != ERROR_OK) - return retval; - - if (target->state != TARGET_HALTED) - { - command_print(cmd_ctx, "target must be stopped for \"%s\" command", CMD_NAME); - return ERROR_OK; - } - - if (argc == 4) - { - uint32_t value; - if ((retval = arm926ejs->read_cp15(target, opcode_1, opcode_2, CRn, CRm, &value)) != ERROR_OK) - { - command_print(cmd_ctx, "couldn't access register"); - return ERROR_OK; - } - if ((retval = jtag_execute_queue()) != ERROR_OK) - { - return retval; - } - - command_print(cmd_ctx, "%i %i %i %i: %8.8" PRIx32 "", opcode_1, opcode_2, CRn, CRm, value); - } - else - { - uint32_t value; - COMMAND_PARSE_NUMBER(u32, args[4], value); - if ((retval = arm926ejs->write_cp15(target, opcode_1, opcode_2, CRn, CRm, value)) != ERROR_OK) - { - command_print(cmd_ctx, "couldn't access register"); - return ERROR_OK; - } - command_print(cmd_ctx, "%i %i %i %i: %8.8" PRIx32 "", opcode_1, opcode_2, CRn, CRm, value); - } - - return ERROR_OK; -} - COMMAND_HANDLER(arm926ejs_handle_cache_info_command) { int retval; - struct target *target = get_current_target(cmd_ctx); + struct target *target = get_current_target(CMD_CTX); struct arm926ejs_common *arm926ejs = target_to_arm926(target); - retval = arm926ejs_verify_pointer(cmd_ctx, arm926ejs); + retval = arm926ejs_verify_pointer(CMD_CTX, arm926ejs); if (retval != ERROR_OK) return retval; - return armv4_5_handle_cache_info_command(cmd_ctx, &arm926ejs->armv4_5_mmu.armv4_5_cache); + return armv4_5_handle_cache_info_command(CMD_CTX, &arm926ejs->armv4_5_mmu.armv4_5_cache); } static int arm926ejs_virt2phys(struct target *target, uint32_t virtual, uint32_t *physical) @@ -817,29 +759,28 @@ static int arm926ejs_mmu(struct target *target, int *enabled) return ERROR_OK; } -/** Registers commands to access coprocessor, cache, and debug resources. */ -int arm926ejs_register_commands(struct command_context *cmd_ctx) -{ - int retval; - struct command *arm926ejs_cmd; - - retval = arm9tdmi_register_commands(cmd_ctx); - - arm926ejs_cmd = register_command(cmd_ctx, NULL, "arm926ejs", - NULL, COMMAND_ANY, - "arm926ejs specific commands"); - - register_command(cmd_ctx, arm926ejs_cmd, "cp15", - arm926ejs_handle_cp15_command, COMMAND_EXEC, - "display/modify cp15 register " - " [value]"); - - register_command(cmd_ctx, arm926ejs_cmd, "cache_info", - arm926ejs_handle_cache_info_command, COMMAND_EXEC, - "display information about target caches"); +static const struct command_registration arm926ejs_exec_command_handlers[] = { + { + .name = "cache_info", + .handler = &arm926ejs_handle_cache_info_command, + .mode = COMMAND_EXEC, + .help = "display information about target caches", - return retval; -} + }, + COMMAND_REGISTRATION_DONE +}; +const struct command_registration arm926ejs_command_handlers[] = { + { + .chain = arm9tdmi_command_handlers, + }, + { + .name = "arm926ejs", + .mode = COMMAND_ANY, + .help = "arm926ejs command group", + .chain = arm926ejs_exec_command_handlers, + }, + COMMAND_REGISTRATION_DONE +}; /** Holds methods for ARM926 targets. */ struct target_type arm926ejs_target = @@ -864,8 +805,9 @@ struct target_type arm926ejs_target = .read_memory = arm7_9_read_memory, .write_memory = arm926ejs_write_memory, .bulk_write_memory = arm7_9_bulk_write_memory, - .checksum_memory = arm7_9_checksum_memory, - .blank_check_memory = arm7_9_blank_check_memory, + + .checksum_memory = arm_checksum_memory, + .blank_check_memory = arm_blank_check_memory, .run_algorithm = armv4_5_run_algorithm, @@ -874,7 +816,7 @@ struct target_type arm926ejs_target = .add_watchpoint = arm7_9_add_watchpoint, .remove_watchpoint = arm7_9_remove_watchpoint, - .register_commands = arm926ejs_register_commands, + .commands = arm926ejs_command_handlers, .target_create = arm926ejs_target_create, .init_target = arm9tdmi_init_target, .examine = arm7_9_examine, @@ -883,6 +825,4 @@ struct target_type arm926ejs_target = .read_phys_memory = arm926ejs_read_phys_memory, .write_phys_memory = arm926ejs_write_phys_memory, - .mrc = arm926ejs_mrc, - .mcr = arm926ejs_mcr, };