X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm926ejs.c;h=408ede9debeb7bf82db75e9f625bbc8fed612ae9;hp=9c9628a3e1773237d5b8459c9ab6de257340f526;hb=c4992c6d863d0ead91d84d19bbfe1643d720b205;hpb=1e5daf5886999a8ff01a4957e17c1466d76e022d diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c index 9c9628a3e1..408ede9deb 100644 --- a/src/target/arm926ejs.c +++ b/src/target/arm926ejs.c @@ -2,7 +2,7 @@ * Copyright (C) 2007 by Dominic Rath * * Dominic.Rath@gmx.de * * * - * Copyright (C) 2009 by Øyvind Harboe * + * Copyright (C) 2007,2008,2009 by Øyvind Harboe * * oyvind.harboe@zylin.com * * * * This program is free software; you can redistribute it and/or modify * @@ -27,108 +27,36 @@ #include "arm926ejs.h" #include "time_support.h" #include "target_type.h" +#include "register.h" -#if 0 -#define _DEBUG_INSTRUCTION_EXECUTION_ -#endif - -/* cli handling */ -int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); -int arm926ejs_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); -int arm926ejs_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); - -int arm926ejs_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); -int arm926ejs_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); - -/* forward declarations */ -int arm926ejs_target_create(struct target_s *target, Jim_Interp *interp); -int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *target); -int arm926ejs_quit(void); - -int arm926ejs_read_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer); -int arm926ejs_write_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer); - -static int arm926ejs_virt2phys(struct target_s *target, uint32_t virtual, uint32_t *physical); -static int arm926ejs_mmu(struct target_s *target, int *enabled); - -target_type_t arm926ejs_target = -{ - .name = "arm926ejs", - - .poll = arm7_9_poll, - .arch_state = arm926ejs_arch_state, - - .target_request_data = arm7_9_target_request_data, - - .halt = arm7_9_halt, - .resume = arm7_9_resume, - .step = arm7_9_step, - - .assert_reset = arm7_9_assert_reset, - .deassert_reset = arm7_9_deassert_reset, - .soft_reset_halt = arm926ejs_soft_reset_halt, +/* + * The ARM926 is built around the ARM9EJ-S core, and most JTAG docs + * are in the ARM9EJ-S Technical Reference Manual (ARM DDI 0222B) not + * the ARM926 manual (ARM DDI 0198E). The scan chains are: + * + * 1 ... core debugging + * 2 ... EmbeddedICE + * 3 ... external boundary scan (SoC-specific, unused here) + * 6 ... ETM + * 15 ... coprocessor 15 + */ - .get_gdb_reg_list = armv4_5_get_gdb_reg_list, - - .read_memory = arm7_9_read_memory, - .write_memory = arm926ejs_write_memory, - .bulk_write_memory = arm7_9_bulk_write_memory, - .checksum_memory = arm7_9_checksum_memory, - .blank_check_memory = arm7_9_blank_check_memory, - - .run_algorithm = armv4_5_run_algorithm, - - .add_breakpoint = arm7_9_add_breakpoint, - .remove_breakpoint = arm7_9_remove_breakpoint, - .add_watchpoint = arm7_9_add_watchpoint, - .remove_watchpoint = arm7_9_remove_watchpoint, - - .register_commands = arm926ejs_register_commands, - .target_create = arm926ejs_target_create, - .init_target = arm926ejs_init_target, - .examine = arm9tdmi_examine, - .quit = arm926ejs_quit, - .virt2phys = arm926ejs_virt2phys, - .mmu = arm926ejs_mmu, - - .read_phys_memory = arm926ejs_read_phys_memory, - .write_phys_memory = arm926ejs_write_phys_memory, -}; - -int arm926ejs_catch_broken_irscan(uint8_t *captured, void *priv, scan_field_t *field) -{ - /* FIX!!!! this code should be reenabled. For now it does not check - * the queue...*/ - return 0; #if 0 - /* The ARM926EJ-S' instruction register is 4 bits wide */ - uint8_t t = *captured & 0xf; - uint8_t t2 = *field->in_check_value & 0xf; - if (t == t2) - { - return ERROR_OK; - } - else if ((t == 0x0f) || (t == 0x00)) - { - LOG_DEBUG("caught ARM926EJ-S invalid Capture-IR result after CP15 access"); - return ERROR_OK; - } - return ERROR_JTAG_QUEUE_FAILED;; +#define _DEBUG_INSTRUCTION_EXECUTION_ #endif -} #define ARM926EJS_CP15_ADDR(opcode_1, opcode_2, CRn, CRm) ((opcode_1 << 11) | (opcode_2 << 8) | (CRn << 4) | (CRm << 0)) -int arm926ejs_cp15_read(target_t *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value) +static int arm926ejs_cp15_read(struct target *target, uint32_t op1, uint32_t op2, + uint32_t CRn, uint32_t CRm, uint32_t *value) { int retval = ERROR_OK; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; uint32_t address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm); - scan_field_t fields[4]; - uint8_t address_buf[2]; + struct scan_field fields[4]; + uint8_t address_buf[2] = {0, 0}; uint8_t nr_w_buf = 0; uint8_t access = 1; @@ -197,21 +125,31 @@ int arm926ejs_cp15_read(target_t *target, uint32_t op1, uint32_t op2, uint32_t C LOG_DEBUG("addr: 0x%x value: %8.8x", address, *value); #endif - arm_jtag_set_instr(jtag_info, 0xc, &arm926ejs_catch_broken_irscan); + arm_jtag_set_instr(jtag_info, 0xc, NULL); return ERROR_OK; } -int arm926ejs_cp15_write(target_t *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value) +static int arm926ejs_mrc(struct target *target, int cpnum, uint32_t op1, + uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value) +{ + if (cpnum != 15) { + LOG_ERROR("Only cp15 is supported"); + return ERROR_FAIL; + } + return arm926ejs_cp15_read(target, op1, op2, CRn, CRm, value); +} + +static int arm926ejs_cp15_write(struct target *target, uint32_t op1, uint32_t op2, + uint32_t CRn, uint32_t CRm, uint32_t value) { int retval = ERROR_OK; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; uint32_t address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm); - scan_field_t fields[4]; + struct scan_field fields[4]; uint8_t value_buf[4]; - uint8_t address_buf[2]; + uint8_t address_buf[2] = {0, 0}; uint8_t nr_w_buf = 1; uint8_t access = 1; @@ -277,16 +215,25 @@ int arm926ejs_cp15_write(target_t *target, uint32_t op1, uint32_t op2, uint32_t LOG_DEBUG("addr: 0x%x value: %8.8x", address, value); #endif - arm_jtag_set_instr(jtag_info, 0xf, &arm926ejs_catch_broken_irscan); + arm_jtag_set_instr(jtag_info, 0xf, NULL); return ERROR_OK; } -static int arm926ejs_examine_debug_reason(target_t *target) +static int arm926ejs_mcr(struct target *target, int cpnum, uint32_t op1, + uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value) +{ + if (cpnum != 15) { + LOG_ERROR("Only cp15 is supported"); + return ERROR_FAIL; + } + return arm926ejs_cp15_write(target, op1, op2, CRn, CRm, value); +} + +static int arm926ejs_examine_debug_reason(struct target *target) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; int debug_reason; int retval; @@ -386,12 +333,9 @@ static int arm926ejs_examine_debug_reason(target_t *target) return ERROR_OK; } -uint32_t arm926ejs_get_ttb(target_t *target) +static uint32_t arm926ejs_get_ttb(struct target *target) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info; - arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info; + struct arm926ejs_common *arm926ejs = target_to_arm926(target); int retval; uint32_t ttb = 0x0; @@ -401,12 +345,10 @@ uint32_t arm926ejs_get_ttb(target_t *target) return ttb; } -void arm926ejs_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache) +static void arm926ejs_disable_mmu_caches(struct target *target, int mmu, + int d_u_cache, int i_cache) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info; - arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info; + struct arm926ejs_common *arm926ejs = target_to_arm926(target); uint32_t cp15_control; /* read cp15 control register */ @@ -452,12 +394,10 @@ void arm926ejs_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control); } -void arm926ejs_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache) +static void arm926ejs_enable_mmu_caches(struct target *target, int mmu, + int d_u_cache, int i_cache) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info; - arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info; + struct arm926ejs_common *arm926ejs = target_to_arm926(target); uint32_t cp15_control; /* read cp15 control register */ @@ -476,12 +416,9 @@ void arm926ejs_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control); } -void arm926ejs_post_debug_entry(target_t *target) +static void arm926ejs_post_debug_entry(struct target *target) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info; - arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info; + struct arm926ejs_common *arm926ejs = target_to_arm926(target); /* examine cp15 control reg */ arm926ejs->read_cp15(target, 0, 0, 1, 0, &arm926ejs->cp15_control_reg); @@ -518,12 +455,9 @@ void arm926ejs_post_debug_entry(target_t *target) arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl); } -void arm926ejs_pre_restore_context(target_t *target) +static void arm926ejs_pre_restore_context(struct target *target) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info; - arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info; + struct arm926ejs_common *arm926ejs = target_to_arm926(target); /* restore i/d fault status and address register */ arm926ejs->write_cp15(target, 0, 0, 5, 0, arm926ejs->d_fsr); @@ -539,70 +473,44 @@ void arm926ejs_pre_restore_context(target_t *target) arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl); } -int arm926ejs_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p, arm926ejs_common_t **arm926ejs_p) -{ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9; - arm9tdmi_common_t *arm9tdmi; - arm926ejs_common_t *arm926ejs; - - if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) - { - return -1; - } - - arm7_9 = armv4_5->arch_info; - if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC) - { - return -1; - } - - arm9tdmi = arm7_9->arch_info; - if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC) - { - return -1; - } +static const char arm926_not[] = "target is not an ARM926"; - arm926ejs = arm9tdmi->arch_info; - if (arm926ejs->common_magic != ARM926EJS_COMMON_MAGIC) - { - return -1; +static int arm926ejs_verify_pointer(struct command_context *cmd_ctx, + struct arm926ejs_common *arm926) +{ + if (arm926->common_magic != ARM926EJS_COMMON_MAGIC) { + command_print(cmd_ctx, arm926_not); + return ERROR_TARGET_INVALID; } - - *armv4_5_p = armv4_5; - *arm7_9_p = arm7_9; - *arm9tdmi_p = arm9tdmi; - *arm926ejs_p = arm926ejs; - return ERROR_OK; } -int arm926ejs_arch_state(struct target_s *target) +/** Logs summary of ARM926 state for a halted target. */ +int arm926ejs_arch_state(struct target *target) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info; - arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info; - - char *state[] = + static const char *state[] = { "disabled", "enabled" }; - if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) + struct arm926ejs_common *arm926ejs = target_to_arm926(target); + struct arm *armv4_5; + + if (arm926ejs->common_magic != ARM926EJS_COMMON_MAGIC) { - LOG_ERROR("BUG: called for a non-ARMv4/5 target"); - exit(-1); + LOG_ERROR("BUG: %s", arm926_not); + return ERROR_TARGET_INVALID; } - LOG_USER( - "target halted in %s state due to %s, current mode: %s\n" + armv4_5 = &arm926ejs->arm7_9_common.armv4_5_common; + + LOG_USER("target halted in %s state due to %s, current mode: %s\n" "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n" "MMU: %s, D-Cache: %s, I-Cache: %s", armv4_5_state_strings[armv4_5->core_state], Jim_Nvp_value2name_simple(nvp_target_debug_reason,target->debug_reason)->name, - armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)], - buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32), + arm_mode_name(armv4_5->core_mode), + buf_get_u32(armv4_5->cpsr->value, 0, 32), buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32), state[arm926ejs->armv4_5_mmu.mmu_enabled], state[arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled], @@ -611,14 +519,13 @@ int arm926ejs_arch_state(struct target_s *target) return ERROR_OK; } -int arm926ejs_soft_reset_halt(struct target_s *target) +int arm926ejs_soft_reset_halt(struct target *target) { int retval = ERROR_OK; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info; - arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info; - reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; + struct arm926ejs_common *arm926ejs = target_to_arm926(target); + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm *armv4_5 = &arm7_9->armv4_5_common; + struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; if ((retval = target_halt(target)) != ERROR_OK) { @@ -658,18 +565,19 @@ int arm926ejs_soft_reset_halt(struct target_s *target) target->state = TARGET_HALTED; /* SVC, ARM state, IRQ and FIQ disabled */ - buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3); - armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1; - armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1; + uint32_t cpsr; + + cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32); + cpsr &= ~0xff; + cpsr |= 0xd3; + arm_set_cpsr(armv4_5, cpsr); + armv4_5->cpsr->dirty = 1; /* start fetching from 0x0 */ buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0); armv4_5->core_cache->reg_list[15].dirty = 1; armv4_5->core_cache->reg_list[15].valid = 1; - armv4_5->core_mode = ARMV4_5_MODE_SVC; - armv4_5->core_state = ARMV4_5_STATE_ARM; - arm926ejs_disable_mmu_caches(target, 1, 1, 1); arm926ejs->armv4_5_mmu.mmu_enabled = 0; arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0; @@ -678,18 +586,17 @@ int arm926ejs_soft_reset_halt(struct target_s *target) return target_call_event_callbacks(target, TARGET_EVENT_HALTED); } -int arm926ejs_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) +/** Writes a buffer, in the specified word size, with current MMU settings. */ +int arm926ejs_write_memory(struct target *target, uint32_t address, + uint32_t size, uint32_t count, uint8_t *buffer) { int retval; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info; - arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info; + struct arm926ejs_common *arm926ejs = target_to_arm926(target); /* FIX!!!! this should be cleaned up and made much more general. The * plan is to write up and test on arm926ejs specifically and * then generalize and clean up afterwards. */ - if ((count == 1) && ((size==2) || (size==4))) + if (arm926ejs->armv4_5_mmu.mmu_enabled && (count == 1) && ((size==2) || (size==4))) { /* special case the handling of single word writes to bypass MMU * to allow implementation of breakpoints in memory marked read only @@ -741,48 +648,34 @@ int arm926ejs_write_memory(struct target_s *target, uint32_t address, uint32_t s return retval; } -int arm926ejs_write_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) +static int arm926ejs_write_phys_memory(struct target *target, + uint32_t address, uint32_t size, + uint32_t count, uint8_t *buffer) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info; - arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info; + struct arm926ejs_common *arm926ejs = target_to_arm926(target); - return armv4_5_mmu_write_physical(target, &arm926ejs->armv4_5_mmu, address, size, count, buffer); + return armv4_5_mmu_write_physical(target, &arm926ejs->armv4_5_mmu, + address, size, count, buffer); } -int arm926ejs_read_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) +static int arm926ejs_read_phys_memory(struct target *target, + uint32_t address, uint32_t size, + uint32_t count, uint8_t *buffer) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info; - arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info; + struct arm926ejs_common *arm926ejs = target_to_arm926(target); - return armv4_5_mmu_read_physical(target, &arm926ejs->armv4_5_mmu, address, size, count, buffer); + return armv4_5_mmu_read_physical(target, &arm926ejs->armv4_5_mmu, + address, size, count, buffer); } -int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *target) +int arm926ejs_init_arch_info(struct target *target, struct arm926ejs_common *arm926ejs, + struct jtag_tap *tap) { - arm9tdmi_init_target(cmd_ctx, target); + struct arm7_9_common *arm7_9 = &arm926ejs->arm7_9_common; - return ERROR_OK; -} - -int arm926ejs_quit(void) -{ - return ERROR_OK; -} + /* initialize arm7/arm9 specific info (including armv4_5) */ + arm9tdmi_init_arch_info(target, arm7_9, tap); -int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, jtag_tap_t *tap) -{ - arm9tdmi_common_t *arm9tdmi = &arm926ejs->arm9tdmi_common; - arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common; - - /* initialize arm9tdmi specific info (including arm7_9 and armv4_5) - */ - arm9tdmi_init_arch_info(target, arm9tdmi, tap); - - arm9tdmi->arch_info = arm926ejs; arm926ejs->common_magic = ARM926EJS_COMMON_MAGIC; arm7_9->post_debug_entry = arm926ejs_post_debug_entry; @@ -810,131 +703,37 @@ int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, jt return ERROR_OK; } -int arm926ejs_target_create(struct target_s *target, Jim_Interp *interp) -{ - arm926ejs_common_t *arm926ejs = calloc(1,sizeof(arm926ejs_common_t)); - - arm926ejs_init_arch_info(target, arm926ejs, target->tap); - - return ERROR_OK; -} - -int arm926ejs_register_commands(struct command_context_s *cmd_ctx) +static int arm926ejs_target_create(struct target *target, Jim_Interp *interp) { - int retval; - command_t *arm926ejs_cmd; + struct arm926ejs_common *arm926ejs = calloc(1,sizeof(struct arm926ejs_common)); + /* ARM9EJ-S core always reports 0x1 in Capture-IR */ + target->tap->ir_capture_mask = 0x0f; - retval = arm9tdmi_register_commands(cmd_ctx); - - arm926ejs_cmd = register_command(cmd_ctx, NULL, "arm926ejs", NULL, COMMAND_ANY, "arm926ejs specific commands"); - - register_command(cmd_ctx, arm926ejs_cmd, "cp15", arm926ejs_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register [value]"); - - register_command(cmd_ctx, arm926ejs_cmd, "cache_info", arm926ejs_handle_cache_info_command, COMMAND_EXEC, "display information about target caches"); - - return retval; + return arm926ejs_init_arch_info(target, arm926ejs, target->tap); } -int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +COMMAND_HANDLER(arm926ejs_handle_cache_info_command) { int retval; - target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5; - arm7_9_common_t *arm7_9; - arm9tdmi_common_t *arm9tdmi; - arm926ejs_common_t *arm926ejs; - int opcode_1; - int opcode_2; - int CRn; - int CRm; - - if ((argc < 4) || (argc > 5)) - { - command_print(cmd_ctx, "usage: arm926ejs cp15 [value]"); - return ERROR_OK; - } - - opcode_1 = strtoul(args[0], NULL, 0); - opcode_2 = strtoul(args[1], NULL, 0); - CRn = strtoul(args[2], NULL, 0); - CRm = strtoul(args[3], NULL, 0); - - if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK) - { - command_print(cmd_ctx, "current target isn't an ARM926EJ-S target"); - return ERROR_OK; - } - - if (target->state != TARGET_HALTED) - { - command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); - return ERROR_OK; - } + struct target *target = get_current_target(CMD_CTX); + struct arm926ejs_common *arm926ejs = target_to_arm926(target); - if (argc == 4) - { - uint32_t value; - if ((retval = arm926ejs->read_cp15(target, opcode_1, opcode_2, CRn, CRm, &value)) != ERROR_OK) - { - command_print(cmd_ctx, "couldn't access register"); - return ERROR_OK; - } - if ((retval = jtag_execute_queue()) != ERROR_OK) - { - return retval; - } - - command_print(cmd_ctx, "%i %i %i %i: %8.8" PRIx32 "", opcode_1, opcode_2, CRn, CRm, value); - } - else - { - uint32_t value = strtoul(args[4], NULL, 0); - if ((retval = arm926ejs->write_cp15(target, opcode_1, opcode_2, CRn, CRm, value)) != ERROR_OK) - { - command_print(cmd_ctx, "couldn't access register"); - return ERROR_OK; - } - command_print(cmd_ctx, "%i %i %i %i: %8.8" PRIx32 "", opcode_1, opcode_2, CRn, CRm, value); - } - - return ERROR_OK; -} - -int arm926ejs_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) -{ - target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5; - arm7_9_common_t *arm7_9; - arm9tdmi_common_t *arm9tdmi; - arm926ejs_common_t *arm926ejs; - - if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK) - { - command_print(cmd_ctx, "current target isn't an ARM926EJ-S target"); - return ERROR_OK; - } + retval = arm926ejs_verify_pointer(CMD_CTX, arm926ejs); + if (retval != ERROR_OK) + return retval; - return armv4_5_handle_cache_info_command(cmd_ctx, &arm926ejs->armv4_5_mmu.armv4_5_cache); + return armv4_5_handle_cache_info_command(CMD_CTX, &arm926ejs->armv4_5_mmu.armv4_5_cache); } -static int arm926ejs_virt2phys(struct target_s *target, uint32_t virtual, uint32_t *physical) +static int arm926ejs_virt2phys(struct target *target, uint32_t virtual, uint32_t *physical) { - int retval; int type; uint32_t cb; int domain; uint32_t ap; + struct arm926ejs_common *arm926ejs = target_to_arm926(target); - armv4_5_common_t *armv4_5; - arm7_9_common_t *arm7_9; - arm9tdmi_common_t *arm9tdmi; - arm926ejs_common_t *arm926ejs; - retval= arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs); - if (retval != ERROR_OK) - { - return retval; - } uint32_t ret = armv4_5_mmu_translate_va(target, &arm926ejs->armv4_5_mmu, virtual, &type, &cb, &domain, &ap); if (type == -1) { @@ -944,10 +743,9 @@ static int arm926ejs_virt2phys(struct target_s *target, uint32_t virtual, uint32 return ERROR_OK; } -static int arm926ejs_mmu(struct target_s *target, int *enabled) +static int arm926ejs_mmu(struct target *target, int *enabled) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm926ejs_common_t *arm926ejs = armv4_5->arch_info; + struct arm926ejs_common *arm926ejs = target_to_arm926(target); if (target->state != TARGET_HALTED) { @@ -957,3 +755,73 @@ static int arm926ejs_mmu(struct target_s *target, int *enabled) *enabled = arm926ejs->armv4_5_mmu.mmu_enabled; return ERROR_OK; } + +static const struct command_registration arm926ejs_exec_command_handlers[] = { + { + .name = "cache_info", + .handler = &arm926ejs_handle_cache_info_command, + .mode = COMMAND_EXEC, + .help = "display information about target caches", + + }, + COMMAND_REGISTRATION_DONE +}; +const struct command_registration arm926ejs_command_handlers[] = { + { + .chain = arm9tdmi_command_handlers, + }, + { + .name = "arm926ejs", + .mode = COMMAND_ANY, + .help = "arm926ejs command group", + .chain = arm926ejs_exec_command_handlers, + }, + COMMAND_REGISTRATION_DONE +}; + +/** Holds methods for ARM926 targets. */ +struct target_type arm926ejs_target = +{ + .name = "arm926ejs", + + .poll = arm7_9_poll, + .arch_state = arm926ejs_arch_state, + + .target_request_data = arm7_9_target_request_data, + + .halt = arm7_9_halt, + .resume = arm7_9_resume, + .step = arm7_9_step, + + .assert_reset = arm7_9_assert_reset, + .deassert_reset = arm7_9_deassert_reset, + .soft_reset_halt = arm926ejs_soft_reset_halt, + + .get_gdb_reg_list = armv4_5_get_gdb_reg_list, + + .read_memory = arm7_9_read_memory, + .write_memory = arm926ejs_write_memory, + .bulk_write_memory = arm7_9_bulk_write_memory, + + .checksum_memory = arm_checksum_memory, + .blank_check_memory = arm_blank_check_memory, + + .run_algorithm = armv4_5_run_algorithm, + + .add_breakpoint = arm7_9_add_breakpoint, + .remove_breakpoint = arm7_9_remove_breakpoint, + .add_watchpoint = arm7_9_add_watchpoint, + .remove_watchpoint = arm7_9_remove_watchpoint, + + .commands = arm926ejs_command_handlers, + .target_create = arm926ejs_target_create, + .init_target = arm9tdmi_init_target, + .examine = arm7_9_examine, + .virt2phys = arm926ejs_virt2phys, + .mmu = arm926ejs_mmu, + + .read_phys_memory = arm926ejs_read_phys_memory, + .write_phys_memory = arm926ejs_write_phys_memory, + .mrc = arm926ejs_mrc, + .mcr = arm926ejs_mcr, +};