X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm920t.c;h=e6c2eed82d48928055667124e8abf97e9484b1c0;hp=58e92c35ec24490d4e88b2505960a21515a35100;hb=66ee303456910f684244a20a0ac2e958d40b78cb;hpb=7bf1a86e473a12882bf6f71cb4d0d416394b69d4 diff --git a/src/target/arm920t.c b/src/target/arm920t.c index 58e92c35ec..e6c2eed82d 100644 --- a/src/target/arm920t.c +++ b/src/target/arm920t.c @@ -212,10 +212,11 @@ static int arm920t_execute_cp15(struct target *target, uint32_t cp15_opcode, static int arm920t_read_cp15_interpreted(struct target *target, uint32_t cp15_opcode, uint32_t address, uint32_t *value) { - struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); + struct arm *armv4_5 = target_to_armv4_5(target); uint32_t* regs_p[1]; uint32_t regs[2]; uint32_t cp15c15 = 0x0; + struct reg *r = armv4_5->core_cache->reg_list; /* load address into R1 */ regs[1] = address; @@ -244,11 +245,11 @@ static int arm920t_read_cp15_interpreted(struct target *target, LOG_DEBUG("cp15_opcode: %8.8x, address: %8.8x, value: %8.8x", cp15_opcode, address, *value); #endif - if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) + if (!is_arm_mode(armv4_5->core_mode)) return ERROR_FAIL; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = 1; + r[0].dirty = 1; + r[1].dirty = 1; return ERROR_OK; } @@ -258,8 +259,9 @@ int arm920t_write_cp15_interpreted(struct target *target, uint32_t cp15_opcode, uint32_t value, uint32_t address) { uint32_t cp15c15 = 0x0; - struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); + struct arm *armv4_5 = target_to_armv4_5(target); uint32_t regs[2]; + struct reg *r = armv4_5->core_cache->reg_list; /* load value, address into R0, R1 */ regs[0] = value; @@ -284,11 +286,11 @@ int arm920t_write_cp15_interpreted(struct target *target, LOG_DEBUG("cp15_opcode: %8.8x, value: %8.8x, address: %8.8x", cp15_opcode, value, address); #endif - if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) + if (!is_arm_mode(armv4_5->core_mode)) return ERROR_FAIL; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = 1; + r[0].dirty = 1; + r[1].dirty = 1; return ERROR_OK; } @@ -436,7 +438,7 @@ int arm920t_arch_state(struct target *target) }; struct arm920t_common *arm920t = target_to_arm920(target); - struct armv4_5_common_s *armv4_5; + struct arm *armv4_5; if (arm920t->common_magic != ARM920T_COMMON_MAGIC) { @@ -451,8 +453,8 @@ int arm920t_arch_state(struct target *target) "MMU: %s, D-Cache: %s, I-Cache: %s", armv4_5_state_strings[armv4_5->core_state], Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name, - armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)], - buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32), + arm_mode_name(armv4_5->core_mode), + buf_get_u32(armv4_5->cpsr->value, 0, 32), buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32), state[arm920t->armv4_5_mmu.mmu_enabled], state[arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled], @@ -555,7 +557,7 @@ int arm920t_soft_reset_halt(struct target *target) int retval = ERROR_OK; struct arm920t_common *arm920t = target_to_arm920(target); struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; + struct arm *armv4_5 = &arm7_9->armv4_5_common; struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; if ((retval = target_halt(target)) != ERROR_OK) @@ -596,18 +598,19 @@ int arm920t_soft_reset_halt(struct target *target) target->state = TARGET_HALTED; /* SVC, ARM state, IRQ and FIQ disabled */ - buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3); - armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1; - armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1; + uint32_t cpsr; + + cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32); + cpsr &= ~0xff; + cpsr |= 0xd3; + arm_set_cpsr(armv4_5, cpsr); + armv4_5->cpsr->dirty = 1; /* start fetching from 0x0 */ buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0); armv4_5->core_cache->reg_list[15].dirty = 1; armv4_5->core_cache->reg_list[15].valid = 1; - armv4_5->core_mode = ARMV4_5_MODE_SVC; - armv4_5->core_state = ARMV4_5_STATE_ARM; - arm920t_disable_mmu_caches(target, 1, 1, 1); arm920t->armv4_5_mmu.mmu_enabled = 0; arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0; @@ -664,10 +667,10 @@ static int arm920t_target_create(struct target *target, Jim_Interp *interp) COMMAND_HANDLER(arm920t_handle_read_cache_command) { int retval = ERROR_OK; - struct target *target = get_current_target(cmd_ctx); + struct target *target = get_current_target(CMD_CTX); struct arm920t_common *arm920t = target_to_arm920(target); struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; + struct arm *armv4_5 = &arm7_9->armv4_5_common; uint32_t cp15c15; uint32_t cp15_ctrl, cp15_ctrl_saved; uint32_t regs[16]; @@ -677,18 +680,19 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command) FILE *output; struct arm920t_cache_line d_cache[8][64], i_cache[8][64]; int segment, index; + struct reg *r; - retval = arm920t_verify_pointer(cmd_ctx, arm920t); + retval = arm920t_verify_pointer(CMD_CTX, arm920t); if (retval != ERROR_OK) return retval; if (CMD_ARGC != 1) { - command_print(cmd_ctx, "usage: arm920t read_cache "); + command_print(CMD_CTX, "usage: arm920t read_cache "); return ERROR_OK; } - if ((output = fopen(args[0], "w")) == NULL) + if ((output = fopen(CMD_ARGV[0], "w")) == NULL) { LOG_DEBUG("error opening cache content file"); return ERROR_OK; @@ -885,24 +889,29 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command) /* restore CP15 MMU and Cache settings */ arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved); - command_print(cmd_ctx, "cache content successfully output to %s", args[0]); + command_print(CMD_CTX, "cache content successfully output to %s", CMD_ARGV[0]); fclose(output); - if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) + if (!is_arm_mode(armv4_5->core_mode)) return ERROR_FAIL; - /* mark registers dirty. */ - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).valid; + /* force writeback of the valid data */ + r = armv4_5->core_cache->reg_list; + r[0].dirty = r[0].valid; + r[1].dirty = r[1].valid; + r[2].dirty = r[2].valid; + r[3].dirty = r[3].valid; + r[4].dirty = r[4].valid; + r[5].dirty = r[5].valid; + r[6].dirty = r[6].valid; + r[7].dirty = r[7].valid; + + r = arm_reg_current(armv4_5, 8); + r->dirty = r->valid; + + r = arm_reg_current(armv4_5, 9); + r->dirty = r->valid; return ERROR_OK; } @@ -910,10 +919,10 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command) COMMAND_HANDLER(arm920t_handle_read_mmu_command) { int retval = ERROR_OK; - struct target *target = get_current_target(cmd_ctx); + struct target *target = get_current_target(CMD_CTX); struct arm920t_common *arm920t = target_to_arm920(target); struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; + struct arm *armv4_5 = &arm7_9->armv4_5_common; uint32_t cp15c15; uint32_t cp15_ctrl, cp15_ctrl_saved; uint32_t regs[16]; @@ -923,18 +932,19 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command) uint32_t Dlockdown, Ilockdown; struct arm920t_tlb_entry d_tlb[64], i_tlb[64]; int victim; + struct reg *r; - retval = arm920t_verify_pointer(cmd_ctx, arm920t); + retval = arm920t_verify_pointer(CMD_CTX, arm920t); if (retval != ERROR_OK) return retval; if (CMD_ARGC != 1) { - command_print(cmd_ctx, "usage: arm920t read_mmu "); + command_print(CMD_CTX, "usage: arm920t read_mmu "); return ERROR_OK; } - if ((output = fopen(args[0], "w")) == NULL) + if ((output = fopen(CMD_ARGV[0], "w")) == NULL) { LOG_DEBUG("error opening mmu content file"); return ERROR_OK; @@ -1168,24 +1178,29 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command) fprintf(output, "%i: 0x%8.8" PRIx32 " 0x%8.8" PRIx32 " 0x%8.8" PRIx32 " %s\n", i, i_tlb[i].cam, i_tlb[i].ram1, i_tlb[i].ram2, (i_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)"); } - command_print(cmd_ctx, "mmu content successfully output to %s", args[0]); + command_print(CMD_CTX, "mmu content successfully output to %s", CMD_ARGV[0]); fclose(output); - if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) + if (!is_arm_mode(armv4_5->core_mode)) return ERROR_FAIL; - /* mark registers dirty */ - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).valid; + /* force writeback of the valid data */ + r = armv4_5->core_cache->reg_list; + r[0].dirty = r[0].valid; + r[1].dirty = r[1].valid; + r[2].dirty = r[2].valid; + r[3].dirty = r[3].valid; + r[4].dirty = r[4].valid; + r[5].dirty = r[5].valid; + r[6].dirty = r[6].valid; + r[7].dirty = r[7].valid; + + r = arm_reg_current(armv4_5, 8); + r->dirty = r->valid; + + r = arm_reg_current(armv4_5, 9); + r->dirty = r->valid; return ERROR_OK; } @@ -1193,16 +1208,16 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command) COMMAND_HANDLER(arm920t_handle_cp15_command) { int retval; - struct target *target = get_current_target(cmd_ctx); + struct target *target = get_current_target(CMD_CTX); struct arm920t_common *arm920t = target_to_arm920(target); - retval = arm920t_verify_pointer(cmd_ctx, arm920t); + retval = arm920t_verify_pointer(CMD_CTX, arm920t); if (retval != ERROR_OK) return retval; if (target->state != TARGET_HALTED) { - command_print(cmd_ctx, "target must be stopped for \"%s\" command", CMD_NAME); + command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME); return ERROR_OK; } @@ -1210,14 +1225,14 @@ COMMAND_HANDLER(arm920t_handle_cp15_command) if (CMD_ARGC >= 1) { int address; - COMMAND_PARSE_NUMBER(int, args[0], address); + COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], address); if (CMD_ARGC == 1) { uint32_t value; if ((retval = arm920t_read_cp15_physical(target, address, &value)) != ERROR_OK) { - command_print(cmd_ctx, "couldn't access reg %i", address); + command_print(CMD_CTX, "couldn't access reg %i", address); return ERROR_OK; } if ((retval = jtag_execute_queue()) != ERROR_OK) @@ -1225,18 +1240,18 @@ COMMAND_HANDLER(arm920t_handle_cp15_command) return retval; } - command_print(cmd_ctx, "%i: %8.8" PRIx32 "", address, value); + command_print(CMD_CTX, "%i: %8.8" PRIx32 "", address, value); } else if (CMD_ARGC == 2) { uint32_t value; - COMMAND_PARSE_NUMBER(u32, args[1], value); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value); if ((retval = arm920t_write_cp15_physical(target, address, value)) != ERROR_OK) { - command_print(cmd_ctx, "couldn't access reg %i", address); + command_print(CMD_CTX, "couldn't access reg %i", address); return ERROR_OK; } - command_print(cmd_ctx, "%i: %8.8" PRIx32 "", address, value); + command_print(CMD_CTX, "%i: %8.8" PRIx32 "", address, value); } } @@ -1246,17 +1261,17 @@ COMMAND_HANDLER(arm920t_handle_cp15_command) COMMAND_HANDLER(arm920t_handle_cp15i_command) { int retval; - struct target *target = get_current_target(cmd_ctx); + struct target *target = get_current_target(CMD_CTX); struct arm920t_common *arm920t = target_to_arm920(target); - retval = arm920t_verify_pointer(cmd_ctx, arm920t); + retval = arm920t_verify_pointer(CMD_CTX, arm920t); if (retval != ERROR_OK) return retval; if (target->state != TARGET_HALTED) { - command_print(cmd_ctx, "target must be stopped for \"%s\" command", CMD_NAME); + command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME); return ERROR_OK; } @@ -1264,47 +1279,47 @@ COMMAND_HANDLER(arm920t_handle_cp15i_command) if (CMD_ARGC >= 1) { uint32_t opcode; - COMMAND_PARSE_NUMBER(u32, args[0], opcode); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], opcode); if (CMD_ARGC == 1) { uint32_t value; if ((retval = arm920t_read_cp15_interpreted(target, opcode, 0x0, &value)) != ERROR_OK) { - command_print(cmd_ctx, "couldn't execute %8.8" PRIx32 "", opcode); + command_print(CMD_CTX, "couldn't execute %8.8" PRIx32 "", opcode); return ERROR_OK; } - command_print(cmd_ctx, "%8.8" PRIx32 ": %8.8" PRIx32 "", opcode, value); + command_print(CMD_CTX, "%8.8" PRIx32 ": %8.8" PRIx32 "", opcode, value); } else if (CMD_ARGC == 2) { uint32_t value; - COMMAND_PARSE_NUMBER(u32, args[1], value); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value); if ((retval = arm920t_write_cp15_interpreted(target, opcode, value, 0)) != ERROR_OK) { - command_print(cmd_ctx, "couldn't execute %8.8" PRIx32 "", opcode); + command_print(CMD_CTX, "couldn't execute %8.8" PRIx32 "", opcode); return ERROR_OK; } - command_print(cmd_ctx, "%8.8" PRIx32 ": %8.8" PRIx32 "", opcode, value); + command_print(CMD_CTX, "%8.8" PRIx32 ": %8.8" PRIx32 "", opcode, value); } else if (CMD_ARGC == 3) { uint32_t value; - COMMAND_PARSE_NUMBER(u32, args[1], value); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value); uint32_t address; - COMMAND_PARSE_NUMBER(u32, args[2], address); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], address); if ((retval = arm920t_write_cp15_interpreted(target, opcode, value, address)) != ERROR_OK) { - command_print(cmd_ctx, "couldn't execute %8.8" PRIx32 "", opcode); + command_print(CMD_CTX, "couldn't execute %8.8" PRIx32 "", opcode); return ERROR_OK; } - command_print(cmd_ctx, "%8.8" PRIx32 ": %8.8" PRIx32 " %8.8" PRIx32 "", opcode, value, address); + command_print(CMD_CTX, "%8.8" PRIx32 ": %8.8" PRIx32 " %8.8" PRIx32 "", opcode, value, address); } } else { - command_print(cmd_ctx, "usage: arm920t cp15i [value] [address]"); + command_print(CMD_CTX, "usage: arm920t cp15i [value] [address]"); } return ERROR_OK; @@ -1313,14 +1328,14 @@ COMMAND_HANDLER(arm920t_handle_cp15i_command) COMMAND_HANDLER(arm920t_handle_cache_info_command) { int retval; - struct target *target = get_current_target(cmd_ctx); + struct target *target = get_current_target(CMD_CTX); struct arm920t_common *arm920t = target_to_arm920(target); - retval = arm920t_verify_pointer(cmd_ctx, arm920t); + retval = arm920t_verify_pointer(CMD_CTX, arm920t); if (retval != ERROR_OK) return retval; - return armv4_5_handle_cache_info_command(cmd_ctx, &arm920t->armv4_5_mmu.armv4_5_cache); + return armv4_5_handle_cache_info_command(CMD_CTX, &arm920t->armv4_5_mmu.armv4_5_cache); } @@ -1346,37 +1361,53 @@ static int arm920t_mcr(struct target *target, int cpnum, uint32_t op1, uint32_t return arm920t_write_cp15_interpreted(target, mrc_opcode(cpnum, op1, op2, CRn, CRm), 0, value); } -/** Registers commands to access coprocessor, cache, and MMU resources. */ -int arm920t_register_commands(struct command_context *cmd_ctx) -{ - int retval; - struct command *arm920t_cmd; - - retval = arm9tdmi_register_commands(cmd_ctx); - - arm920t_cmd = register_command(cmd_ctx, NULL, "arm920t", - NULL, COMMAND_ANY, - "arm920t specific commands"); - - register_command(cmd_ctx, arm920t_cmd, "cp15", - arm920t_handle_cp15_command, COMMAND_EXEC, - "display/modify cp15 register [value]"); - register_command(cmd_ctx, arm920t_cmd, "cp15i", - arm920t_handle_cp15i_command, COMMAND_EXEC, - "display/modify cp15 (interpreted access) " - " [value] [address]"); - register_command(cmd_ctx, arm920t_cmd, "cache_info", - arm920t_handle_cache_info_command, COMMAND_EXEC, - "display information about target caches"); - register_command(cmd_ctx, arm920t_cmd, "read_cache", - arm920t_handle_read_cache_command, COMMAND_EXEC, - "display I/D cache content"); - register_command(cmd_ctx, arm920t_cmd, "read_mmu", - arm920t_handle_read_mmu_command, COMMAND_EXEC, - "display I/D mmu content"); - - return retval; -} +static const struct command_registration arm920t_exec_command_handlers[] = { + { + .name = "cp15", + .handler = &arm920t_handle_cp15_command, + .mode = COMMAND_EXEC, + .help = "display/modify cp15 register", + .usage = " [value]", + }, + { + .name = "cp15i", + .handler = &arm920t_handle_cp15i_command, + .mode = COMMAND_EXEC, + .help = "display/modify cp15 (interpreted access)", + .usage = " [value] [address]", + }, + { + .name = "cache_info", + .handler = &arm920t_handle_cache_info_command, + .mode = COMMAND_EXEC, + .help = "display information about target caches", + }, + { + .name = "read_cache", + .handler = &arm920t_handle_read_cache_command, + .mode = COMMAND_EXEC, + .help = "display I/D cache content", + }, + { + .name = "read_mmu", + .handler = &arm920t_handle_read_mmu_command, + .mode = COMMAND_EXEC, + .help = "display I/D mmu content", + }, + COMMAND_REGISTRATION_DONE +}; +const struct command_registration arm920t_command_handlers[] = { + { + .chain = arm9tdmi_command_handlers, + }, + { + .name = "arm920t", + .mode = COMMAND_ANY, + .help = "arm920t command group", + .chain = arm920t_exec_command_handlers, + }, + COMMAND_REGISTRATION_DONE +}; /** Holds methods for ARM920 targets. */ struct target_type arm920t_target = @@ -1417,7 +1448,7 @@ struct target_type arm920t_target = .add_watchpoint = arm7_9_add_watchpoint, .remove_watchpoint = arm7_9_remove_watchpoint, - .register_commands = arm920t_register_commands, + .commands = arm920t_command_handlers, .target_create = arm920t_target_create, .init_target = arm9tdmi_init_target, .examine = arm7_9_examine,