X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm920t.c;h=c14f6ef801c9dd02f03acadc248c1118292fe3af;hp=3d178161481b5096dc6c252331649815e76a861a;hb=f370d70670bd5e30befe6fbfbc8d472e760f032b;hpb=d47e1b8f362379d8a2307f49e2b42115a3f40524

diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index 3d17816148..c14f6ef801 100644
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -48,7 +48,7 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd
 /* forward declarations */
 int arm920t_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
 int arm920t_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
-int arm920t_quit();
+int arm920t_quit(void);
 int arm920t_arch_state(struct target_s *target);
 int arm920t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
 int arm920t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
@@ -72,7 +72,6 @@ target_type_t arm920t_target =
 	.assert_reset = arm7_9_assert_reset,
 	.deassert_reset = arm7_9_deassert_reset,
 	.soft_reset_halt = arm920t_soft_reset_halt,
-	.prepare_reset_halt = arm7_9_prepare_reset_halt,
 	
 	.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
 
@@ -80,6 +79,7 @@ target_type_t arm920t_target =
 	.write_memory = arm920t_write_memory,
 	.bulk_write_memory = arm7_9_bulk_write_memory,
 	.checksum_memory = arm7_9_checksum_memory,
+	.blank_check_memory = arm7_9_blank_check_memory,
 	
 	.run_algorithm = armv4_5_run_algorithm,
 
@@ -91,6 +91,7 @@ target_type_t arm920t_target =
 	.register_commands = arm920t_register_commands,
 	.target_command = arm920t_target_command,
 	.init_target = arm920t_init_target,
+	.examine = arm9tdmi_examine,
 	.quit = arm920t_quit
 };
 
@@ -335,6 +336,9 @@ int arm920t_read_cp15_interpreted(target_t *target, u32 cp15_opcode, u32 address
 	LOG_DEBUG("cp15_opcode: %8.8x, address: %8.8x, value: %8.8x", cp15_opcode, address, *value);
 #endif
 
+	if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
+		return ERROR_FAIL;
+
 	ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
 	ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = 1;
 
@@ -370,6 +374,9 @@ int arm920t_write_cp15_interpreted(target_t *target, u32 cp15_opcode, u32 value,
 	LOG_DEBUG("cp15_opcode: %8.8x, value: %8.8x, address: %8.8x", cp15_opcode, value, address);
 #endif
 
+	if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
+		return ERROR_FAIL;
+	
 	ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
 	ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = 1;
 	
@@ -622,13 +629,27 @@ int arm920t_soft_reset_halt(struct target_s *target)
 	arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 	arm920t_common_t *arm920t = arm9tdmi->arch_info;
 	reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
+	int i;
 	
-	target->type->halt(target);
+	target_halt(target);
 	
-	while (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
+	for (i=0; i<10; i++)
 	{
-		embeddedice_read_reg(dbg_stat);
-		jtag_execute_queue();
+		if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
+		{
+			embeddedice_read_reg(dbg_stat);
+			jtag_execute_queue();
+		} else
+		{
+			break;
+		}
+		/* do not eat all CPU, time out after 1 se*/
+		usleep(100*1000);
+	}
+	if (i==10)
+	{
+		LOG_ERROR("Failed to halt CPU after 1 sec");
+		return ERROR_TARGET_TIMEOUT;
 	}
 	
 	target->state = TARGET_HALTED;
@@ -664,7 +685,7 @@ int arm920t_init_target(struct command_context_s *cmd_ctx, struct target_s *targ
 	
 }
 
-int arm920t_quit()
+int arm920t_quit(void)
 {
 	
 	return ERROR_OK;
@@ -986,6 +1007,9 @@ int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *c
 	
 	fclose(output);
 	
+	if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
+		return ERROR_FAIL;
+
 	/* mark registers dirty. */
 	ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid;
 	ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).valid;
@@ -1247,6 +1271,9 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd
 	
 	fclose(output);
 	
+	if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
+		return ERROR_FAIL;
+
 	/* mark registers dirty */
 	ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid;
 	ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).valid;