X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm920t.c;h=76e54f72afe9d24dd1f8f061826e08abdb5d8a4e;hp=2dff6b9428599c9590f96127287224a150ff5a3a;hb=a28eaa85f73759bb189a46308642502c9fa5aa4b;hpb=c4a2fdbc39dd31170e61e7fe0be332826825acbd diff --git a/src/target/arm920t.c b/src/target/arm920t.c index 2dff6b9428..76e54f72af 100644 --- a/src/target/arm920t.c +++ b/src/target/arm920t.c @@ -24,6 +24,7 @@ #include "arm920t.h" #include "jtag.h" #include "log.h" +#include "time_support.h" #include #include @@ -46,9 +47,9 @@ int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *c int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); /* forward declarations */ -int arm920t_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target); +int arm920t_target_create(struct target_s *target, Jim_Interp *interp); int arm920t_init_target(struct command_context_s *cmd_ctx, struct target_s *target); -int arm920t_quit(); +int arm920t_quit(void); int arm920t_arch_state(struct target_s *target); int arm920t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer); int arm920t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer); @@ -79,6 +80,7 @@ target_type_t arm920t_target = .write_memory = arm920t_write_memory, .bulk_write_memory = arm7_9_bulk_write_memory, .checksum_memory = arm7_9_checksum_memory, + .blank_check_memory = arm7_9_blank_check_memory, .run_algorithm = armv4_5_run_algorithm, @@ -88,7 +90,7 @@ target_type_t arm920t_target = .remove_watchpoint = arm7_9_remove_watchpoint, .register_commands = arm920t_register_commands, - .target_command = arm920t_target_command, + .target_create = arm920t_target_create, .init_target = arm920t_init_target, .examine = arm9tdmi_examine, .quit = arm920t_quit @@ -108,7 +110,7 @@ int arm920t_read_cp15_physical(target_t *target, int reg_addr, u32 *value) arm_jtag_scann(jtag_info, 0xf); arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); - fields[0].device = jtag_info->chain_pos; + fields[0].tap = jtag_info->tap; fields[0].num_bits = 1; fields[0].out_value = &access_type_buf; fields[0].out_mask = NULL; @@ -118,7 +120,7 @@ int arm920t_read_cp15_physical(target_t *target, int reg_addr, u32 *value) fields[0].in_handler = NULL; fields[0].in_handler_priv = NULL; - fields[1].device = jtag_info->chain_pos; + fields[1].tap = jtag_info->tap; fields[1].num_bits = 32; fields[1].out_value = NULL; fields[1].out_mask = NULL; @@ -128,7 +130,7 @@ int arm920t_read_cp15_physical(target_t *target, int reg_addr, u32 *value) fields[1].in_handler = NULL; fields[1].in_handler_priv = NULL; - fields[2].device = jtag_info->chain_pos; + fields[2].tap = jtag_info->tap; fields[2].num_bits = 6; fields[2].out_value = ®_addr_buf; fields[2].out_mask = NULL; @@ -138,7 +140,7 @@ int arm920t_read_cp15_physical(target_t *target, int reg_addr, u32 *value) fields[2].in_handler = NULL; fields[2].in_handler_priv = NULL; - fields[3].device = jtag_info->chain_pos; + fields[3].tap = jtag_info->tap; fields[3].num_bits = 1; fields[3].out_value = &nr_w_buf; fields[3].out_mask = NULL; @@ -180,7 +182,7 @@ int arm920t_write_cp15_physical(target_t *target, int reg_addr, u32 value) arm_jtag_scann(jtag_info, 0xf); arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); - fields[0].device = jtag_info->chain_pos; + fields[0].tap = jtag_info->tap; fields[0].num_bits = 1; fields[0].out_value = &access_type_buf; fields[0].out_mask = NULL; @@ -190,7 +192,7 @@ int arm920t_write_cp15_physical(target_t *target, int reg_addr, u32 value) fields[0].in_handler = NULL; fields[0].in_handler_priv = NULL; - fields[1].device = jtag_info->chain_pos; + fields[1].tap = jtag_info->tap; fields[1].num_bits = 32; fields[1].out_value = value_buf; fields[1].out_mask = NULL; @@ -200,7 +202,7 @@ int arm920t_write_cp15_physical(target_t *target, int reg_addr, u32 value) fields[1].in_handler = NULL; fields[1].in_handler_priv = NULL; - fields[2].device = jtag_info->chain_pos; + fields[2].tap = jtag_info->tap; fields[2].num_bits = 6; fields[2].out_value = ®_addr_buf; fields[2].out_mask = NULL; @@ -210,7 +212,7 @@ int arm920t_write_cp15_physical(target_t *target, int reg_addr, u32 value) fields[2].in_handler = NULL; fields[2].in_handler_priv = NULL; - fields[3].device = jtag_info->chain_pos; + fields[3].tap = jtag_info->tap; fields[3].num_bits = 1; fields[3].out_value = &nr_w_buf; fields[3].out_mask = NULL; @@ -231,6 +233,7 @@ int arm920t_write_cp15_physical(target_t *target, int reg_addr, u32 value) int arm920t_execute_cp15(target_t *target, u32 cp15_opcode, u32 arm_opcode) { + int retval; armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info; @@ -246,7 +249,7 @@ int arm920t_execute_cp15(target_t *target, u32 cp15_opcode, u32 arm_opcode) buf_set_u32(cp15_opcode_buf, 0, 32, cp15_opcode); - fields[0].device = jtag_info->chain_pos; + fields[0].tap = jtag_info->tap; fields[0].num_bits = 1; fields[0].out_value = &access_type_buf; fields[0].out_mask = NULL; @@ -256,7 +259,7 @@ int arm920t_execute_cp15(target_t *target, u32 cp15_opcode, u32 arm_opcode) fields[0].in_handler = NULL; fields[0].in_handler_priv = NULL; - fields[1].device = jtag_info->chain_pos; + fields[1].tap = jtag_info->tap; fields[1].num_bits = 32; fields[1].out_value = cp15_opcode_buf; fields[1].out_mask = NULL; @@ -266,7 +269,7 @@ int arm920t_execute_cp15(target_t *target, u32 cp15_opcode, u32 arm_opcode) fields[1].in_handler = NULL; fields[1].in_handler_priv = NULL; - fields[2].device = jtag_info->chain_pos; + fields[2].tap = jtag_info->tap; fields[2].num_bits = 6; fields[2].out_value = ®_addr_buf; fields[2].out_mask = NULL; @@ -276,7 +279,7 @@ int arm920t_execute_cp15(target_t *target, u32 cp15_opcode, u32 arm_opcode) fields[2].in_handler = NULL; fields[2].in_handler_priv = NULL; - fields[3].device = jtag_info->chain_pos; + fields[3].tap = jtag_info->tap; fields[3].num_bits = 1; fields[3].out_value = &nr_w_buf; fields[3].out_mask = NULL; @@ -290,12 +293,14 @@ int arm920t_execute_cp15(target_t *target, u32 cp15_opcode, u32 arm_opcode) arm9tdmi_clock_out(jtag_info, arm_opcode, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1); - arm7_9_execute_sys_speed(target); + retval = arm7_9_execute_sys_speed(target); + if (retval != ERROR_OK) + return retval; - if (jtag_execute_queue() != ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) { LOG_ERROR("failed executing JTAG queue, exiting"); - exit(-1); + return retval; } return ERROR_OK; @@ -335,6 +340,9 @@ int arm920t_read_cp15_interpreted(target_t *target, u32 cp15_opcode, u32 address LOG_DEBUG("cp15_opcode: %8.8x, address: %8.8x, value: %8.8x", cp15_opcode, address, *value); #endif + if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) + return ERROR_FAIL; + ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1; ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = 1; @@ -370,6 +378,9 @@ int arm920t_write_cp15_interpreted(target_t *target, u32 cp15_opcode, u32 value, LOG_DEBUG("cp15_opcode: %8.8x, value: %8.8x, address: %8.8x", cp15_opcode, value, address); #endif + if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) + return ERROR_FAIL; + ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1; ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = 1; @@ -558,7 +569,7 @@ int arm920t_arch_state(struct target_s *target) "cpsr: 0x%8.8x pc: 0x%8.8x\n" "MMU: %s, D-Cache: %s, I-Cache: %s", armv4_5_state_strings[armv4_5->core_state], - target_debug_reason_strings[target->debug_reason], + Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name, armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)], buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32), buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32), @@ -617,29 +628,43 @@ int arm920t_write_memory(struct target_s *target, u32 address, u32 size, u32 cou int arm920t_soft_reset_halt(struct target_s *target) { + int retval = ERROR_OK; armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info; arm920t_common_t *arm920t = arm9tdmi->arch_info; reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; - int i; - target_halt(target); + if((retval = target_halt(target)) != ERROR_OK) + { + return retval; + } - for (i=0; i<10; i++) + long long then=timeval_ms(); + int timeout; + while (!(timeout=((timeval_ms()-then)>1000))) { if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0) { embeddedice_read_reg(dbg_stat); - jtag_execute_queue(); + if((retval = jtag_execute_queue()) != ERROR_OK) + { + return retval; + } } else { break; } - /* do not eat all CPU, time out after 1 se*/ - usleep(100*1000); + if (debug_level>=3) + { + /* do not eat all CPU, time out after 1 se*/ + alive_sleep(100); + } else + { + keep_alive(); + } } - if (i==10) + if (timeout) { LOG_ERROR("Failed to halt CPU after 1 sec"); return ERROR_TARGET_TIMEOUT; @@ -665,7 +690,10 @@ int arm920t_soft_reset_halt(struct target_s *target) arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0; arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0; - target_call_event_callbacks(target, TARGET_EVENT_HALTED); + if((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK) + { + return retval; + } return ERROR_OK; } @@ -678,20 +706,20 @@ int arm920t_init_target(struct command_context_s *cmd_ctx, struct target_s *targ } -int arm920t_quit() +int arm920t_quit(void) { return ERROR_OK; } -int arm920t_init_arch_info(target_t *target, arm920t_common_t *arm920t, int chain_pos, char *variant) +int arm920t_init_arch_info(target_t *target, arm920t_common_t *arm920t, jtag_tap_t *tap, const char *variant) { arm9tdmi_common_t *arm9tdmi = &arm920t->arm9tdmi_common; arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common; /* initialize arm9tdmi specific info (including arm7_9 and armv4_5) */ - arm9tdmi_init_arch_info(target, arm9tdmi, chain_pos, variant); + arm9tdmi_init_arch_info(target, arm9tdmi, tap, variant); arm9tdmi->arch_info = arm920t; arm920t->common_magic = ARM920T_COMMON_MAGIC; @@ -720,27 +748,11 @@ int arm920t_init_arch_info(target_t *target, arm920t_common_t *arm920t, int chai return ERROR_OK; } -int arm920t_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target) +int arm920t_target_create(struct target_s *target, Jim_Interp *interp) { - int chain_pos; - char *variant = NULL; - arm920t_common_t *arm920t = malloc(sizeof(arm920t_common_t)); - memset(arm920t, 0, sizeof(*arm920t)); - - if (argc < 4) - { - LOG_ERROR("'target arm920t' requires at least one additional argument"); - exit(-1); - } - - chain_pos = strtoul(args[3], NULL, 0); - - if (argc >= 5) - variant = args[4]; - - LOG_DEBUG("chain_pos: %i, variant: %s", chain_pos, variant); + arm920t_common_t *arm920t = calloc(1,sizeof(arm920t_common_t)); - arm920t_init_arch_info(target, arm920t, chain_pos, variant); + arm920t_init_arch_info(target, arm920t, target->tap, target->variant); return ERROR_OK; } @@ -771,11 +783,12 @@ int arm920t_register_commands(struct command_context_s *cmd_ctx) register_command(cmd_ctx, arm920t_cmd, "read_cache", arm920t_handle_read_cache_command, COMMAND_EXEC, "display I/D cache content"); register_command(cmd_ctx, arm920t_cmd, "read_mmu", arm920t_handle_read_mmu_command, COMMAND_EXEC, "display I/D mmu content"); - return ERROR_OK; + return retval; } int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) { + int retval = ERROR_OK; target_t *target = get_current_target(cmd_ctx); armv4_5_common_t *armv4_5; arm7_9_common_t *arm7_9; @@ -817,7 +830,10 @@ int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *c /* disable MMU and Caches */ arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl); - jtag_execute_queue(); + if((retval = jtag_execute_queue()) != ERROR_OK) + { + return retval; + } cp15_ctrl_saved = cp15_ctrl; cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED | ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED); arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl); @@ -877,7 +893,10 @@ int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *c /* read D RAM and CAM content */ arm9tdmi_read_core_regs(target, 0x3fe, regs_p); - jtag_execute_queue(); + if((retval = jtag_execute_queue()) != ERROR_OK) + { + return retval; + } d_cache[segment][index].cam = regs[9]; @@ -960,7 +979,10 @@ int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *c /* read I RAM and CAM content */ arm9tdmi_read_core_regs(target, 0x3fe, regs_p); - jtag_execute_queue(); + if((retval = jtag_execute_queue()) != ERROR_OK) + { + return retval; + } i_cache[segment][index].cam = regs[9]; @@ -1000,6 +1022,9 @@ int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *c fclose(output); + if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) + return ERROR_FAIL; + /* mark registers dirty. */ ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid; ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).valid; @@ -1017,6 +1042,7 @@ int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *c int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) { + int retval = ERROR_OK; target_t *target = get_current_target(cmd_ctx); armv4_5_common_t *armv4_5; arm7_9_common_t *arm7_9; @@ -1058,14 +1084,20 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd /* disable MMU and Caches */ arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl); - jtag_execute_queue(); + if((retval = jtag_execute_queue()) != ERROR_OK) + { + return retval; + } cp15_ctrl_saved = cp15_ctrl; cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED | ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED); arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl); /* read CP15 test state register */ arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15); - jtag_execute_queue(); + if((retval = jtag_execute_queue()) != ERROR_OK) + { + return retval; + } /* prepare reading D TLB content * */ @@ -1083,7 +1115,10 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd /* read D TLB lockdown stored to r1 */ arm9tdmi_read_core_regs(target, 0x2, regs_p); - jtag_execute_queue(); + if((retval = jtag_execute_queue()) != ERROR_OK) + { + return retval; + } Dlockdown = regs[1]; for (victim = 0; victim < 64; victim += 8) @@ -1109,7 +1144,10 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd /* read D TLB CAM content stored to r2-r9 */ arm9tdmi_read_core_regs(target, 0x3fc, regs_p); - jtag_execute_queue(); + if((retval = jtag_execute_queue()) != ERROR_OK) + { + return retval; + } for (i = 0; i < 8; i++) d_tlb[victim + i].cam = regs[i + 2]; @@ -1141,7 +1179,10 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd /* read D TLB RAM content stored to r2 and r3 */ arm9tdmi_read_core_regs(target, 0xc, regs_p); - jtag_execute_queue(); + if((retval = jtag_execute_queue()) != ERROR_OK) + { + return retval; + } d_tlb[victim].ram1 = regs[2]; d_tlb[victim].ram2 = regs[3]; @@ -1170,7 +1211,10 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd /* read I TLB lockdown stored to r1 */ arm9tdmi_read_core_regs(target, 0x2, regs_p); - jtag_execute_queue(); + if((retval = jtag_execute_queue()) != ERROR_OK) + { + return retval; + } Ilockdown = regs[1]; for (victim = 0; victim < 64; victim += 8) @@ -1196,7 +1240,10 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd /* read I TLB CAM content stored to r2-r9 */ arm9tdmi_read_core_regs(target, 0x3fc, regs_p); - jtag_execute_queue(); + if((retval = jtag_execute_queue()) != ERROR_OK) + { + return retval; + } for (i = 0; i < 8; i++) i_tlb[i + victim].cam = regs[i + 2]; @@ -1228,7 +1275,10 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd /* read I TLB RAM content stored to r2 and r3 */ arm9tdmi_read_core_regs(target, 0xc, regs_p); - jtag_execute_queue(); + if((retval = jtag_execute_queue()) != ERROR_OK) + { + return retval; + } i_tlb[victim].ram1 = regs[2]; i_tlb[victim].ram2 = regs[3]; @@ -1261,6 +1311,9 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd fclose(output); + if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) + return ERROR_FAIL; + /* mark registers dirty */ ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid; ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).valid; @@ -1312,7 +1365,10 @@ int arm920t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, ch command_print(cmd_ctx, "couldn't access reg %i", address); return ERROR_OK; } - jtag_execute_queue(); + if((retval = jtag_execute_queue()) != ERROR_OK) + { + return retval; + } command_print(cmd_ctx, "%i: %8.8x", address, value); }