X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm7tdmi.c;h=e1e91c3a04b71fd6cccf4a12e61367b062087652;hp=c94d974b8da274fc9fa97e97993c71ebb3d9a8d6;hb=a851b91c4c1db76dd1e26a7d1a99124ad456b020;hpb=f90d8fa45f2d4c9d4b7990f198b232ee55cbb4e1 diff --git a/src/target/arm7tdmi.c b/src/target/arm7tdmi.c index c94d974b8d..e1e91c3a04 100644 --- a/src/target/arm7tdmi.c +++ b/src/target/arm7tdmi.c @@ -5,7 +5,7 @@ * Copyright (C) 2008 by Spencer Oliver * * spen@spen-soft.co.uk * * * - * Copyright (C) 2007,2008 Øyvind Harboe * + * Copyright (C) 2007,2008 Øyvind Harboe * * oyvind.harboe@zylin.com * * * * This program is free software; you can redistribute it and/or modify * @@ -19,115 +19,67 @@ * GNU General Public License for more details. * * * * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * + * along with this program. If not, see . * ***************************************************************************/ + #ifdef HAVE_CONFIG_H #include "config.h" #endif #include "arm7tdmi.h" #include "target_type.h" - +#include "register.h" +#include "arm_opcodes.h" +#include "arm_semihosting.h" + +/* + * For information about ARM7TDMI, see ARM DDI 0210C (r4p1) + * or ARM DDI 0029G (r3). "Debug In Depth", Appendix B, + * covers JTAG support. + */ #if 0 #define _DEBUG_INSTRUCTION_EXECUTION_ #endif -/* forward declarations */ - -int arm7tdmi_target_create(struct target_s *target,Jim_Interp *interp); -int arm7tdmi_quit(void); - -/* target function declarations */ -int arm7tdmi_poll(struct target_s *target); -int arm7tdmi_halt(target_t *target); - -target_type_t arm7tdmi_target = -{ - .name = "arm7tdmi", - - .poll = arm7_9_poll, - .arch_state = armv4_5_arch_state, - - .target_request_data = arm7_9_target_request_data, - - .halt = arm7_9_halt, - .resume = arm7_9_resume, - .step = arm7_9_step, - - .assert_reset = arm7_9_assert_reset, - .deassert_reset = arm7_9_deassert_reset, - .soft_reset_halt = arm7_9_soft_reset_halt, - - .get_gdb_reg_list = armv4_5_get_gdb_reg_list, - - .read_memory = arm7_9_read_memory, - .write_memory = arm7_9_write_memory, - .bulk_write_memory = arm7_9_bulk_write_memory, - .checksum_memory = arm7_9_checksum_memory, - .blank_check_memory = arm7_9_blank_check_memory, - - .run_algorithm = armv4_5_run_algorithm, - - .add_breakpoint = arm7_9_add_breakpoint, - .remove_breakpoint = arm7_9_remove_breakpoint, - .add_watchpoint = arm7_9_add_watchpoint, - .remove_watchpoint = arm7_9_remove_watchpoint, - - .register_commands = arm7tdmi_register_commands, - .target_create = arm7tdmi_target_create, - .init_target = arm7tdmi_init_target, - .examine = arm7tdmi_examine, - .quit = arm7tdmi_quit -}; - -int arm7tdmi_examine_debug_reason(target_t *target) +static int arm7tdmi_examine_debug_reason(struct target *target) { int retval = ERROR_OK; - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); /* only check the debug reason if we don't know it already */ if ((target->debug_reason != DBG_REASON_DBGRQ) - && (target->debug_reason != DBG_REASON_SINGLESTEP)) - { - scan_field_t fields[2]; + && (target->debug_reason != DBG_REASON_SINGLESTEP)) { + struct scan_field fields[2]; uint8_t databus[4]; uint8_t breakpoint; - jtag_set_end_state(TAP_DRPAUSE); - - fields[0].tap = arm7_9->jtag_info.tap; fields[0].num_bits = 1; fields[0].out_value = NULL; fields[0].in_value = &breakpoint; - fields[1].tap = arm7_9->jtag_info.tap; fields[1].num_bits = 32; fields[1].out_value = NULL; fields[1].in_value = databus; - if ((retval = arm_jtag_scann(&arm7_9->jtag_info, 0x1)) != ERROR_OK) - { + retval = arm_jtag_scann(&arm7_9->jtag_info, 0x1, TAP_DRPAUSE); + if (retval != ERROR_OK) + return retval; + retval = arm_jtag_set_instr(arm7_9->jtag_info.tap, arm7_9->jtag_info.intest_instr, NULL, TAP_DRPAUSE); + if (retval != ERROR_OK) return retval; - } - arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL); - jtag_add_dr_scan(2, fields, jtag_set_end_state(TAP_DRPAUSE)); - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + jtag_add_dr_scan(arm7_9->jtag_info.tap, 2, fields, TAP_DRPAUSE); + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; - } fields[0].in_value = NULL; fields[0].out_value = &breakpoint; fields[1].in_value = NULL; fields[1].out_value = databus; - jtag_add_dr_scan(2, fields, jtag_set_end_state(TAP_DRPAUSE)); + jtag_add_dr_scan(arm7_9->jtag_info.tap, 2, fields, TAP_DRPAUSE); if (breakpoint & 1) target->debug_reason = DBG_REASON_WATCHPOINT; @@ -138,179 +90,157 @@ int arm7tdmi_examine_debug_reason(target_t *target) return ERROR_OK; } -static int arm7tdmi_num_bits[]={1, 32}; -static __inline int arm7tdmi_clock_out_inner(arm_jtag_t *jtag_info, uint32_t out, int breakpoint) +static const int arm7tdmi_num_bits[] = {1, 32}; + +static inline int arm7tdmi_clock_out_inner(struct arm_jtag *jtag_info, uint32_t out, int breakpoint) { - uint32_t values[2]={breakpoint, flip_u32(out, 32)}; + uint8_t bp = breakpoint ? 1 : 0; + uint8_t out_value[4]; + buf_set_u32(out_value, 0, 32, flip_u32(out, 32)); + + struct scan_field fields[2] = { + { .num_bits = arm7tdmi_num_bits[0], .out_value = &bp }, + { .num_bits = arm7tdmi_num_bits[1], .out_value = out_value }, + }; - jtag_add_dr_out(jtag_info->tap, + jtag_add_dr_scan(jtag_info->tap, 2, - arm7tdmi_num_bits, - values, - jtag_get_end_state()); + fields, + TAP_DRPAUSE); - jtag_add_runtest(0, jtag_get_end_state()); + jtag_add_runtest(0, TAP_DRPAUSE); return ERROR_OK; } -/* put an instruction in the ARM7TDMI pipeline or write the data bus, and optionally read data */ -static __inline int arm7tdmi_clock_out(arm_jtag_t *jtag_info, uint32_t out, uint32_t *deprecated, int breakpoint) +/* put an instruction in the ARM7TDMI pipeline or write the data bus, + * and optionally read data + * + * FIXME remove the unused "deprecated" parameter + */ +static inline int arm7tdmi_clock_out(struct arm_jtag *jtag_info, + uint32_t out, uint32_t *deprecated, int breakpoint) { - jtag_set_end_state(TAP_DRPAUSE); - arm_jtag_scann(jtag_info, 0x1); - arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); + int retval; + retval = arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE); + if (retval != ERROR_OK) + return retval; + retval = arm_jtag_set_instr(jtag_info->tap, jtag_info->intest_instr, NULL, TAP_DRPAUSE); + if (retval != ERROR_OK) + return retval; return arm7tdmi_clock_out_inner(jtag_info, out, breakpoint); } /* clock the target, reading the databus */ -int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, uint32_t *in) +static int arm7tdmi_clock_data_in(struct arm_jtag *jtag_info, uint32_t *in) { int retval = ERROR_OK; - scan_field_t fields[2]; + struct scan_field fields[2]; - jtag_set_end_state(TAP_DRPAUSE); - if ((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK) - { + retval = arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE); + if (retval != ERROR_OK) + return retval; + retval = arm_jtag_set_instr(jtag_info->tap, jtag_info->intest_instr, NULL, TAP_DRPAUSE); + if (retval != ERROR_OK) return retval; - } - arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); - fields[0].tap = jtag_info->tap; fields[0].num_bits = 1; fields[0].out_value = NULL; fields[0].in_value = NULL; - fields[1].tap = jtag_info->tap; fields[1].num_bits = 32; fields[1].out_value = NULL; fields[1].in_value = (uint8_t *)in; - jtag_add_dr_scan(2, fields, jtag_get_end_state()); + jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_DRPAUSE); jtag_add_callback(arm7flip32, (jtag_callback_data_t)in); - jtag_add_runtest(0, jtag_get_end_state()); + jtag_add_runtest(0, TAP_DRPAUSE); #ifdef _DEBUG_INSTRUCTION_EXECUTION_ -{ - if ((retval = jtag_execute_queue()) != ERROR_OK) - { - return retval; - } + retval = jtag_execute_queue(); + if (retval != ERROR_OK) + return retval; - if (in) - { - LOG_DEBUG("in: 0x%8.8x", *in); - } - else - { - LOG_ERROR("BUG: called with in == NULL"); - } -} + if (in) + LOG_DEBUG("in: 0x%8.8x", *in); + else + LOG_ERROR("BUG: called with in == NULL"); #endif return ERROR_OK; } -void arm_endianness(uint8_t *tmp, void *in, int size, int be, int flip) -{ - uint32_t readback = le_to_h_u32(tmp); - if (flip) - readback = flip_u32(readback, 32); - switch (size) - { - case 4: - if (be) - { - h_u32_to_be(((uint8_t*)in), readback); - } else - { - h_u32_to_le(((uint8_t*)in), readback); - } - break; - case 2: - if (be) - { - h_u16_to_be(((uint8_t*)in), readback & 0xffff); - } else - { - h_u16_to_le(((uint8_t*)in), readback & 0xffff); - } - break; - case 1: - *((uint8_t *)in)= readback & 0xff; - break; - } -} - -static int arm7endianness(jtag_callback_data_t arg, jtag_callback_data_t size, jtag_callback_data_t be, jtag_callback_data_t captured) -{ - uint8_t *in = (uint8_t *)arg; - arm_endianness((uint8_t *)captured, in, (int)size, (int)be, 1); - return ERROR_OK; -} - /* clock the target, and read the databus * the *in pointer points to a buffer where elements of 'size' bytes * are stored in big (be == 1) or little (be == 0) endianness */ -int arm7tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, int be) +static int arm7tdmi_clock_data_in_endianness(struct arm_jtag *jtag_info, + void *in, int size, int be) { int retval = ERROR_OK; - scan_field_t fields[2]; + struct scan_field fields[3]; - jtag_set_end_state(TAP_DRPAUSE); - if ((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK) - { + retval = arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE); + if (retval != ERROR_OK) + return retval; + retval = arm_jtag_set_instr(jtag_info->tap, jtag_info->intest_instr, NULL, TAP_DRPAUSE); + if (retval != ERROR_OK) return retval; - } - arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); - fields[0].tap = jtag_info->tap; fields[0].num_bits = 1; fields[0].out_value = NULL; fields[0].in_value = NULL; - fields[1].tap = jtag_info->tap; - fields[1].num_bits = 32; - fields[1].out_value = NULL; - jtag_alloc_in_value32(&fields[1]); + if (size == 4) { + fields[1].num_bits = 32; + fields[1].out_value = NULL; + fields[1].in_value = in; + } else { + /* Discard irrelevant bits of the scan, making sure we don't write more + * than size bytes to in */ + fields[1].num_bits = 32 - size * 8; + fields[1].out_value = NULL; + fields[1].in_value = NULL; - jtag_add_dr_scan(2, fields, jtag_get_end_state()); + fields[2].num_bits = size * 8; + fields[2].out_value = NULL; + fields[2].in_value = in; + } + + jtag_add_dr_scan(jtag_info->tap, size == 4 ? 2 : 3, fields, TAP_DRPAUSE); - jtag_add_callback4(arm7endianness, (jtag_callback_data_t)in, (jtag_callback_data_t)size, (jtag_callback_data_t)be, (jtag_callback_data_t)fields[1].in_value); + jtag_add_callback4(arm7_9_endianness_callback, + (jtag_callback_data_t)in, + (jtag_callback_data_t)size, + (jtag_callback_data_t)be, + (jtag_callback_data_t)1); - jtag_add_runtest(0, jtag_get_end_state()); + jtag_add_runtest(0, TAP_DRPAUSE); #ifdef _DEBUG_INSTRUCTION_EXECUTION_ { - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; - } if (in) - { - LOG_DEBUG("in: 0x%8.8x", *(uint32_t*)in); - } + LOG_DEBUG("in: 0x%8.8x", *(uint32_t *)in); else - { LOG_ERROR("BUG: called with in == NULL"); - } } #endif return ERROR_OK; } -void arm7tdmi_change_to_arm(target_t *target, uint32_t *r0, uint32_t *pc) +static void arm7tdmi_change_to_arm(struct target *target, + uint32_t *r0, uint32_t *pc) { - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* save r0 before using it and put system in ARM state * to allow common handling of ARM and THUMB debugging */ @@ -355,20 +285,18 @@ void arm7tdmi_change_to_arm(target_t *target, uint32_t *r0, uint32_t *pc) *pc -= 0xa; } - /* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s? * * The solution is to arrange for a large out/in scan in this loop and * and convert data afterwards. */ -void arm7tdmi_read_core_regs(target_t *target, uint32_t mask, uint32_t* core_regs[16]) +static void arm7tdmi_read_core_regs(struct target *target, + uint32_t mask, uint32_t *core_regs[16]) { int i; - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* STMIA r0-15, [r0] at debug speed * register values will start to appear on 4th DCLK @@ -380,21 +308,19 @@ void arm7tdmi_read_core_regs(target_t *target, uint32_t mask, uint32_t* core_reg /* fetch NOP, STM in EXECUTE stage (1st cycle) */ arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0); - for (i = 0; i <= 15; i++) - { + for (i = 0; i <= 15; i++) { if (mask & (1 << i)) /* nothing fetched, STM still in EXECUTE (1 + i cycle) */ arm7tdmi_clock_data_in(jtag_info, core_regs[i]); } } -void arm7tdmi_read_core_regs_target_buffer(target_t *target, uint32_t mask, void* buffer, int size) +static void arm7tdmi_read_core_regs_target_buffer(struct target *target, + uint32_t mask, void *buffer, int size) { int i; - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0; uint32_t *buf_u32 = buffer; uint16_t *buf_u16 = buffer; @@ -410,13 +336,10 @@ void arm7tdmi_read_core_regs_target_buffer(target_t *target, uint32_t mask, void /* fetch NOP, STM in EXECUTE stage (1st cycle) */ arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0); - for (i = 0; i <= 15; i++) - { + for (i = 0; i <= 15; i++) { /* nothing fetched, STM still in EXECUTE (1 + i cycle), read databus */ - if (mask & (1 << i)) - { - switch (size) - { + if (mask & (1 << i)) { + switch (size) { case 4: arm7tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be); break; @@ -431,12 +354,10 @@ void arm7tdmi_read_core_regs_target_buffer(target_t *target, uint32_t mask, void } } -void arm7tdmi_read_xpsr(target_t *target, uint32_t *xpsr, int spsr) +static void arm7tdmi_read_xpsr(struct target *target, uint32_t *xpsr, int spsr) { - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* MRS r0, cpsr */ arm7tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), NULL, 0); @@ -451,12 +372,10 @@ void arm7tdmi_read_xpsr(target_t *target, uint32_t *xpsr, int spsr) arm7tdmi_clock_data_in(jtag_info, xpsr); } -void arm7tdmi_write_xpsr(target_t *target, uint32_t xpsr, int spsr) +static void arm7tdmi_write_xpsr(struct target *target, uint32_t xpsr, int spsr) { - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr); @@ -482,12 +401,11 @@ void arm7tdmi_write_xpsr(target_t *target, uint32_t xpsr, int spsr) arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0); } -void arm7tdmi_write_xpsr_im8(target_t *target, uint8_t xpsr_im, int rot, int spsr) +static void arm7tdmi_write_xpsr_im8(struct target *target, + uint8_t xpsr_im, int rot, int spsr) { - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr); @@ -501,13 +419,12 @@ void arm7tdmi_write_xpsr_im8(target_t *target, uint8_t xpsr_im, int rot, int sps arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0); } -void arm7tdmi_write_core_regs(target_t *target, uint32_t mask, uint32_t core_regs[16]) +static void arm7tdmi_write_core_regs(struct target *target, + uint32_t mask, uint32_t core_regs[16]) { int i; - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* LDMIA r0-15, [r0] at debug speed * register values will start to appear on 4th DCLK @@ -519,8 +436,7 @@ void arm7tdmi_write_core_regs(target_t *target, uint32_t mask, uint32_t core_reg /* fetch NOP, LDM in EXECUTE stage (1st cycle) */ arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0); - for (i = 0; i <= 15; i++) - { + for (i = 0; i <= 15; i++) { if (mask & (1 << i)) /* nothing fetched, LDM still in EXECUTE (1 + i cycle) */ arm7tdmi_clock_out_inner(jtag_info, core_regs[i], 0); @@ -528,12 +444,10 @@ void arm7tdmi_write_core_regs(target_t *target, uint32_t mask, uint32_t core_reg arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0); } -void arm7tdmi_load_word_regs(target_t *target, uint32_t mask) +static void arm7tdmi_load_word_regs(struct target *target, uint32_t mask) { - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* put system-speed load-multiple into the pipeline */ arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0); @@ -541,12 +455,10 @@ void arm7tdmi_load_word_regs(target_t *target, uint32_t mask) arm7tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 1), NULL, 0); } -void arm7tdmi_load_hword_reg(target_t *target, int num) +static void arm7tdmi_load_hword_reg(struct target *target, int num) { - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* put system-speed load half-word into the pipeline */ arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0); @@ -554,12 +466,10 @@ void arm7tdmi_load_hword_reg(target_t *target, int num) arm7tdmi_clock_out(jtag_info, ARMV4_5_LDRH_IP(num, 0), NULL, 0); } -void arm7tdmi_load_byte_reg(target_t *target, int num) +static void arm7tdmi_load_byte_reg(struct target *target, int num) { - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* put system-speed load byte into the pipeline */ arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0); @@ -567,12 +477,10 @@ void arm7tdmi_load_byte_reg(target_t *target, int num) arm7tdmi_clock_out(jtag_info, ARMV4_5_LDRB_IP(num, 0), NULL, 0); } -void arm7tdmi_store_word_regs(target_t *target, uint32_t mask) +static void arm7tdmi_store_word_regs(struct target *target, uint32_t mask) { - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* put system-speed store-multiple into the pipeline */ arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0); @@ -580,12 +488,10 @@ void arm7tdmi_store_word_regs(target_t *target, uint32_t mask) arm7tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask, 0, 1), NULL, 0); } -void arm7tdmi_store_hword_reg(target_t *target, int num) +static void arm7tdmi_store_hword_reg(struct target *target, int num) { - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* put system-speed store half-word into the pipeline */ arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0); @@ -593,12 +499,10 @@ void arm7tdmi_store_hword_reg(target_t *target, int num) arm7tdmi_clock_out(jtag_info, ARMV4_5_STRH_IP(num, 0), NULL, 0); } -void arm7tdmi_store_byte_reg(target_t *target, int num) +static void arm7tdmi_store_byte_reg(struct target *target, int num) { - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* put system-speed store byte into the pipeline */ arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0); @@ -606,12 +510,10 @@ void arm7tdmi_store_byte_reg(target_t *target, int num) arm7tdmi_clock_out(jtag_info, ARMV4_5_STRB_IP(num, 0), NULL, 0); } -void arm7tdmi_write_pc(target_t *target, uint32_t pc) +static void arm7tdmi_write_pc(struct target *target, uint32_t pc) { - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* LDMIA r0-15, [r0] at debug speed * register values will start to appear on 4th DCLK @@ -633,26 +535,23 @@ void arm7tdmi_write_pc(target_t *target, uint32_t pc) arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0); } -void arm7tdmi_branch_resume(target_t *target) +static void arm7tdmi_branch_resume(struct target *target) { - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1); arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_B(0xfffffa, 0), 0); } -void arm7tdmi_branch_resume_thumb(target_t *target) +static void arm7tdmi_branch_resume_thumb(struct target *target) { - LOG_DEBUG("-"); + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm *arm = &arm7_9->arm; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; + struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; - reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; + LOG_DEBUG("-"); /* LDMIA r0, [r0] at debug speed * register values will start to appear on 4th DCLK @@ -664,7 +563,8 @@ void arm7tdmi_branch_resume_thumb(target_t *target) /* fetch NOP, LDM in EXECUTE stage (1st cycle) */ arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0); /* nothing fetched, LDM in EXECUTE stage (2nd cycle) */ - arm7tdmi_clock_out(jtag_info, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32) | 1, NULL, 0); + arm7tdmi_clock_out(jtag_info, + buf_get_u32(arm->pc->value, 0, 32) | 1, NULL, 0); /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */ arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0); @@ -692,7 +592,7 @@ void arm7tdmi_branch_resume_thumb(target_t *target) /* fetch NOP, LDR in Execute */ arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0); /* nothing fetched, LDR in EXECUTE stage (2nd cycle) */ - arm7tdmi_clock_out(jtag_info, buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32), NULL, 0); + arm7tdmi_clock_out(jtag_info, buf_get_u32(arm->core_cache->reg_list[0].value, 0, 32), NULL, 0); /* nothing fetched, LDR in EXECUTE stage (3rd cycle) */ arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0); @@ -705,72 +605,24 @@ void arm7tdmi_branch_resume_thumb(target_t *target) arm7tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7f8), NULL, 0); } -void arm7tdmi_build_reg_cache(target_t *target) +static void arm7tdmi_build_reg_cache(struct target *target) { - reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache); - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; + struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache); + struct arm *arm = target_to_arm(target); - (*cache_p) = armv4_5_build_reg_cache(target, armv4_5); - armv4_5->core_cache = (*cache_p); + (*cache_p) = arm_build_reg_cache(target, arm); } -int arm7tdmi_examine(struct target_s *target) -{ - int retval; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - if (!target_was_examined(target)) - { - /* get pointers to arch-specific information */ - reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache); - reg_cache_t *t = embeddedice_build_reg_cache(target, arm7_9); - if (t == NULL) - return ERROR_FAIL; - - (*cache_p) = t; - arm7_9->eice_cache = (*cache_p); - - if (arm7_9->etm_ctx) - { - arm_jtag_t *jtag_info = &arm7_9->jtag_info; - (*cache_p)->next = etm_build_reg_cache(target, jtag_info, arm7_9->etm_ctx); - arm7_9->etm_ctx->reg_cache = (*cache_p)->next; - } - target_set_examined(target); - } - if ((retval = embeddedice_setup(target)) != ERROR_OK) - return retval; - if ((retval = arm7_9_setup(target)) != ERROR_OK) - return retval; - if (arm7_9->etm_ctx) - { - if ((retval = etm_setup(target)) != ERROR_OK) - return retval; - } - return ERROR_OK; -} - -int arm7tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target) +int arm7tdmi_init_target(struct command_context *cmd_ctx, struct target *target) { arm7tdmi_build_reg_cache(target); - - return ERROR_OK; -} - -int arm7tdmi_quit(void) -{ + arm_semihosting_init(target); return ERROR_OK; } -int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, jtag_tap_t *tap) +int arm7tdmi_init_arch_info(struct target *target, + struct arm7_9_common *arm7_9, struct jtag_tap *tap) { - armv4_5_common_t *armv4_5; - arm7_9_common_t *arm7_9; - - arm7_9 = &arm7tdmi->arm7_9_common; - armv4_5 = &arm7_9->armv4_5_common; - /* prepare JTAG information for the new target */ arm7_9->jtag_info.tap = tap; arm7_9->jtag_info.scann_size = 4; @@ -801,42 +653,71 @@ int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, jtag_ arm7_9->enable_single_step = arm7_9_enable_eice_step; arm7_9->disable_single_step = arm7_9_disable_eice_step; - arm7_9->pre_debug_entry = NULL; + arm7_9->write_memory = arm7_9_write_memory; + arm7_9->bulk_write_memory = arm7_9_bulk_write_memory; + arm7_9->post_debug_entry = NULL; arm7_9->pre_restore_context = NULL; - arm7_9->post_restore_context = NULL; /* initialize arch-specific breakpoint handling */ arm7_9->arm_bkpt = 0xdeeedeee; arm7_9->thumb_bkpt = 0xdeee; arm7_9->dbgreq_adjust_pc = 2; - arm7_9->arch_info = arm7tdmi; - - arm7tdmi->arch_info = NULL; - arm7tdmi->common_magic = ARM7TDMI_COMMON_MAGIC; arm7_9_init_arch_info(target, arm7_9); return ERROR_OK; } -int arm7tdmi_target_create(struct target_s *target, Jim_Interp *interp ) +static int arm7tdmi_target_create(struct target *target, Jim_Interp *interp) { - arm7tdmi_common_t *arm7tdmi; + struct arm7_9_common *arm7_9; - arm7tdmi = calloc(1,sizeof(arm7tdmi_common_t)); - arm7tdmi_init_arch_info(target, arm7tdmi, target->tap); + arm7_9 = calloc(1, sizeof(struct arm7_9_common)); + arm7tdmi_init_arch_info(target, arm7_9, target->tap); + arm7_9->arm.is_armv4 = true; return ERROR_OK; } -int arm7tdmi_register_commands(struct command_context_s *cmd_ctx) -{ - int retval; +/** Holds methods for ARM7TDMI targets. */ +struct target_type arm7tdmi_target = { + .name = "arm7tdmi", - retval = arm7_9_register_commands(cmd_ctx); + .poll = arm7_9_poll, + .arch_state = arm_arch_state, - return retval; -} + .target_request_data = arm7_9_target_request_data, + + .halt = arm7_9_halt, + .resume = arm7_9_resume, + .step = arm7_9_step, + + .assert_reset = arm7_9_assert_reset, + .deassert_reset = arm7_9_deassert_reset, + .soft_reset_halt = arm7_9_soft_reset_halt, + + .get_gdb_arch = arm_get_gdb_arch, + .get_gdb_reg_list = arm_get_gdb_reg_list, + + .read_memory = arm7_9_read_memory, + .write_memory = arm7_9_write_memory_opt, + + .checksum_memory = arm_checksum_memory, + .blank_check_memory = arm_blank_check_memory, + + .run_algorithm = armv4_5_run_algorithm, + + .add_breakpoint = arm7_9_add_breakpoint, + .remove_breakpoint = arm7_9_remove_breakpoint, + .add_watchpoint = arm7_9_add_watchpoint, + .remove_watchpoint = arm7_9_remove_watchpoint, + + .commands = arm7_9_command_handlers, + .target_create = arm7tdmi_target_create, + .init_target = arm7tdmi_init_target, + .examine = arm7_9_examine, + .check_reset = arm7_9_check_reset, +};