X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm7tdmi.c;h=c94d974b8da274fc9fa97e97993c71ebb3d9a8d6;hp=93281ce58c12e9cdad3828ab81bb44552dfd54d2;hb=f90d8fa45f2d4c9d4b7990f198b232ee55cbb4e1;hpb=a28fdee804981e2015b2aba299e57d635a6e32db

diff --git a/src/target/arm7tdmi.c b/src/target/arm7tdmi.c
index 93281ce58c..c94d974b8d 100644
--- a/src/target/arm7tdmi.c
+++ b/src/target/arm7tdmi.c
@@ -28,6 +28,7 @@
 #endif
 
 #include "arm7tdmi.h"
+#include "target_type.h"
 
 
 #if 0
@@ -94,10 +95,10 @@ int arm7tdmi_examine_debug_reason(target_t *target)
 			&& (target->debug_reason != DBG_REASON_SINGLESTEP))
 	{
 		scan_field_t fields[2];
-		u8 databus[4];
-		u8 breakpoint;
+		uint8_t databus[4];
+		uint8_t breakpoint;
 
-		jtag_add_end_state(TAP_DRPAUSE);
+		jtag_set_end_state(TAP_DRPAUSE);
 
 		fields[0].tap = arm7_9->jtag_info.tap;
 		fields[0].num_bits = 1;
@@ -109,14 +110,14 @@ int arm7tdmi_examine_debug_reason(target_t *target)
 		fields[1].out_value = NULL;
 		fields[1].in_value = databus;
 
-		if((retval = arm_jtag_scann(&arm7_9->jtag_info, 0x1)) != ERROR_OK)
+		if ((retval = arm_jtag_scann(&arm7_9->jtag_info, 0x1)) != ERROR_OK)
 		{
 			return retval;
 		}
 		arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL);
 
-		jtag_add_dr_scan(2, fields, TAP_DRPAUSE);
-		if((retval = jtag_execute_queue()) != ERROR_OK)
+		jtag_add_dr_scan(2, fields, jtag_set_end_state(TAP_DRPAUSE));
+		if ((retval = jtag_execute_queue()) != ERROR_OK)
 		{
 			return retval;
 		}
@@ -126,7 +127,7 @@ int arm7tdmi_examine_debug_reason(target_t *target)
 		fields[1].in_value = NULL;
 		fields[1].out_value = databus;
 
-		jtag_add_dr_scan(2, fields, TAP_DRPAUSE);
+		jtag_add_dr_scan(2, fields, jtag_set_end_state(TAP_DRPAUSE));
 
 		if (breakpoint & 1)
 			target->debug_reason = DBG_REASON_WATCHPOINT;
@@ -138,25 +139,25 @@ int arm7tdmi_examine_debug_reason(target_t *target)
 }
 
 static int arm7tdmi_num_bits[]={1, 32};
-static __inline int arm7tdmi_clock_out_inner(arm_jtag_t *jtag_info, u32 out, int breakpoint)
+static __inline int arm7tdmi_clock_out_inner(arm_jtag_t *jtag_info, uint32_t out, int breakpoint)
 {
-	u32 values[2]={breakpoint, flip_u32(out, 32)};
+	uint32_t values[2]={breakpoint, flip_u32(out, 32)};
 
 	jtag_add_dr_out(jtag_info->tap,
 			2,
 			arm7tdmi_num_bits,
 			values,
-			TAP_INVALID);
+			jtag_get_end_state());
 
-	jtag_add_runtest(0, TAP_INVALID);
+	jtag_add_runtest(0, jtag_get_end_state());
 
 	return ERROR_OK;
 }
 
 /* put an instruction in the ARM7TDMI pipeline or write the data bus, and optionally read data */
-static __inline int arm7tdmi_clock_out(arm_jtag_t *jtag_info, u32 out, u32 *deprecated, int breakpoint)
+static __inline int arm7tdmi_clock_out(arm_jtag_t *jtag_info, uint32_t out, uint32_t *deprecated, int breakpoint)
 {
-	jtag_add_end_state(TAP_DRPAUSE);
+	jtag_set_end_state(TAP_DRPAUSE);
 	arm_jtag_scann(jtag_info, 0x1);
 	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 
@@ -164,13 +165,13 @@ static __inline int arm7tdmi_clock_out(arm_jtag_t *jtag_info, u32 out, u32 *depr
 }
 
 /* clock the target, reading the databus */
-int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
+int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, uint32_t *in)
 {
 	int retval = ERROR_OK;
 	scan_field_t fields[2];
 
-	jtag_add_end_state(TAP_DRPAUSE);
-	if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
+	jtag_set_end_state(TAP_DRPAUSE);
+	if ((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
 	{
 		return retval;
 	}
@@ -184,17 +185,17 @@ int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
 	fields[1].tap = jtag_info->tap;
 	fields[1].num_bits = 32;
 	fields[1].out_value = NULL;
-	fields[1].in_value = (u8 *)in;
+	fields[1].in_value = (uint8_t *)in;
 
-	jtag_add_dr_scan(2, fields, TAP_INVALID);
+	jtag_add_dr_scan(2, fields, jtag_get_end_state());
 
-	jtag_add_callback(arm7flip32, (u8 *)in);
+	jtag_add_callback(arm7flip32, (jtag_callback_data_t)in);
 
-	jtag_add_runtest(0, TAP_INVALID);
+	jtag_add_runtest(0, jtag_get_end_state());
 
 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 {
-		if((retval = jtag_execute_queue()) != ERROR_OK)
+		if ((retval = jtag_execute_queue()) != ERROR_OK)
 		{
 			return retval;
 		}
@@ -213,54 +214,55 @@ int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
 	return ERROR_OK;
 }
 
-void arm_endianness(u8 *tmp, void *in, int size, int be, int flip)
+void arm_endianness(uint8_t *tmp, void *in, int size, int be, int flip)
 {
-	u32 readback=le_to_h_u32(tmp);
+	uint32_t readback = le_to_h_u32(tmp);
 	if (flip)
-		readback=flip_u32(readback, 32);
+		readback = flip_u32(readback, 32);
 	switch (size)
 	{
 		case 4:
 			if (be)
 			{
-				h_u32_to_be(((u8*)in), readback);
+				h_u32_to_be(((uint8_t*)in), readback);
 			} else
 			{
-				 h_u32_to_le(((u8*)in), readback);
+				 h_u32_to_le(((uint8_t*)in), readback);
 			}
 			break;
 		case 2:
 			if (be)
 			{
-				h_u16_to_be(((u8*)in), readback & 0xffff);
+				h_u16_to_be(((uint8_t*)in), readback & 0xffff);
 			} else
 			{
-				h_u16_to_le(((u8*)in), readback & 0xffff);
+				h_u16_to_le(((uint8_t*)in), readback & 0xffff);
 			}
 			break;
 		case 1:
-			*((u8 *)in)= readback & 0xff;
+			*((uint8_t *)in)= readback & 0xff;
 			break;
 	}
 }
 
-static int arm7endianness(u8 *in, jtag_callback_data_t size, jtag_callback_data_t be, jtag_callback_data_t captured)
+static int arm7endianness(jtag_callback_data_t arg, jtag_callback_data_t size, jtag_callback_data_t be, jtag_callback_data_t captured)
 {
-	arm_endianness((u8 *)captured, in, (int)size, (int)be, 1);
+  uint8_t *in = (uint8_t *)arg;
+	arm_endianness((uint8_t *)captured, in, (int)size, (int)be, 1);
 	return ERROR_OK;
 }
 
 /* clock the target, and read the databus
  * the *in pointer points to a buffer where elements of 'size' bytes
- * are stored in big (be==1) or little (be==0) endianness
+ * are stored in big (be == 1) or little (be == 0) endianness
  */
 int arm7tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, int be)
 {
 	int retval = ERROR_OK;
 	scan_field_t fields[2];
 
-	jtag_add_end_state(TAP_DRPAUSE);
-	if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
+	jtag_set_end_state(TAP_DRPAUSE);
+	if ((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
 	{
 		return retval;
 	}
@@ -276,22 +278,22 @@ int arm7tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size,
 	fields[1].out_value = NULL;
 	jtag_alloc_in_value32(&fields[1]);
 
-	jtag_add_dr_scan(2, fields, TAP_INVALID);
+	jtag_add_dr_scan(2, fields, jtag_get_end_state());
 
-	jtag_add_callback4(arm7endianness, in, (jtag_callback_data_t)size, (jtag_callback_data_t)be, (jtag_callback_data_t)fields[1].in_value);
+	jtag_add_callback4(arm7endianness, (jtag_callback_data_t)in, (jtag_callback_data_t)size, (jtag_callback_data_t)be, (jtag_callback_data_t)fields[1].in_value);
 
-	jtag_add_runtest(0, TAP_INVALID);
+	jtag_add_runtest(0, jtag_get_end_state());
 
 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 {
-		if((retval = jtag_execute_queue()) != ERROR_OK)
+		if ((retval = jtag_execute_queue()) != ERROR_OK)
 		{
 			return retval;
 		}
 
 		if (in)
 		{
-			LOG_DEBUG("in: 0x%8.8x", *(u32*)in);
+			LOG_DEBUG("in: 0x%8.8x", *(uint32_t*)in);
 		}
 		else
 		{
@@ -303,7 +305,7 @@ int arm7tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size,
 	return ERROR_OK;
 }
 
-void arm7tdmi_change_to_arm(target_t *target, u32 *r0, u32 *pc)
+void arm7tdmi_change_to_arm(target_t *target, uint32_t *r0, uint32_t *pc)
 {
 	/* get pointers to arch-specific information */
 	armv4_5_common_t *armv4_5 = target->arch_info;
@@ -360,7 +362,7 @@ void arm7tdmi_change_to_arm(target_t *target, u32 *r0, u32 *pc)
  * The solution is to arrange for a large out/in scan in this loop and
  * and convert data afterwards.
  */
-void arm7tdmi_read_core_regs(target_t *target, u32 mask, u32* core_regs[16])
+void arm7tdmi_read_core_regs(target_t *target, uint32_t mask, uint32_t* core_regs[16])
 {
 	int i;
 	/* get pointers to arch-specific information */
@@ -381,12 +383,12 @@ void arm7tdmi_read_core_regs(target_t *target, u32 mask, u32* core_regs[16])
 	for (i = 0; i <= 15; i++)
 	{
 		if (mask & (1 << i))
-			/* nothing fetched, STM still in EXECUTE (1+i cycle) */
+			/* nothing fetched, STM still in EXECUTE (1 + i cycle) */
 			arm7tdmi_clock_data_in(jtag_info, core_regs[i]);
 	}
 }
 
-void arm7tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buffer, int size)
+void arm7tdmi_read_core_regs_target_buffer(target_t *target, uint32_t mask, void* buffer, int size)
 {
 	int i;
 	/* get pointers to arch-specific information */
@@ -394,9 +396,9 @@ void arm7tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buf
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 	arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 	int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
-	u32 *buf_u32 = buffer;
-	u16 *buf_u16 = buffer;
-	u8 *buf_u8 = buffer;
+	uint32_t *buf_u32 = buffer;
+	uint16_t *buf_u16 = buffer;
+	uint8_t *buf_u8 = buffer;
 
 	/* STMIA r0-15, [r0] at debug speed
 	 * register values will start to appear on 4th DCLK
@@ -410,7 +412,7 @@ void arm7tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buf
 
 	for (i = 0; i <= 15; i++)
 	{
-		/* nothing fetched, STM still in EXECUTE (1+i cycle), read databus */
+		/* nothing fetched, STM still in EXECUTE (1 + i cycle), read databus */
 		if (mask & (1 << i))
 		{
 			switch (size)
@@ -429,7 +431,7 @@ void arm7tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buf
 	}
 }
 
-void arm7tdmi_read_xpsr(target_t *target, u32 *xpsr, int spsr)
+void arm7tdmi_read_xpsr(target_t *target, uint32_t *xpsr, int spsr)
 {
 	/* get pointers to arch-specific information */
 	armv4_5_common_t *armv4_5 = target->arch_info;
@@ -449,14 +451,14 @@ void arm7tdmi_read_xpsr(target_t *target, u32 *xpsr, int spsr)
 	arm7tdmi_clock_data_in(jtag_info, xpsr);
 }
 
-void arm7tdmi_write_xpsr(target_t *target, u32 xpsr, int spsr)
+void arm7tdmi_write_xpsr(target_t *target, uint32_t xpsr, int spsr)
 {
 	/* get pointers to arch-specific information */
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 	arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 
-	LOG_DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr);
+	LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr);
 
 	/* MSR1 fetched */
 	arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), NULL, 0);
@@ -480,7 +482,7 @@ void arm7tdmi_write_xpsr(target_t *target, u32 xpsr, int spsr)
 	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 }
 
-void arm7tdmi_write_xpsr_im8(target_t *target, u8 xpsr_im, int rot, int spsr)
+void arm7tdmi_write_xpsr_im8(target_t *target, uint8_t xpsr_im, int rot, int spsr)
 {
 	/* get pointers to arch-specific information */
 	armv4_5_common_t *armv4_5 = target->arch_info;
@@ -499,7 +501,7 @@ void arm7tdmi_write_xpsr_im8(target_t *target, u8 xpsr_im, int rot, int spsr)
 	arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 }
 
-void arm7tdmi_write_core_regs(target_t *target, u32 mask, u32 core_regs[16])
+void arm7tdmi_write_core_regs(target_t *target, uint32_t mask, uint32_t core_regs[16])
 {
 	int i;
 	/* get pointers to arch-specific information */
@@ -520,13 +522,13 @@ void arm7tdmi_write_core_regs(target_t *target, u32 mask, u32 core_regs[16])
 	for (i = 0; i <= 15; i++)
 	{
 		if (mask & (1 << i))
-			/* nothing fetched, LDM still in EXECUTE (1+i cycle) */
+			/* nothing fetched, LDM still in EXECUTE (1 + i cycle) */
 			arm7tdmi_clock_out_inner(jtag_info, core_regs[i], 0);
 	}
 	arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
 }
 
-void arm7tdmi_load_word_regs(target_t *target, u32 mask)
+void arm7tdmi_load_word_regs(target_t *target, uint32_t mask)
 {
 	/* get pointers to arch-specific information */
 	armv4_5_common_t *armv4_5 = target->arch_info;
@@ -565,7 +567,7 @@ void arm7tdmi_load_byte_reg(target_t *target, int num)
 	arm7tdmi_clock_out(jtag_info, ARMV4_5_LDRB_IP(num, 0), NULL, 0);
 }
 
-void arm7tdmi_store_word_regs(target_t *target, u32 mask)
+void arm7tdmi_store_word_regs(target_t *target, uint32_t mask)
 {
 	/* get pointers to arch-specific information */
 	armv4_5_common_t *armv4_5 = target->arch_info;
@@ -604,7 +606,7 @@ void arm7tdmi_store_byte_reg(target_t *target, int num)
 	arm7tdmi_clock_out(jtag_info, ARMV4_5_STRB_IP(num, 0), NULL, 0);
 }
 
-void arm7tdmi_write_pc(target_t *target, u32 pc)
+void arm7tdmi_write_pc(target_t *target, uint32_t pc)
 {
 	/* get pointers to arch-specific information */
 	armv4_5_common_t *armv4_5 = target->arch_info;
@@ -718,12 +720,12 @@ int arm7tdmi_examine(struct target_s *target)
 	int retval;
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
-	if (!target->type->examined)
+	if (!target_was_examined(target))
 	{
 		/* get pointers to arch-specific information */
 		reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
-		reg_cache_t *t=embeddedice_build_reg_cache(target, arm7_9);
-		if (t==NULL)
+		reg_cache_t *t = embeddedice_build_reg_cache(target, arm7_9);
+		if (t == NULL)
 			return ERROR_FAIL;
 
 		(*cache_p) = t;
@@ -735,15 +737,15 @@ int arm7tdmi_examine(struct target_s *target)
 			(*cache_p)->next = etm_build_reg_cache(target, jtag_info, arm7_9->etm_ctx);
 			arm7_9->etm_ctx->reg_cache = (*cache_p)->next;
 		}
-		target->type->examined = 1;
+		target_set_examined(target);
 	}
-	if ((retval=embeddedice_setup(target))!=ERROR_OK)
+	if ((retval = embeddedice_setup(target)) != ERROR_OK)
 		return retval;
-	if ((retval=arm7_9_setup(target))!=ERROR_OK)
+	if ((retval = arm7_9_setup(target)) != ERROR_OK)
 		return retval;
 	if (arm7_9->etm_ctx)
 	{
-		if ((retval=etm_setup(target))!=ERROR_OK)
+		if ((retval = etm_setup(target)) != ERROR_OK)
 			return retval;
 	}
 	return ERROR_OK;
@@ -820,7 +822,7 @@ int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, jtag_
 	return ERROR_OK;
 }
 
-int arm7tdmi_target_create( struct target_s *target, Jim_Interp *interp )
+int arm7tdmi_target_create(struct target_s *target, Jim_Interp *interp )
 {
 	arm7tdmi_common_t *arm7tdmi;