X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm7tdmi.c;h=aea012dc079c2e24d8652152c355a4d2ad1dec0c;hp=be98c8e193f310a945f841dc0d5fa0e87188ae22;hb=ac927559c3ce5406adac34b9d4ca4ecb37a48181;hpb=c45de8073d027f1a4d39640dc140666f27960e3b diff --git a/src/target/arm7tdmi.c b/src/target/arm7tdmi.c index be98c8e193..aea012dc07 100644 --- a/src/target/arm7tdmi.c +++ b/src/target/arm7tdmi.c @@ -5,6 +5,9 @@ * Copyright (C) 2008 by Spencer Oliver * * spen@spen-soft.co.uk * * * + * Copyright (C) 2007,2008 Øyvind Harboe * + * oyvind.harboe@zylin.com * + * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * * the Free Software Foundation; either version 2 of the License, or * @@ -25,121 +28,52 @@ #endif #include "arm7tdmi.h" +#include "target_type.h" -#include "arm7_9_common.h" -#include "register.h" -#include "target.h" -#include "armv4_5.h" -#include "embeddedice.h" -#include "etm.h" -#include "log.h" -#include "jtag.h" -#include "arm_jtag.h" -#include -#include +/* + * For information about ARM7TDMI, see ARM DDI 0210C (r4p1) + * or ARM DDI 0029G (r3). "Debug In Depth", Appendix B, + * covers JTAG support. + */ #if 0 #define _DEBUG_INSTRUCTION_EXECUTION_ #endif -/* cli handling */ -int arm7tdmi_register_commands(struct command_context_s *cmd_ctx); - -/* forward declarations */ - -int arm7tdmi_target_create(struct target_s *target,Jim_Interp *interp); -int arm7tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target); -int arm7tdmi_quit(void); - -/* target function declarations */ -int arm7tdmi_poll(struct target_s *target); -int arm7tdmi_halt(target_t *target); - -target_type_t arm7tdmi_target = -{ - .name = "arm7tdmi", - - .poll = arm7_9_poll, - .arch_state = armv4_5_arch_state, - - .target_request_data = arm7_9_target_request_data, - - .halt = arm7_9_halt, - .resume = arm7_9_resume, - .step = arm7_9_step, - - .assert_reset = arm7_9_assert_reset, - .deassert_reset = arm7_9_deassert_reset, - .soft_reset_halt = arm7_9_soft_reset_halt, - - .get_gdb_reg_list = armv4_5_get_gdb_reg_list, - - .read_memory = arm7_9_read_memory, - .write_memory = arm7_9_write_memory, - .bulk_write_memory = arm7_9_bulk_write_memory, - .checksum_memory = arm7_9_checksum_memory, - .blank_check_memory = arm7_9_blank_check_memory, - - .run_algorithm = armv4_5_run_algorithm, - - .add_breakpoint = arm7_9_add_breakpoint, - .remove_breakpoint = arm7_9_remove_breakpoint, - .add_watchpoint = arm7_9_add_watchpoint, - .remove_watchpoint = arm7_9_remove_watchpoint, - - .register_commands = arm7tdmi_register_commands, - .target_create = arm7tdmi_target_create, - .init_target = arm7tdmi_init_target, - .examine = arm7tdmi_examine, - .quit = arm7tdmi_quit -}; - -int arm7tdmi_examine_debug_reason(target_t *target) +static int arm7tdmi_examine_debug_reason(target_t *target) { int retval = ERROR_OK; - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); /* only check the debug reason if we don't know it already */ if ((target->debug_reason != DBG_REASON_DBGRQ) && (target->debug_reason != DBG_REASON_SINGLESTEP)) { - scan_field_t fields[2]; - u8 databus[4]; - u8 breakpoint; + struct scan_field fields[2]; + uint8_t databus[4]; + uint8_t breakpoint; - jtag_add_end_state(TAP_DRPAUSE); + jtag_set_end_state(TAP_DRPAUSE); fields[0].tap = arm7_9->jtag_info.tap; fields[0].num_bits = 1; fields[0].out_value = NULL; - fields[0].out_mask = NULL; fields[0].in_value = &breakpoint; - fields[0].in_check_value = NULL; - fields[0].in_check_mask = NULL; - fields[0].in_handler = NULL; - fields[0].in_handler_priv = NULL; fields[1].tap = arm7_9->jtag_info.tap; fields[1].num_bits = 32; fields[1].out_value = NULL; - fields[1].out_mask = NULL; fields[1].in_value = databus; - fields[1].in_check_value = NULL; - fields[1].in_check_mask = NULL; - fields[1].in_handler = NULL; - fields[1].in_handler_priv = NULL; - if((retval = arm_jtag_scann(&arm7_9->jtag_info, 0x1)) != ERROR_OK) + if ((retval = arm_jtag_scann(&arm7_9->jtag_info, 0x1)) != ERROR_OK) { return retval; } arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL); - jtag_add_dr_scan(2, fields, TAP_DRPAUSE); - if((retval = jtag_execute_queue()) != ERROR_OK) + jtag_add_dr_scan(2, fields, jtag_set_end_state(TAP_DRPAUSE)); + if ((retval = jtag_execute_queue()) != ERROR_OK) { return retval; } @@ -149,7 +83,7 @@ int arm7tdmi_examine_debug_reason(target_t *target) fields[1].in_value = NULL; fields[1].out_value = databus; - jtag_add_dr_scan(2, fields, TAP_DRPAUSE); + jtag_add_dr_scan(2, fields, jtag_set_end_state(TAP_DRPAUSE)); if (breakpoint & 1) target->debug_reason = DBG_REASON_WATCHPOINT; @@ -160,26 +94,32 @@ int arm7tdmi_examine_debug_reason(target_t *target) return ERROR_OK; } -static int arm7tdmi_num_bits[]={1, 32}; -static __inline int arm7tdmi_clock_out_inner(arm_jtag_t *jtag_info, u32 out, int breakpoint) +static const int arm7tdmi_num_bits[] = {1, 32}; + +static __inline int arm7tdmi_clock_out_inner(struct arm_jtag *jtag_info, uint32_t out, int breakpoint) { - u32 values[2]={breakpoint, flip_u32(out, 32)}; + uint32_t values[2]={breakpoint, flip_u32(out, 32)}; jtag_add_dr_out(jtag_info->tap, 2, arm7tdmi_num_bits, values, - -1); + jtag_get_end_state()); - jtag_add_runtest(0, -1); + jtag_add_runtest(0, jtag_get_end_state()); return ERROR_OK; } -/* put an instruction in the ARM7TDMI pipeline or write the data bus, and optionally read data */ -static __inline int arm7tdmi_clock_out(arm_jtag_t *jtag_info, u32 out, u32 *deprecated, int breakpoint) +/* put an instruction in the ARM7TDMI pipeline or write the data bus, + * and optionally read data + * + * FIXME remove the unused "deprecated" parameter + */ +static __inline int arm7tdmi_clock_out(struct arm_jtag *jtag_info, + uint32_t out, uint32_t *deprecated, int breakpoint) { - jtag_add_end_state(TAP_DRPAUSE); + jtag_set_end_state(TAP_DRPAUSE); arm_jtag_scann(jtag_info, 0x1); arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); @@ -187,13 +127,13 @@ static __inline int arm7tdmi_clock_out(arm_jtag_t *jtag_info, u32 out, u32 *depr } /* clock the target, reading the databus */ -int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in) +static int arm7tdmi_clock_data_in(struct arm_jtag *jtag_info, uint32_t *in) { int retval = ERROR_OK; - scan_field_t fields[2]; + struct scan_field fields[2]; - jtag_add_end_state(TAP_DRPAUSE); - if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK) + jtag_set_end_state(TAP_DRPAUSE); + if ((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK) { return retval; } @@ -202,59 +142,85 @@ int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in) fields[0].tap = jtag_info->tap; fields[0].num_bits = 1; fields[0].out_value = NULL; - fields[0].out_mask = NULL; fields[0].in_value = NULL; - fields[0].in_check_value = NULL; - fields[0].in_check_mask = NULL; - fields[0].in_handler = NULL; - fields[0].in_handler_priv = NULL; fields[1].tap = jtag_info->tap; fields[1].num_bits = 32; fields[1].out_value = NULL; - fields[1].out_mask = NULL; - fields[1].in_value = NULL; - fields[1].in_handler = arm_jtag_buf_to_u32_flip; - fields[1].in_handler_priv = in; - fields[1].in_check_value = NULL; - fields[1].in_check_mask = NULL; + fields[1].in_value = (uint8_t *)in; - jtag_add_dr_scan(2, fields, -1); + jtag_add_dr_scan(2, fields, jtag_get_end_state()); - jtag_add_runtest(0, -1); + jtag_add_callback(arm7flip32, (jtag_callback_data_t)in); + + jtag_add_runtest(0, jtag_get_end_state()); #ifdef _DEBUG_INSTRUCTION_EXECUTION_ -{ - if((retval = jtag_execute_queue()) != ERROR_OK) - { - return retval; - } + if ((retval = jtag_execute_queue()) != ERROR_OK) + return retval; - if (in) - { - LOG_DEBUG("in: 0x%8.8x", *in); - } - else - { - LOG_ERROR("BUG: called with in == NULL"); - } -} + if (in) + LOG_DEBUG("in: 0x%8.8x", *in); + else + LOG_ERROR("BUG: called with in == NULL"); #endif return ERROR_OK; } +void arm_endianness(uint8_t *tmp, void *in, int size, int be, int flip) +{ + uint32_t readback = le_to_h_u32(tmp); + if (flip) + readback = flip_u32(readback, 32); + switch (size) + { + case 4: + if (be) + { + h_u32_to_be(((uint8_t*)in), readback); + } else + { + h_u32_to_le(((uint8_t*)in), readback); + } + break; + case 2: + if (be) + { + h_u16_to_be(((uint8_t*)in), readback & 0xffff); + } else + { + h_u16_to_le(((uint8_t*)in), readback & 0xffff); + } + break; + case 1: + *((uint8_t *)in)= readback & 0xff; + break; + } +} + +static int arm7endianness(jtag_callback_data_t arg, + jtag_callback_data_t size, jtag_callback_data_t be, + jtag_callback_data_t captured) +{ + uint8_t *in = (uint8_t *)arg; + + arm_endianness((uint8_t *)captured, in, (int)size, (int)be, 1); + return ERROR_OK; +} + /* clock the target, and read the databus * the *in pointer points to a buffer where elements of 'size' bytes - * are stored in big (be==1) or little (be==0) endianness + * are stored in big (be == 1) or little (be == 0) endianness */ -int arm7tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, int be) +static int arm7tdmi_clock_data_in_endianness(struct arm_jtag *jtag_info, + void *in, int size, int be) { int retval = ERROR_OK; - scan_field_t fields[2]; + struct scan_field fields[2]; - jtag_add_end_state(TAP_DRPAUSE); - if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK) + jtag_set_end_state(TAP_DRPAUSE); + if ((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK) { return retval; } @@ -263,48 +229,29 @@ int arm7tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, fields[0].tap = jtag_info->tap; fields[0].num_bits = 1; fields[0].out_value = NULL; - fields[0].out_mask = NULL; fields[0].in_value = NULL; - fields[0].in_check_value = NULL; - fields[0].in_check_mask = NULL; - fields[0].in_handler = NULL; - fields[0].in_handler_priv = NULL; fields[1].tap = jtag_info->tap; fields[1].num_bits = 32; fields[1].out_value = NULL; - fields[1].out_mask = NULL; - fields[1].in_value = NULL; - switch (size) - { - case 4: - fields[1].in_handler = (be) ? arm_jtag_buf_to_be32_flip : arm_jtag_buf_to_le32_flip; - break; - case 2: - fields[1].in_handler = (be) ? arm_jtag_buf_to_be16_flip : arm_jtag_buf_to_le16_flip; - break; - case 1: - fields[1].in_handler = arm_jtag_buf_to_8_flip; - break; - } - fields[1].in_handler_priv = in; - fields[1].in_check_value = NULL; - fields[1].in_check_mask = NULL; + jtag_alloc_in_value32(&fields[1]); - jtag_add_dr_scan(2, fields, -1); + jtag_add_dr_scan(2, fields, jtag_get_end_state()); - jtag_add_runtest(0, -1); + jtag_add_callback4(arm7endianness, (jtag_callback_data_t)in, (jtag_callback_data_t)size, (jtag_callback_data_t)be, (jtag_callback_data_t)fields[1].in_value); + + jtag_add_runtest(0, jtag_get_end_state()); #ifdef _DEBUG_INSTRUCTION_EXECUTION_ { - if((retval = jtag_execute_queue()) != ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) { return retval; } if (in) { - LOG_DEBUG("in: 0x%8.8x", *(u32*)in); + LOG_DEBUG("in: 0x%8.8x", *(uint32_t*)in); } else { @@ -316,12 +263,11 @@ int arm7tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, return ERROR_OK; } -void arm7tdmi_change_to_arm(target_t *target, u32 *r0, u32 *pc) +static void arm7tdmi_change_to_arm(target_t *target, + uint32_t *r0, uint32_t *pc) { - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* save r0 before using it and put system in ARM state * to allow common handling of ARM and THUMB debugging */ @@ -364,16 +310,21 @@ void arm7tdmi_change_to_arm(target_t *target, u32 *r0, u32 *pc) * reading PC in Thumb state gives address of instruction + 4 */ *pc -= 0xa; - } -void arm7tdmi_read_core_regs(target_t *target, u32 mask, u32* core_regs[16]) + +/* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many + * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s? + * + * The solution is to arrange for a large out/in scan in this loop and + * and convert data afterwards. + */ +static void arm7tdmi_read_core_regs(target_t *target, + uint32_t mask, uint32_t* core_regs[16]) { int i; - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* STMIA r0-15, [r0] at debug speed * register values will start to appear on 4th DCLK @@ -388,23 +339,21 @@ void arm7tdmi_read_core_regs(target_t *target, u32 mask, u32* core_regs[16]) for (i = 0; i <= 15; i++) { if (mask & (1 << i)) - /* nothing fetched, STM still in EXECUTE (1+i cycle) */ + /* nothing fetched, STM still in EXECUTE (1 + i cycle) */ arm7tdmi_clock_data_in(jtag_info, core_regs[i]); } - } -void arm7tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buffer, int size) +static void arm7tdmi_read_core_regs_target_buffer(target_t *target, + uint32_t mask, void* buffer, int size) { int i; - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0; - u32 *buf_u32 = buffer; - u16 *buf_u16 = buffer; - u8 *buf_u8 = buffer; + uint32_t *buf_u32 = buffer; + uint16_t *buf_u16 = buffer; + uint8_t *buf_u8 = buffer; /* STMIA r0-15, [r0] at debug speed * register values will start to appear on 4th DCLK @@ -418,7 +367,7 @@ void arm7tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buf for (i = 0; i <= 15; i++) { - /* nothing fetched, STM still in EXECUTE (1+i cycle), read databus */ + /* nothing fetched, STM still in EXECUTE (1 + i cycle), read databus */ if (mask & (1 << i)) { switch (size) @@ -435,15 +384,12 @@ void arm7tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buf } } } - } -void arm7tdmi_read_xpsr(target_t *target, u32 *xpsr, int spsr) +static void arm7tdmi_read_xpsr(target_t *target, uint32_t *xpsr, int spsr) { - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* MRS r0, cpsr */ arm7tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), NULL, 0); @@ -456,17 +402,14 @@ void arm7tdmi_read_xpsr(target_t *target, u32 *xpsr, int spsr) arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0); /* nothing fetched, STR still in EXECUTE (2nd cycle) */ arm7tdmi_clock_data_in(jtag_info, xpsr); - } -void arm7tdmi_write_xpsr(target_t *target, u32 xpsr, int spsr) +static void arm7tdmi_write_xpsr(target_t *target, uint32_t xpsr, int spsr) { - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; - LOG_DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr); + LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr); /* MSR1 fetched */ arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), NULL, 0); @@ -490,12 +433,11 @@ void arm7tdmi_write_xpsr(target_t *target, u32 xpsr, int spsr) arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0); } -void arm7tdmi_write_xpsr_im8(target_t *target, u8 xpsr_im, int rot, int spsr) +static void arm7tdmi_write_xpsr_im8(target_t *target, + uint8_t xpsr_im, int rot, int spsr) { - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr); @@ -507,16 +449,14 @@ void arm7tdmi_write_xpsr_im8(target_t *target, u8 xpsr_im, int rot, int spsr) arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0); /* nothing fetched, MSR in EXECUTE (2) */ arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0); - } -void arm7tdmi_write_core_regs(target_t *target, u32 mask, u32 core_regs[16]) +static void arm7tdmi_write_core_regs(target_t *target, + uint32_t mask, uint32_t core_regs[16]) { int i; - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* LDMIA r0-15, [r0] at debug speed * register values will start to appear on 4th DCLK @@ -531,103 +471,82 @@ void arm7tdmi_write_core_regs(target_t *target, u32 mask, u32 core_regs[16]) for (i = 0; i <= 15; i++) { if (mask & (1 << i)) - /* nothing fetched, LDM still in EXECUTE (1+i cycle) */ + /* nothing fetched, LDM still in EXECUTE (1 + i cycle) */ arm7tdmi_clock_out_inner(jtag_info, core_regs[i], 0); } arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0); - } -void arm7tdmi_load_word_regs(target_t *target, u32 mask) +static void arm7tdmi_load_word_regs(target_t *target, uint32_t mask) { - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* put system-speed load-multiple into the pipeline */ arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0); arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1); arm7tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 1), NULL, 0); - } -void arm7tdmi_load_hword_reg(target_t *target, int num) +static void arm7tdmi_load_hword_reg(target_t *target, int num) { - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* put system-speed load half-word into the pipeline */ arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0); arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1); arm7tdmi_clock_out(jtag_info, ARMV4_5_LDRH_IP(num, 0), NULL, 0); - } -void arm7tdmi_load_byte_reg(target_t *target, int num) +static void arm7tdmi_load_byte_reg(target_t *target, int num) { - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* put system-speed load byte into the pipeline */ arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0); arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1); arm7tdmi_clock_out(jtag_info, ARMV4_5_LDRB_IP(num, 0), NULL, 0); - } -void arm7tdmi_store_word_regs(target_t *target, u32 mask) +static void arm7tdmi_store_word_regs(target_t *target, uint32_t mask) { - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* put system-speed store-multiple into the pipeline */ arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0); arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1); arm7tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask, 0, 1), NULL, 0); - } -void arm7tdmi_store_hword_reg(target_t *target, int num) +static void arm7tdmi_store_hword_reg(target_t *target, int num) { - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* put system-speed store half-word into the pipeline */ arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0); arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1); arm7tdmi_clock_out(jtag_info, ARMV4_5_STRH_IP(num, 0), NULL, 0); - } -void arm7tdmi_store_byte_reg(target_t *target, int num) +static void arm7tdmi_store_byte_reg(target_t *target, int num) { - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* put system-speed store byte into the pipeline */ arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0); arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1); arm7tdmi_clock_out(jtag_info, ARMV4_5_STRB_IP(num, 0), NULL, 0); - } -void arm7tdmi_write_pc(target_t *target, u32 pc) +static void arm7tdmi_write_pc(target_t *target, uint32_t pc) { - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* LDMIA r0-15, [r0] at debug speed * register values will start to appear on 4th DCLK @@ -649,28 +568,24 @@ void arm7tdmi_write_pc(target_t *target, u32 pc) arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0); } -void arm7tdmi_branch_resume(target_t *target) +static void arm7tdmi_branch_resume(target_t *target) { - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1); arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_B(0xfffffa, 0), 0); - } -void arm7tdmi_branch_resume_thumb(target_t *target) +static void arm7tdmi_branch_resume_thumb(target_t *target) { - LOG_DEBUG("-"); - - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; + LOG_DEBUG("-"); + /* LDMIA r0, [r0] at debug speed * register values will start to appear on 4th DCLK */ @@ -720,14 +635,12 @@ void arm7tdmi_branch_resume_thumb(target_t *target) arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 1); arm7tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7f8), NULL, 0); - } -void arm7tdmi_build_reg_cache(target_t *target) +static void arm7tdmi_build_reg_cache(target_t *target) { - reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache); - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; + struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache); + struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); (*cache_p) = armv4_5_build_reg_cache(target, armv4_5); armv4_5->core_cache = (*cache_p); @@ -735,35 +648,37 @@ void arm7tdmi_build_reg_cache(target_t *target) int arm7tdmi_examine(struct target_s *target) { + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); int retval; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - if (!target->type->examined) + + + if (!target_was_examined(target)) { /* get pointers to arch-specific information */ - reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache); - reg_cache_t *t=embeddedice_build_reg_cache(target, arm7_9); - if (t==NULL) + struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache); + struct reg_cache *t = embeddedice_build_reg_cache(target, arm7_9); + if (t == NULL) return ERROR_FAIL; (*cache_p) = t; arm7_9->eice_cache = (*cache_p); - if (arm7_9->etm_ctx) + if (arm7_9->armv4_5_common.etm) { - arm_jtag_t *jtag_info = &arm7_9->jtag_info; - (*cache_p)->next = etm_build_reg_cache(target, jtag_info, arm7_9->etm_ctx); - arm7_9->etm_ctx->reg_cache = (*cache_p)->next; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; + (*cache_p)->next = etm_build_reg_cache(target, + jtag_info, arm7_9->armv4_5_common.etm); + arm7_9->armv4_5_common.etm->reg_cache = (*cache_p)->next; } - target->type->examined = 1; + target_set_examined(target); } - if ((retval=embeddedice_setup(target))!=ERROR_OK) + if ((retval = embeddedice_setup(target)) != ERROR_OK) return retval; - if ((retval=arm7_9_setup(target))!=ERROR_OK) + if ((retval = arm7_9_setup(target)) != ERROR_OK) return retval; - if (arm7_9->etm_ctx) + if (arm7_9->armv4_5_common.etm) { - if ((retval=etm_setup(target))!=ERROR_OK) + if ((retval = etm_setup(target)) != ERROR_OK) return retval; } return ERROR_OK; @@ -771,26 +686,14 @@ int arm7tdmi_examine(struct target_s *target) int arm7tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target) { - arm7tdmi_build_reg_cache(target); - return ERROR_OK; - -} - -int arm7tdmi_quit(void) -{ - return ERROR_OK; } -int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, jtag_tap_t *tap, const char *variant) +int arm7tdmi_init_arch_info(target_t *target, struct arm7tdmi_common *arm7tdmi, struct jtag_tap *tap) { - armv4_5_common_t *armv4_5; - arm7_9_common_t *arm7_9; - - arm7_9 = &arm7tdmi->arm7_9_common; - armv4_5 = &arm7_9->armv4_5_common; + struct arm7_9_common *arm7_9 = &arm7tdmi->arm7_9_common; /* prepare JTAG information for the new target */ arm7_9->jtag_info.tap = tap; @@ -822,7 +725,6 @@ int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, jtag_ arm7_9->enable_single_step = arm7_9_enable_eice_step; arm7_9->disable_single_step = arm7_9_disable_eice_step; - arm7_9->pre_debug_entry = NULL; arm7_9->post_debug_entry = NULL; arm7_9->pre_restore_context = NULL; @@ -833,45 +735,58 @@ int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, jtag_ arm7_9->thumb_bkpt = 0xdeee; arm7_9->dbgreq_adjust_pc = 2; - arm7_9->arch_info = arm7tdmi; - - arm7tdmi->arch_info = NULL; - arm7tdmi->common_magic = ARM7TDMI_COMMON_MAGIC; - - if (variant) - { - arm7tdmi->variant = strdup(variant); - } - else - { - arm7tdmi->variant = strdup(""); - } arm7_9_init_arch_info(target, arm7_9); return ERROR_OK; } +static int arm7tdmi_target_create(struct target_s *target, Jim_Interp *interp) +{ + struct arm7tdmi_common *arm7tdmi; + arm7tdmi = calloc(1,sizeof(struct arm7tdmi_common)); + arm7tdmi_init_arch_info(target, arm7tdmi, target->tap); + arm7tdmi->arm7_9_common.armv4_5_common.is_armv4 = true; -int arm7tdmi_target_create( struct target_s *target, Jim_Interp *interp ) + return ERROR_OK; +} + +/** Holds methods for ARM7TDMI targets. */ +struct target_type arm7tdmi_target = { - arm7tdmi_common_t *arm7tdmi; + .name = "arm7tdmi", - arm7tdmi = calloc(1,sizeof(arm7tdmi_common_t)); + .poll = arm7_9_poll, + .arch_state = armv4_5_arch_state, - arm7tdmi_init_arch_info(target, arm7tdmi, target->tap, target->variant); + .target_request_data = arm7_9_target_request_data, - return ERROR_OK; -} + .halt = arm7_9_halt, + .resume = arm7_9_resume, + .step = arm7_9_step, + .assert_reset = arm7_9_assert_reset, + .deassert_reset = arm7_9_deassert_reset, + .soft_reset_halt = arm7_9_soft_reset_halt, -int arm7tdmi_register_commands(struct command_context_s *cmd_ctx) -{ - int retval; + .get_gdb_reg_list = armv4_5_get_gdb_reg_list, + + .read_memory = arm7_9_read_memory, + .write_memory = arm7_9_write_memory, + .bulk_write_memory = arm7_9_bulk_write_memory, + .checksum_memory = arm7_9_checksum_memory, + .blank_check_memory = arm7_9_blank_check_memory, - retval = arm7_9_register_commands(cmd_ctx); + .run_algorithm = armv4_5_run_algorithm, - return retval; + .add_breakpoint = arm7_9_add_breakpoint, + .remove_breakpoint = arm7_9_remove_breakpoint, + .add_watchpoint = arm7_9_add_watchpoint, + .remove_watchpoint = arm7_9_remove_watchpoint, -} + .register_commands = arm7_9_register_commands, + .target_create = arm7tdmi_target_create, + .init_target = arm7tdmi_init_target, + .examine = arm7tdmi_examine, +};