X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm7tdmi.c;h=2e9d28d835453f64cbb6c8082aeebc94c7fa33a1;hp=52a15bc66984941675a86aeeeeedb5dfe2afbd0b;hb=a28eaa85f73759bb189a46308642502c9fa5aa4b;hpb=0d7d64b5e9a463f63deb19f00efa14e6e5b1c34e diff --git a/src/target/arm7tdmi.c b/src/target/arm7tdmi.c index 52a15bc669..2e9d28d835 100644 --- a/src/target/arm7tdmi.c +++ b/src/target/arm7tdmi.c @@ -2,6 +2,9 @@ * Copyright (C) 2005 by Dominic Rath * * Dominic.Rath@gmx.de * * * + * Copyright (C) 2008 by Spencer Oliver * + * spen@spen-soft.co.uk * + * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * * the Free Software Foundation; either version 2 of the License, or * @@ -44,9 +47,10 @@ int arm7tdmi_register_commands(struct command_context_s *cmd_ctx); /* forward declarations */ -int arm7tdmi_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target); + +int arm7tdmi_target_create(struct target_s *target,Jim_Interp *interp); int arm7tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target); -int arm7tdmi_quit(); +int arm7tdmi_quit(void); /* target function declarations */ int arm7tdmi_poll(struct target_s *target); @@ -75,6 +79,7 @@ target_type_t arm7tdmi_target = .write_memory = arm7_9_write_memory, .bulk_write_memory = arm7_9_bulk_write_memory, .checksum_memory = arm7_9_checksum_memory, + .blank_check_memory = arm7_9_blank_check_memory, .run_algorithm = armv4_5_run_algorithm, @@ -83,8 +88,8 @@ target_type_t arm7tdmi_target = .add_watchpoint = arm7_9_add_watchpoint, .remove_watchpoint = arm7_9_remove_watchpoint, - .register_commands = arm7tdmi_register_commands, - .target_command = arm7tdmi_target_command, + .register_commands = arm7tdmi_register_commands, + .target_create = arm7tdmi_target_create, .init_target = arm7tdmi_init_target, .examine = arm7tdmi_examine, .quit = arm7tdmi_quit @@ -92,6 +97,7 @@ target_type_t arm7tdmi_target = int arm7tdmi_examine_debug_reason(target_t *target) { + int retval = ERROR_OK; /* get pointers to arch-specific information */ armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; @@ -106,7 +112,7 @@ int arm7tdmi_examine_debug_reason(target_t *target) jtag_add_end_state(TAP_PD); - fields[0].device = arm7_9->jtag_info.chain_pos; + fields[0].tap = arm7_9->jtag_info.tap; fields[0].num_bits = 1; fields[0].out_value = NULL; fields[0].out_mask = NULL; @@ -116,7 +122,7 @@ int arm7tdmi_examine_debug_reason(target_t *target) fields[0].in_handler = NULL; fields[0].in_handler_priv = NULL; - fields[1].device = arm7_9->jtag_info.chain_pos; + fields[1].tap = arm7_9->jtag_info.tap; fields[1].num_bits = 32; fields[1].out_value = NULL; fields[1].out_mask = NULL; @@ -126,11 +132,17 @@ int arm7tdmi_examine_debug_reason(target_t *target) fields[1].in_handler = NULL; fields[1].in_handler_priv = NULL; - arm_jtag_scann(&arm7_9->jtag_info, 0x1); + if((retval = arm_jtag_scann(&arm7_9->jtag_info, 0x1)) != ERROR_OK) + { + return retval; + } arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL); jtag_add_dr_scan(2, fields, TAP_PD); - jtag_execute_queue(); + if((retval = jtag_execute_queue()) != ERROR_OK) + { + return retval; + } fields[0].in_value = NULL; fields[0].out_value = &breakpoint; @@ -148,78 +160,46 @@ int arm7tdmi_examine_debug_reason(target_t *target) return ERROR_OK; } -/* put an instruction in the ARM7TDMI pipeline or write the data bus, and optionally read data */ -int arm7tdmi_clock_out(arm_jtag_t *jtag_info, u32 out, u32 *in, int breakpoint) +static int arm7tdmi_num_bits[]={1, 32}; +static __inline int arm7tdmi_clock_out_inner(arm_jtag_t *jtag_info, u32 out, int breakpoint) { - scan_field_t fields[2]; - u8 out_buf[4]; - u8 breakpoint_buf; - - buf_set_u32(out_buf, 0, 32, flip_u32(out, 32)); - buf_set_u32(&breakpoint_buf, 0, 1, breakpoint); + u32 values[2]={breakpoint, flip_u32(out, 32)}; + + jtag_add_dr_out(jtag_info->tap, + 2, + arm7tdmi_num_bits, + values, + -1); + + jtag_add_runtest(0, -1); + + return ERROR_OK; +} +/* put an instruction in the ARM7TDMI pipeline or write the data bus, and optionally read data */ +static __inline int arm7tdmi_clock_out(arm_jtag_t *jtag_info, u32 out, u32 *deprecated, int breakpoint) +{ jtag_add_end_state(TAP_PD); arm_jtag_scann(jtag_info, 0x1); arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); - fields[0].device = jtag_info->chain_pos; - fields[0].num_bits = 1; - fields[0].out_value = &breakpoint_buf; - fields[0].out_mask = NULL; - fields[0].in_value = NULL; - fields[0].in_check_value = NULL; - fields[0].in_check_mask = NULL; - fields[0].in_handler = NULL; - fields[0].in_handler_priv = NULL; - - fields[1].device = jtag_info->chain_pos; - fields[1].num_bits = 32; - fields[1].out_value = out_buf; - fields[1].out_mask = NULL; - fields[1].in_value = NULL; - if (in) - { - fields[1].in_handler = arm_jtag_buf_to_u32_flip; - fields[1].in_handler_priv = in; - } - else - { - fields[1].in_handler = NULL; - fields[1].in_handler_priv = NULL; - } - fields[1].in_check_value = NULL; - fields[1].in_check_mask = NULL; - - jtag_add_dr_scan(2, fields, -1); - - jtag_add_runtest(0, -1); - -#ifdef _DEBUG_INSTRUCTION_EXECUTION_ -{ - jtag_execute_queue(); - - if (in) - { - LOG_DEBUG("out: 0x%8.8x, in: 0x%8.8x", out, *in); - } - else - LOG_DEBUG("out: 0x%8.8x", out); -} -#endif - - return ERROR_OK; + return arm7tdmi_clock_out_inner(jtag_info, out, breakpoint); } /* clock the target, reading the databus */ int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in) { + int retval = ERROR_OK; scan_field_t fields[2]; jtag_add_end_state(TAP_PD); - arm_jtag_scann(jtag_info, 0x1); + if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK) + { + return retval; + } arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); - fields[0].device = jtag_info->chain_pos; + fields[0].tap = jtag_info->tap; fields[0].num_bits = 1; fields[0].out_value = NULL; fields[0].out_mask = NULL; @@ -229,7 +209,7 @@ int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in) fields[0].in_handler = NULL; fields[0].in_handler_priv = NULL; - fields[1].device = jtag_info->chain_pos; + fields[1].tap = jtag_info->tap; fields[1].num_bits = 32; fields[1].out_value = NULL; fields[1].out_mask = NULL; @@ -245,7 +225,10 @@ int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in) #ifdef _DEBUG_INSTRUCTION_EXECUTION_ { - jtag_execute_queue(); + if((retval = jtag_execute_queue()) != ERROR_OK) + { + return retval; + } if (in) { @@ -267,13 +250,17 @@ int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in) */ int arm7tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, int be) { + int retval = ERROR_OK; scan_field_t fields[2]; jtag_add_end_state(TAP_PD); - arm_jtag_scann(jtag_info, 0x1); + if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK) + { + return retval; + } arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); - fields[0].device = jtag_info->chain_pos; + fields[0].tap = jtag_info->tap; fields[0].num_bits = 1; fields[0].out_value = NULL; fields[0].out_mask = NULL; @@ -283,7 +270,7 @@ int arm7tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, fields[0].in_handler = NULL; fields[0].in_handler_priv = NULL; - fields[1].device = jtag_info->chain_pos; + fields[1].tap = jtag_info->tap; fields[1].num_bits = 32; fields[1].out_value = NULL; fields[1].out_mask = NULL; @@ -310,11 +297,14 @@ int arm7tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, #ifdef _DEBUG_INSTRUCTION_EXECUTION_ { - jtag_execute_queue(); + if((retval = jtag_execute_queue()) != ERROR_OK) + { + return retval; + } if (in) { - LOG_DEBUG("in: 0x%8.8x", *in); + LOG_DEBUG("in: 0x%8.8x", *(u32*)in); } else { @@ -534,17 +524,17 @@ void arm7tdmi_write_core_regs(target_t *target, u32 mask, u32 core_regs[16]) arm7tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 0), NULL, 0); /* fetch NOP, LDM in DECODE stage */ - arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0); + arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0); /* fetch NOP, LDM in EXECUTE stage (1st cycle) */ - arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0); + arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0); for (i = 0; i <= 15; i++) { if (mask & (1 << i)) /* nothing fetched, LDM still in EXECUTE (1+i cycle) */ - arm7tdmi_clock_out(jtag_info, core_regs[i], NULL, 0); + arm7tdmi_clock_out_inner(jtag_info, core_regs[i], 0); } - arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0); + arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0); } @@ -644,19 +634,19 @@ void arm7tdmi_write_pc(target_t *target, u32 pc) */ arm7tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x8000, 0, 0), NULL, 0); /* fetch NOP, LDM in DECODE stage */ - arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0); + arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0); /* fetch NOP, LDM in EXECUTE stage (1st cycle) */ - arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0); + arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0); /* nothing fetched, LDM in EXECUTE stage (1st cycle) load register */ - arm7tdmi_clock_out(jtag_info, pc, NULL, 0); + arm7tdmi_clock_out_inner(jtag_info, pc, 0); /* nothing fetched, LDM in EXECUTE stage (2nd cycle) load register */ - arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0); + arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0); /* nothing fetched, LDM in EXECUTE stage (3rd cycle) load register */ - arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0); + arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0); /* fetch NOP, LDM in EXECUTE stage (4th cycle) */ - arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0); + arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0); /* fetch NOP, LDM in EXECUTE stage (5th cycle) */ - arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0); + arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0); } void arm7tdmi_branch_resume(target_t *target) @@ -667,7 +657,7 @@ void arm7tdmi_branch_resume(target_t *target) arm_jtag_t *jtag_info = &arm7_9->jtag_info; arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1); - arm7tdmi_clock_out(jtag_info, ARMV4_5_B(0xfffffa, 0), NULL, 0); + arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_B(0xfffffa, 0), 0); } @@ -738,24 +728,44 @@ void arm7tdmi_build_reg_cache(target_t *target) reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache); /* get pointers to arch-specific information */ armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; (*cache_p) = armv4_5_build_reg_cache(target, armv4_5); armv4_5->core_cache = (*cache_p); - - (*cache_p)->next = embeddedice_build_reg_cache(target, arm7_9); - arm7_9->eice_cache = (*cache_p)->next; - - if (arm7_9->etm_ctx) - { - (*cache_p)->next->next = etm_build_reg_cache(target, jtag_info, arm7_9->etm_ctx); - arm7_9->etm_ctx->reg_cache = (*cache_p)->next->next; - } } -int arm7tdmi_examine(struct command_context_s *cmd_ctx, struct target_s *target) +int arm7tdmi_examine(struct target_s *target) { + int retval; + armv4_5_common_t *armv4_5 = target->arch_info; + arm7_9_common_t *arm7_9 = armv4_5->arch_info; + if (!target->type->examined) + { + /* get pointers to arch-specific information */ + reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache); + reg_cache_t *t=embeddedice_build_reg_cache(target, arm7_9); + if (t==NULL) + return ERROR_FAIL; + + (*cache_p) = t; + arm7_9->eice_cache = (*cache_p); + + if (arm7_9->etm_ctx) + { + arm_jtag_t *jtag_info = &arm7_9->jtag_info; + (*cache_p)->next = etm_build_reg_cache(target, jtag_info, arm7_9->etm_ctx); + arm7_9->etm_ctx->reg_cache = (*cache_p)->next; + } + target->type->examined = 1; + } + if ((retval=embeddedice_setup(target))!=ERROR_OK) + return retval; + if ((retval=arm7_9_setup(target))!=ERROR_OK) + return retval; + if (arm7_9->etm_ctx) + { + if ((retval=etm_setup(target))!=ERROR_OK) + return retval; + } return ERROR_OK; } @@ -768,13 +778,13 @@ int arm7tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *tar } -int arm7tdmi_quit() +int arm7tdmi_quit(void) { return ERROR_OK; } -int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, int chain_pos, char *variant) +int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, jtag_tap_t *tap, const char *variant) { armv4_5_common_t *armv4_5; arm7_9_common_t *arm7_9; @@ -783,7 +793,7 @@ int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, int c armv4_5 = &arm7_9->armv4_5_common; /* prepare JTAG information for the new target */ - arm7_9->jtag_info.chain_pos = chain_pos; + arm7_9->jtag_info.tap = tap; arm7_9->jtag_info.scann_size = 4; /* register arch-specific functions */ @@ -822,8 +832,6 @@ int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, int c arm7_9->arm_bkpt = 0xdeeedeee; arm7_9->thumb_bkpt = 0xdeee; - arm7_9->sw_bkpts_use_wp = 1; - arm7_9->sw_bkpts_enabled = 0; arm7_9->dbgreq_adjust_pc = 2; arm7_9->arch_info = arm7tdmi; @@ -844,37 +852,26 @@ int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, int c return ERROR_OK; } -/* target arm7tdmi */ -int arm7tdmi_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target) -{ - int chain_pos; - char *variant = NULL; - arm7tdmi_common_t *arm7tdmi = malloc(sizeof(arm7tdmi_common_t)); - memset(arm7tdmi, 0, sizeof(*arm7tdmi)); - if (argc < 4) - { - LOG_ERROR("'target arm7tdmi' requires at least one additional argument"); - exit(-1); - } - - chain_pos = strtoul(args[3], NULL, 0); + +int arm7tdmi_target_create( struct target_s *target, Jim_Interp *interp ) +{ + arm7tdmi_common_t *arm7tdmi; - if (argc >= 5) - variant = args[4]; + arm7tdmi = calloc(1,sizeof(arm7tdmi_common_t)); - arm7tdmi_init_arch_info(target, arm7tdmi, chain_pos, variant); + arm7tdmi_init_arch_info(target, arm7tdmi, target->tap, target->variant); return ERROR_OK; } + int arm7tdmi_register_commands(struct command_context_s *cmd_ctx) { int retval; retval = arm7_9_register_commands(cmd_ctx); - return ERROR_OK; + return retval; } -