X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm7_9_common.c;h=e31b0151168287e0cd122f804208dfdef2aea395;hp=af0205d6855b8371d6560dadbf1d63a77e53c337;hb=e66f9aaba94e232f87c725f2fce98cfb3f92679f;hpb=3d6bcf07921753141a3905ee5619724573460cb3

diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index af0205d685..e31b015116 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -700,6 +700,7 @@ int arm7_9_poll(target_t *target)
 		DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, 32));
 		if (target->state == TARGET_UNKNOWN)
 		{
+			target->state = TARGET_RUNNING;
 			WARNING("DBGACK set while target was in unknown state. Reset or initialize target.");
 		}
 		if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
@@ -763,7 +764,6 @@ int arm7_9_assert_reset(target_t *target)
 		{
 			if (retval == ERROR_JTAG_RESET_WOULD_ASSERT_TRST)
 			{
-				WARNING("srst resets test logic, too");
 				retval = jtag_add_reset(1, 1);
 			}
 		}
@@ -774,7 +774,6 @@ int arm7_9_assert_reset(target_t *target)
 		{
 			if (retval == ERROR_JTAG_RESET_WOULD_ASSERT_TRST)
 			{
-				WARNING("srst resets test logic, too");
 				retval = jtag_add_reset(1, 1);
 			}
 			
@@ -1160,7 +1159,7 @@ int arm7_9_debug_entry(target_t *target)
 	ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid;
 	ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).valid;
 
-	if ((retval = jtag->execute_queue()) != ERROR_OK)
+	if ((retval = jtag_execute_queue()) != ERROR_OK)
 		return retval;
 
 	if (arm7_9->post_debug_entry)
@@ -2166,10 +2165,44 @@ int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffe
 
 	arm7_9_resume(target, 0, arm7_9->dcc_working_area->address, 1, 1);
 	
-	for (i = 0; i < count; i++)
+	int little=target->endianness==TARGET_LITTLE_ENDIAN;
+	if (count>2)
 	{
-		embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], target_buffer_get_u32(target, buffer));
-		buffer += 4;
+		/* Handle first & last using standard embeddedice_write_reg and the middle ones w/the
+		   core function repeated. 
+		 */
+		embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
+		buffer+=4;
+		
+		embeddedice_reg_t *ice_reg = arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info;
+		u8 reg_addr = ice_reg->addr & 0x1f;
+		int chain_pos = ice_reg->jtag_info->chain_pos;
+		/* we want the compiler to duplicate the code, which it does not
+		 * do automatically.
+		 */
+		if (little)
+		{
+			for (i = 1; i < count - 1; i++)
+			{
+				embeddedice_write_reg_inner(chain_pos, reg_addr, fast_target_buffer_get_u32(buffer, little));
+				buffer += 4;
+			}
+		} else
+		{
+			for (i = 1; i < count - 1; i++)
+			{
+				embeddedice_write_reg_inner(chain_pos, reg_addr, fast_target_buffer_get_u32(buffer, little));
+				buffer += 4;
+			}
+		}
+		embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
+	} else
+	{
+		for (i = 0; i < count; i++)
+		{
+			embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
+			buffer += 4;
+		}
 	}
 	
 	target->type->halt(target);