X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm7_9_common.c;h=e2eb0d5cd4e4fa1bac72e05b0789e336857aed84;hp=48ba007e6f120246089ec8eae56c8395560e4e62;hb=016e7ebbfa034926c980b4b33b964f6078541690;hpb=e43979e7020ea9d05a3c0a2af444f292eacb6c53
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 48ba007e6f..e2eb0d5cd4 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -2,7 +2,7 @@
* Copyright (C) 2005 by Dominic Rath *
* Dominic.Rath@gmx.de *
* *
- * Copyright (C) 2007,2008 Øyvind Harboe *
+ * Copyright (C) 2007,2008 Ãyvind Harboe *
* oyvind.harboe@zylin.com *
* *
* Copyright (C) 2008 by Spencer Oliver *
@@ -58,8 +58,10 @@ int handle_arm7_9_etm_command(struct command_context_s *cmd_ctx, char *cmd, char
*/
static int arm7_9_clear_watchpoints(arm7_9_common_t *arm7_9)
{
+ LOG_DEBUG("-");
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
+ arm7_9->sw_breakpoint_count = 0;
arm7_9->sw_breakpoints_added = 0;
arm7_9->wp0_used = 0;
arm7_9->wp1_used = arm7_9->wp1_used_default;
@@ -93,6 +95,10 @@ static void arm7_9_assign_wp(arm7_9_common_t *arm7_9, breakpoint_t *breakpoint)
{
LOG_ERROR("BUG: no hardware comparator available");
}
+ LOG_DEBUG("BPID: %d (0x%08" PRIx32 ") using hw wp: %d",
+ breakpoint->unique_id,
+ breakpoint->address,
+ breakpoint->set );
}
/**
@@ -118,11 +124,11 @@ static int arm7_9_set_software_breakpoints(arm7_9_common_t *arm7_9)
/* pick a breakpoint unit */
if (!arm7_9->wp0_used)
{
- arm7_9->sw_breakpoints_added=1;
+ arm7_9->sw_breakpoints_added = 1;
arm7_9->wp0_used = 3;
} else if (!arm7_9->wp1_used)
{
- arm7_9->sw_breakpoints_added=2;
+ arm7_9->sw_breakpoints_added = 2;
arm7_9->wp1_used = 3;
}
else
@@ -131,7 +137,7 @@ static int arm7_9_set_software_breakpoints(arm7_9_common_t *arm7_9)
return ERROR_FAIL;
}
- if (arm7_9->sw_breakpoints_added==1)
+ if (arm7_9->sw_breakpoints_added == 1)
{
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], arm7_9->arm_bkpt);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
@@ -139,7 +145,7 @@ static int arm7_9_set_software_breakpoints(arm7_9_common_t *arm7_9)
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
}
- else if (arm7_9->sw_breakpoints_added==2)
+ else if (arm7_9->sw_breakpoints_added == 2)
{
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], arm7_9->arm_bkpt);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0x0);
@@ -152,6 +158,8 @@ static int arm7_9_set_software_breakpoints(arm7_9_common_t *arm7_9)
LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1");
return ERROR_FAIL;
}
+ LOG_DEBUG("SW BP using hw wp: %d",
+ arm7_9->sw_breakpoints_added );
return jtag_execute_queue();
}
@@ -218,7 +226,12 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
- int retval=ERROR_OK;
+ int retval = ERROR_OK;
+
+ LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32 ", Type: %d" ,
+ breakpoint->unique_id,
+ breakpoint->address,
+ breakpoint->type);
if (target->state != TARGET_HALTED)
{
@@ -232,12 +245,12 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
uint32_t mask = (breakpoint->length == 4) ? 0x3u : 0x1u;
/* reassign a hw breakpoint */
- if (breakpoint->set==0)
+ if (breakpoint->set == 0)
{
arm7_9_assign_wp(arm7_9, breakpoint);
}
- if (breakpoint->set==1)
+ if (breakpoint->set == 1)
{
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], breakpoint->address);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
@@ -245,7 +258,7 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
}
- else if (breakpoint->set==2)
+ else if (breakpoint->set == 2)
{
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], breakpoint->address);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
@@ -259,13 +272,10 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
return ERROR_OK;
}
- retval=jtag_execute_queue();
+ retval = jtag_execute_queue();
}
else if (breakpoint->type == BKPT_SOFT)
{
- if ((retval=arm7_9_set_software_breakpoints(arm7_9))!=ERROR_OK)
- return retval;
-
/* did we already set this breakpoint? */
if (breakpoint->set)
return ERROR_OK;
@@ -318,6 +328,12 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
return ERROR_OK;
}
}
+
+ if ((retval = arm7_9_set_software_breakpoints(arm7_9)) != ERROR_OK)
+ return retval;
+
+ arm7_9->sw_breakpoint_count++;
+
breakpoint->set = 1;
}
@@ -343,6 +359,10 @@ int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32,
+ breakpoint->unique_id,
+ breakpoint->address );
+
if (!breakpoint->set)
{
LOG_WARNING("breakpoint not set");
@@ -351,6 +371,9 @@ int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
if (breakpoint->type == BKPT_HARD)
{
+ LOG_DEBUG("BPID: %d Releasing hw wp: %d",
+ breakpoint->unique_id,
+ breakpoint->set );
if (breakpoint->set == 1)
{
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
@@ -377,7 +400,7 @@ int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
return retval;
}
- if (current_instr==arm7_9->arm_bkpt)
+ if (current_instr == arm7_9->arm_bkpt)
if ((retval = target_write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
{
return retval;
@@ -391,12 +414,26 @@ int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
return retval;
}
- if (current_instr==arm7_9->thumb_bkpt)
+ if (current_instr == arm7_9->thumb_bkpt)
if ((retval = target_write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
{
return retval;
}
}
+
+ if (--arm7_9->sw_breakpoint_count==0)
+ {
+ /* We have removed the last sw breakpoint, clear the hw breakpoint we used to implement it */
+ if (arm7_9->sw_breakpoints_added == 1)
+ {
+ embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0);
+ }
+ else if (arm7_9->sw_breakpoints_added == 2)
+ {
+ embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0);
+ }
+ }
+
breakpoint->set = 0;
}
@@ -423,7 +460,7 @@ int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
return ERROR_TARGET_NOT_HALTED;
}
- if (arm7_9->breakpoint_count==0)
+ if (arm7_9->breakpoint_count == 0)
{
/* make sure we don't have any dangling breakpoints. This is vital upon
* GDB connect/disconnect
@@ -478,7 +515,7 @@ int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
arm7_9->wp_available++;
arm7_9->breakpoint_count--;
- if (arm7_9->breakpoint_count==0)
+ if (arm7_9->breakpoint_count == 0)
{
/* make sure we don't have any dangling breakpoints */
if ((retval = arm7_9_clear_watchpoints(arm7_9)) != ERROR_OK)
@@ -526,7 +563,7 @@ int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], watchpoint->address);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], watchpoint->mask);
- if ( watchpoint->mask != 0xffffffffu )
+ if (watchpoint->mask != 0xffffffffu)
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], watchpoint->value);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
@@ -543,7 +580,7 @@ int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], watchpoint->address);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], watchpoint->mask);
- if ( watchpoint->mask != 0xffffffffu )
+ if (watchpoint->mask != 0xffffffffu)
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], watchpoint->value);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
@@ -700,9 +737,9 @@ int arm7_9_execute_sys_speed(struct target_s *target)
}
arm_jtag_set_instr(jtag_info, 0x4, NULL);
- long long then=timeval_ms();
+ long long then = timeval_ms();
int timeout;
- while (!(timeout=((timeval_ms()-then)>1000)))
+ while (!(timeout = ((timeval_ms()-then) > 1000)))
{
/* read debug status register */
embeddedice_read_reg(dbg_stat);
@@ -711,7 +748,7 @@ int arm7_9_execute_sys_speed(struct target_s *target)
if ((buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
&& (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_SYSCOMP, 1)))
break;
- if (debug_level>=3)
+ if (debug_level >= 3)
{
alive_sleep(100);
} else
@@ -738,7 +775,7 @@ int arm7_9_execute_sys_speed(struct target_s *target)
*/
int arm7_9_execute_fast_sys_speed(struct target_s *target)
{
- static int set=0;
+ static int set = 0;
static uint8_t check_value[4], check_mask[4];
armv4_5_common_t *armv4_5 = target->arch_info;
@@ -764,7 +801,7 @@ int arm7_9_execute_fast_sys_speed(struct target_s *target)
* */
buf_set_u32(check_value, 0, 32, 0x9);
buf_set_u32(check_mask, 0, 32, 0x9);
- set=1;
+ set = 1;
}
/* read debug status register */
@@ -862,11 +899,11 @@ int arm7_9_handle_target_request(void *priv)
* what happens:
*
*
- * State | Action |
- * TARGET_RUNNING | TARGET_RESET | Enters debug mode. If TARGET_RESET, pc may be checked |
- * TARGET_UNKNOWN | Warning is logged |
- * TARGET_DEBUG_RUNNING | Enters debug mode |
- * TARGET_HALTED | Nothing |
+ * State | Action |
+ * TARGET_RUNNING | TARGET_RESET | Enters debug mode. If TARGET_RESET, pc may be checked |
+ * TARGET_UNKNOWN | Warning is logged |
+ * TARGET_DEBUG_RUNNING | Enters debug mode |
+ * TARGET_HALTED | Nothing |
*
*
* If the target does not end up in the halted state, a warning is produced. If
@@ -895,18 +932,19 @@ int arm7_9_poll(target_t *target)
/* LOG_DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, 32));*/
if (target->state == TARGET_UNKNOWN)
{
+ /* Starting OpenOCD with target in debug-halt */
target->state = TARGET_RUNNING;
- LOG_WARNING("DBGACK set while target was in unknown state. Reset or initialize target.");
+ LOG_DEBUG("DBGACK already set during server startup.");
}
if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
{
- int check_pc=0;
+ int check_pc = 0;
if (target->state == TARGET_RESET)
{
if (target->reset_halt)
{
enum reset_types jtag_reset_config = jtag_get_reset_config();
- if ((jtag_reset_config & RESET_SRST_PULLS_TRST)==0)
+ if ((jtag_reset_config & RESET_SRST_PULLS_TRST) == 0)
{
check_pc = 1;
}
@@ -922,7 +960,7 @@ int arm7_9_poll(target_t *target)
{
reg_t *reg = register_get_by_name(target->reg_cache, "pc", 1);
uint32_t t=*((uint32_t *)reg->value);
- if (t!=0)
+ if (t != 0)
{
LOG_ERROR("PC was not 0. Does this target need srst_pulls_trst?");
}
@@ -974,7 +1012,7 @@ int arm7_9_assert_reset(target_t *target)
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
LOG_DEBUG("target->state: %s",
- Jim_Nvp_value2name_simple( nvp_target_state,target->state)->name);
+ target_state_name(target));
enum reset_types jtag_reset_config = jtag_get_reset_config();
if (!(jtag_reset_config & RESET_HAS_SRST))
@@ -983,6 +1021,17 @@ int arm7_9_assert_reset(target_t *target)
return ERROR_FAIL;
}
+ /* at this point trst has been asserted/deasserted once. We want to
+ * program embedded ice while SRST is asserted, but some CPUs gate
+ * the JTAG clock while SRST is asserted
+ */
+ bool srst_asserted = false;
+ if (((jtag_reset_config & RESET_SRST_PULLS_TRST) == 0) && ((jtag_reset_config & RESET_SRST_GATES_JTAG) == 0))
+ {
+ jtag_add_reset(0, 1);
+ srst_asserted = true;
+ }
+
if (target->reset_halt)
{
/*
@@ -996,6 +1045,9 @@ int arm7_9_assert_reset(target_t *target)
{
/* program vector catch register to catch reset vector */
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH], 0x1);
+
+ /* extra runtest added as issues were found with certain ARM9 cores (maybe more) - AT91SAM9260 and STR9 */
+ jtag_add_runtest(1, jtag_get_end_state());
}
else
{
@@ -1012,7 +1064,7 @@ int arm7_9_assert_reset(target_t *target)
if (jtag_reset_config & RESET_SRST_PULLS_TRST)
{
jtag_add_reset(1, 1);
- } else
+ } else if (!srst_asserted)
{
jtag_add_reset(0, 1);
}
@@ -1022,7 +1074,7 @@ int arm7_9_assert_reset(target_t *target)
armv4_5_invalidate_core_regs(target);
- if ((target->reset_halt)&&((jtag_reset_config & RESET_SRST_PULLS_TRST)==0))
+ if ((target->reset_halt) && ((jtag_reset_config & RESET_SRST_PULLS_TRST) == 0))
{
/* debug entry was already prepared in arm7_9_assert_reset() */
target->debug_reason = DBG_REASON_DBGRQ;
@@ -1042,27 +1094,27 @@ int arm7_9_assert_reset(target_t *target)
*/
int arm7_9_deassert_reset(target_t *target)
{
- int retval=ERROR_OK;
+ int retval = ERROR_OK;
LOG_DEBUG("target->state: %s",
- Jim_Nvp_value2name_simple( nvp_target_state,target->state)->name);
+ target_state_name(target));
/* deassert reset lines */
jtag_add_reset(0, 0);
enum reset_types jtag_reset_config = jtag_get_reset_config();
- if (target->reset_halt&&(jtag_reset_config & RESET_SRST_PULLS_TRST)!=0)
+ if (target->reset_halt && (jtag_reset_config & RESET_SRST_PULLS_TRST) != 0)
{
LOG_WARNING("srst pulls trst - can not reset into halted mode. Issuing halt after reset.");
/* set up embedded ice registers again */
if ((retval = target_examine_one(target)) != ERROR_OK)
return retval;
- if ((retval=target_poll(target))!=ERROR_OK)
+ if ((retval = target_poll(target)) != ERROR_OK)
{
return retval;
}
- if ((retval=target_halt(target))!=ERROR_OK)
+ if ((retval = target_halt(target)) != ERROR_OK)
{
return retval;
}
@@ -1147,19 +1199,26 @@ int arm7_9_soft_reset_halt(struct target_s *target)
int i;
int retval;
- if ((retval=target_halt(target))!=ERROR_OK)
+ /* FIX!!! replace some of this code with tcl commands
+ *
+ * halt # the halt command is synchronous
+ * armv4_5 core_state arm
+ *
+ */
+
+ if ((retval = target_halt(target)) != ERROR_OK)
return retval;
- long long then=timeval_ms();
+ long long then = timeval_ms();
int timeout;
- while (!(timeout=((timeval_ms()-then)>1000)))
+ while (!(timeout = ((timeval_ms()-then) > 1000)))
{
if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) != 0)
break;
embeddedice_read_reg(dbg_stat);
- if ((retval=jtag_execute_queue())!=ERROR_OK)
+ if ((retval = jtag_execute_queue()) != ERROR_OK)
return retval;
- if (debug_level>=3)
+ if (debug_level >= 3)
{
alive_sleep(100);
} else
@@ -1246,7 +1305,7 @@ int arm7_9_soft_reset_halt(struct target_s *target)
*/
int arm7_9_halt(target_t *target)
{
- if (target->state==TARGET_RESET)
+ if (target->state == TARGET_RESET)
{
LOG_ERROR("BUG: arm7/9 does not support halt during reset. This is handled in arm7_9_assert_reset()");
return ERROR_OK;
@@ -1257,7 +1316,7 @@ int arm7_9_halt(target_t *target)
reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
LOG_DEBUG("target->state: %s",
- Jim_Nvp_value2name_simple( nvp_target_state,target->state)->name);
+ target_state_name(target));
if (target->state == TARGET_HALTED)
{
@@ -1412,23 +1471,15 @@ int arm7_9_debug_entry(target_t *target)
context[15] -= 3 * 4;
}
- if ((target->debug_reason == DBG_REASON_BREAKPOINT)
- || (target->debug_reason == DBG_REASON_SINGLESTEP)
- || (target->debug_reason == DBG_REASON_WATCHPOINT)
- || (target->debug_reason == DBG_REASON_WPTANDBKPT)
- || ((target->debug_reason == DBG_REASON_DBGRQ) && (arm7_9->use_dbgrq == 0)))
+ if ((target->debug_reason != DBG_REASON_DBGRQ) || (!arm7_9->use_dbgrq))
context[15] -= 3 * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
- else if (target->debug_reason == DBG_REASON_DBGRQ)
- context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
else
- {
- LOG_ERROR("unknown debug reason: %i", target->debug_reason);
- }
+ context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
return ERROR_FAIL;
- for (i=0; i<=15; i++)
+ for (i = 0; i <= 15; i++)
{
LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, context[i]);
buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, context[i]);
@@ -1807,7 +1858,7 @@ int arm7_9_resume(struct target_s *target, int current, uint32_t address, int ha
{
if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
{
- LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 "", breakpoint->address);
+ LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (id: %d)", breakpoint->address, breakpoint->unique_id );
if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK)
{
return retval;
@@ -1819,7 +1870,7 @@ int arm7_9_resume(struct target_s *target, int current, uint32_t address, int ha
{
uint32_t current_opcode;
target_read_u32(target, current_pc, ¤t_opcode);
- LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode);
+ LOG_ERROR("Couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode);
return retval;
}
@@ -1951,7 +2002,7 @@ void arm7_9_enable_eice_step(target_t *target, uint32_t next_pc)
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
- embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~(EICE_W_CTRL_RANGE|EICE_W_CTRL_nOPC) & 0xff);
+ embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~(EICE_W_CTRL_RANGE | EICE_W_CTRL_nOPC) & 0xff);
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], current_pc);
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0);
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff);
@@ -2024,7 +2075,7 @@ int arm7_9_step(struct target_s *target, int current, uint32_t address, int hand
{
uint32_t current_opcode;
target_read_u32(target, current_pc, ¤t_opcode);
- LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode);
+ LOG_ERROR("Couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode);
return retval;
}
@@ -2240,7 +2291,7 @@ int arm7_9_read_memory(struct target_s *target, uint32_t address, uint32_t size,
reg[0] = address;
arm7_9->write_core_regs(target, 0x1, reg);
- int j=0;
+ int j = 0;
switch (size)
{
@@ -2272,7 +2323,7 @@ int arm7_9_read_memory(struct target_s *target, uint32_t address, uint32_t size,
buffer += thisrun_accesses * 4;
num_accesses += thisrun_accesses;
- if ((j++%1024)==0)
+ if ((j++%1024) == 0)
{
keep_alive();
}
@@ -2310,7 +2361,7 @@ int arm7_9_read_memory(struct target_s *target, uint32_t address, uint32_t size,
buffer += thisrun_accesses * 2;
num_accesses += thisrun_accesses;
- if ((j++%1024)==0)
+ if ((j++%1024) == 0)
{
keep_alive();
}
@@ -2347,7 +2398,7 @@ int arm7_9_read_memory(struct target_s *target, uint32_t address, uint32_t size,
buffer += thisrun_accesses * 1;
num_accesses += thisrun_accesses;
- if ((j++%1024)==0)
+ if ((j++%1024) == 0)
{
keep_alive();
}
@@ -2362,7 +2413,7 @@ int arm7_9_read_memory(struct target_s *target, uint32_t address, uint32_t size,
if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
return ERROR_FAIL;
- for (i=0; i<=last_reg; i++)
+ for (i = 0; i <= last_reg; i++)
ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid;
arm7_9->read_xpsr(target, &cpsr, 0);
@@ -2545,7 +2596,7 @@ int arm7_9_write_memory(struct target_s *target, uint32_t address, uint32_t size
if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
return ERROR_FAIL;
- for (i=0; i<=last_reg; i++)
+ for (i = 0; i <= last_reg; i++)
ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid;
arm7_9->read_xpsr(target, &cpsr, 0);
@@ -2576,18 +2627,18 @@ static int arm7_9_dcc_completion(struct target_s *target, uint32_t exit_point, i
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
- if ((retval=target_wait_state(target, TARGET_DEBUG_RUNNING, 500))!=ERROR_OK)
+ if ((retval = target_wait_state(target, TARGET_DEBUG_RUNNING, 500)) != ERROR_OK)
return retval;
- int little=target->endianness==TARGET_LITTLE_ENDIAN;
- int count=dcc_count;
- uint8_t *buffer=dcc_buffer;
- if (count>2)
+ int little = target->endianness == TARGET_LITTLE_ENDIAN;
+ int count = dcc_count;
+ uint8_t *buffer = dcc_buffer;
+ if (count > 2)
{
/* Handle first & last using standard embeddedice_write_reg and the middle ones w/the
* core function repeated. */
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
- buffer+=4;
+ buffer += 4;
embeddedice_reg_t *ice_reg = arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info;
uint8_t reg_addr = ice_reg->addr & 0x1f;
@@ -2617,8 +2668,21 @@ static int arm7_9_dcc_completion(struct target_s *target, uint32_t exit_point, i
static const uint32_t dcc_code[] =
{
- /* MRC TST BNE MRC STR B */
- 0xee101e10, 0xe3110001, 0x0afffffc, 0xee111e10, 0xe4801004, 0xeafffff9
+ /* r0 == input, points to memory buffer
+ * r1 == scratch
+ */
+
+ /* spin until DCC control (c0) reports data arrived */
+ 0xee101e10, /* w: mrc p14, #0, r1, c0, c0 */
+ 0xe3110001, /* tst r1, #1 */
+ 0x0afffffc, /* bne w */
+
+ /* read word from DCC (c1), write to memory */
+ 0xee111e10, /* mrc p14, #0, r1, c1, c0 */
+ 0xe4801004, /* str r1, [r0], #4 */
+
+ /* repeat */
+ 0xeafffff9 /* b w */
};
int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target_s *target, uint32_t exit_point, int timeout_ms, void *arch_info));
@@ -2669,18 +2733,18 @@ int arm7_9_bulk_write_memory(target_t *target, uint32_t address, uint32_t count,
buf_set_u32(reg_params[0].value, 0, 32, address);
- dcc_count=count;
- dcc_buffer=buffer;
+ dcc_count = count;
+ dcc_buffer = buffer;
retval = armv4_5_run_algorithm_inner(target, 0, NULL, 1, reg_params,
- arm7_9->dcc_working_area->address, arm7_9->dcc_working_area->address+6*4, 20*1000, &armv4_5_info, arm7_9_dcc_completion);
+ arm7_9->dcc_working_area->address, arm7_9->dcc_working_area->address + 6*4, 20*1000, &armv4_5_info, arm7_9_dcc_completion);
- if (retval==ERROR_OK)
+ if (retval == ERROR_OK)
{
- uint32_t endaddress=buf_get_u32(reg_params[0].value, 0, 32);
- if (endaddress!=(address+count*4))
+ uint32_t endaddress = buf_get_u32(reg_params[0].value, 0, 32);
+ if (endaddress != (address + count*4))
{
- LOG_ERROR("DCC write failed, expected end address 0x%08" PRIx32 " got 0x%0" PRIx32 "", (address+count*4), endaddress);
- retval=ERROR_FAIL;
+ LOG_ERROR("DCC write failed, expected end address 0x%08" PRIx32 " got 0x%0" PRIx32 "", (address + count*4), endaddress);
+ retval = ERROR_FAIL;
}
}
@@ -2696,7 +2760,7 @@ int arm7_9_checksum_memory(struct target_s *target, uint32_t address, uint32_t c
reg_param_t reg_params[2];
int retval;
- uint32_t arm7_9_crc_code[] = {
+ static const uint32_t arm7_9_crc_code[] = {
0xE1A02000, /* mov r2, r0 */
0xE3E00000, /* mov r0, #0xffffffff */
0xE1A03001, /* mov r3, r1 */
@@ -2734,7 +2798,7 @@ int arm7_9_checksum_memory(struct target_s *target, uint32_t address, uint32_t c
/* convert flash writing code into a buffer in target endianness */
for (i = 0; i < (sizeof(arm7_9_crc_code)/sizeof(uint32_t)); i++)
{
- if ((retval=target_write_u32(target, crc_algorithm->address + i*sizeof(uint32_t), arm7_9_crc_code[i]))!=ERROR_OK)
+ if ((retval = target_write_u32(target, crc_algorithm->address + i*sizeof(uint32_t), arm7_9_crc_code[i])) != ERROR_OK)
{
return retval;
}
@@ -2778,15 +2842,15 @@ int arm7_9_blank_check_memory(struct target_s *target, uint32_t address, uint32_
int retval;
uint32_t i;
- uint32_t erase_check_code[] =
+ static const uint32_t erase_check_code[] =
{
- /* loop: */
- 0xe4d03001, /* ldrb r3, [r0], #1 */
- 0xe0022003, /* and r2, r2, r3 */
- 0xe2511001, /* subs r1, r1, #1 */
- 0x1afffffb, /* bne loop */
- /* end: */
- 0xeafffffe /* b end */
+ /* loop: */
+ 0xe4d03001, /* ldrb r3, [r0], #1 */
+ 0xe0022003, /* and r2, r2, r3 */
+ 0xe2511001, /* subs r1, r1, #1 */
+ 0x1afffffb, /* bne loop */
+ /* end: */
+ 0xeafffffe /* b end */
};
/* make sure we have a working area */
@@ -2842,17 +2906,17 @@ int arm7_9_register_commands(struct command_context_s *cmd_ctx)
arm7_9_cmd = register_command(cmd_ctx, NULL, "arm7_9", NULL, COMMAND_ANY, "arm7/9 specific commands");
- register_command(cmd_ctx, arm7_9_cmd, "write_xpsr", handle_arm7_9_write_xpsr_command, COMMAND_EXEC, "write program status register ");
- register_command(cmd_ctx, arm7_9_cmd, "write_xpsr_im8", handle_arm7_9_write_xpsr_im8_command, COMMAND_EXEC, "write program status register <8bit immediate> ");
+ register_command(cmd_ctx, arm7_9_cmd, "write_xpsr", handle_arm7_9_write_xpsr_command, COMMAND_EXEC, "write program status register ");
+ register_command(cmd_ctx, arm7_9_cmd, "write_xpsr_im8", handle_arm7_9_write_xpsr_im8_command, COMMAND_EXEC, "write program status register <8bit immediate> ");
register_command(cmd_ctx, arm7_9_cmd, "write_core_reg", handle_arm7_9_write_core_reg_command, COMMAND_EXEC, "write core register ");
register_command(cmd_ctx, arm7_9_cmd, "dbgrq", handle_arm7_9_dbgrq_command,
- COMMAND_ANY, "use EmbeddedICE dbgrq instead of breakpoint for target halt requests ");
+ COMMAND_ANY, "use EmbeddedICE dbgrq instead of breakpoint for target halt requests ");
register_command(cmd_ctx, arm7_9_cmd, "fast_memory_access", handle_arm7_9_fast_memory_access_command,
- COMMAND_ANY, "use fast memory accesses instead of slower but potentially safer accesses ");
+ COMMAND_ANY, "use fast memory accesses instead of slower but potentially safer accesses ");
register_command(cmd_ctx, arm7_9_cmd, "dcc_downloads", handle_arm7_9_dcc_downloads_command,
- COMMAND_ANY, "use DCC downloads for larger memory writes ");
+ COMMAND_ANY, "use DCC downloads for larger memory writes ");
armv4_5_register_commands(cmd_ctx);
@@ -2884,7 +2948,7 @@ int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cm
if (argc < 2)
{
- command_print(cmd_ctx, "usage: write_xpsr ");
+ command_print(cmd_ctx, "usage: write_xpsr ");
return ERROR_OK;
}
@@ -2929,7 +2993,7 @@ int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char
if (argc < 3)
{
- command_print(cmd_ctx, "usage: write_xpsr_im8 ");
+ command_print(cmd_ctx, "usage: write_xpsr_im8 ");
return ERROR_OK;
}
@@ -3005,7 +3069,7 @@ int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, ch
}
else
{
- command_print(cmd_ctx, "usage: arm7_9 dbgrq ");
+ command_print(cmd_ctx, "usage: arm7_9 dbgrq ");
}
}
@@ -3038,7 +3102,7 @@ int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx,
}
else
{
- command_print(cmd_ctx, "usage: arm7_9 fast_memory_access ");
+ command_print(cmd_ctx, "usage: arm7_9 fast_memory_access ");
}
}
@@ -3071,7 +3135,7 @@ int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char
}
else
{
- command_print(cmd_ctx, "usage: arm7_9 dcc_downloads ");
+ command_print(cmd_ctx, "usage: arm7_9 dcc_downloads ");
}
}
@@ -3095,6 +3159,7 @@ int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9)
arm7_9->wp_available = 0; /* this is set up in arm7_9_clear_watchpoints() */
arm7_9->wp_available_max = 2;
arm7_9->sw_breakpoints_added = 0;
+ arm7_9->sw_breakpoint_count = 0;
arm7_9->breakpoint_count = 0;
arm7_9->wp0_used = 0;
arm7_9->wp1_used = 0;